| SCORE |
LINE |
COND |
TOGGLE |
FSM |
BRANCH |
ASSERT |
GROUP |
|
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
| 40.74 |
40.74 |
45.01 |
45.01 |
43.02 |
43.02 |
31.88 |
31.88 |
|
|
57.87 |
57.87 |
59.62 |
59.62 |
7.02 |
7.02 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2641963750 |
| 51.44 |
10.70 |
53.25 |
8.24 |
52.41 |
9.39 |
35.18 |
3.30 |
|
|
66.39 |
8.51 |
85.84 |
26.22 |
15.57 |
8.55 |
/workspace/coverage/default/2.chip_jtag_csr_rw.2078388420 |
| 60.04 |
8.60 |
53.29 |
0.04 |
52.46 |
0.06 |
39.30 |
4.12 |
|
|
66.39 |
0.01 |
85.84 |
0.00 |
62.94 |
47.37 |
/workspace/coverage/default/2.chip_sw_alert_test.1561702682 |
| 65.71 |
5.67 |
64.83 |
11.54 |
58.50 |
6.04 |
43.72 |
4.42 |
|
|
69.72 |
3.33 |
90.38 |
4.55 |
67.11 |
4.17 |
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.44534992 |
| 70.14 |
4.43 |
74.90 |
10.07 |
64.96 |
6.45 |
44.92 |
1.19 |
|
|
78.56 |
8.84 |
90.38 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.81235782 |
| 73.35 |
3.21 |
74.91 |
0.01 |
64.98 |
0.02 |
64.15 |
19.24 |
|
|
78.58 |
0.02 |
90.38 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.441931367 |
| 75.27 |
1.92 |
77.23 |
2.33 |
67.83 |
2.86 |
67.87 |
3.71 |
|
|
80.84 |
2.26 |
90.73 |
0.35 |
67.11 |
0.00 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.4227809854 |
| 77.16 |
1.89 |
80.67 |
3.44 |
71.69 |
3.86 |
68.17 |
0.30 |
|
|
84.58 |
3.74 |
90.73 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1033013839 |
| 78.47 |
1.31 |
80.96 |
0.29 |
71.84 |
0.15 |
75.23 |
7.06 |
|
|
84.75 |
0.18 |
90.91 |
0.17 |
67.11 |
0.00 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2298722843 |
| 79.72 |
1.25 |
83.05 |
2.09 |
74.34 |
2.50 |
75.47 |
0.25 |
|
|
87.08 |
2.32 |
91.26 |
0.35 |
67.11 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.508379240 |
| 80.97 |
1.25 |
85.37 |
2.32 |
76.25 |
1.91 |
76.45 |
0.98 |
|
|
89.36 |
2.29 |
91.26 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.2355578299 |
| 81.77 |
0.80 |
86.32 |
0.95 |
76.91 |
0.66 |
78.12 |
1.66 |
|
|
90.33 |
0.97 |
91.61 |
0.35 |
67.32 |
0.22 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3937940380 |
| 82.53 |
0.76 |
86.67 |
0.35 |
77.08 |
0.17 |
78.13 |
0.01 |
|
|
90.52 |
0.19 |
95.45 |
3.85 |
67.32 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4016050770 |
| 83.18 |
0.65 |
87.75 |
1.08 |
78.09 |
1.01 |
78.95 |
0.81 |
|
|
91.27 |
0.75 |
95.45 |
0.00 |
67.54 |
0.22 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3370897953 |
| 83.80 |
0.62 |
88.87 |
1.11 |
78.98 |
0.88 |
79.65 |
0.71 |
|
|
92.29 |
1.02 |
95.45 |
0.00 |
67.54 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.1777260582 |
| 84.35 |
0.55 |
89.78 |
0.91 |
79.87 |
0.89 |
80.94 |
1.29 |
|
|
92.48 |
0.19 |
95.45 |
0.00 |
67.54 |
0.00 |
/workspace/coverage/default/0.chip_jtag_csr_rw.3884699716 |
| 84.83 |
0.49 |
90.35 |
0.57 |
80.35 |
0.48 |
81.69 |
0.75 |
|
|
93.06 |
0.58 |
95.98 |
0.52 |
67.54 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2331742198 |
| 85.16 |
0.33 |
90.36 |
0.01 |
80.36 |
0.01 |
83.67 |
1.98 |
|
|
93.06 |
0.00 |
95.98 |
0.00 |
67.54 |
0.00 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2885155931 |
| 85.47 |
0.31 |
90.92 |
0.55 |
80.84 |
0.48 |
84.07 |
0.40 |
|
|
93.48 |
0.41 |
95.98 |
0.00 |
67.54 |
0.00 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.488880422 |
| 85.77 |
0.30 |
90.94 |
0.03 |
80.86 |
0.02 |
84.10 |
0.03 |
|
|
93.50 |
0.02 |
96.15 |
0.17 |
69.08 |
1.54 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.994527174 |
| 85.98 |
0.21 |
90.94 |
0.00 |
80.86 |
0.00 |
85.34 |
1.24 |
|
|
93.50 |
0.00 |
96.15 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3320441371 |
| 86.16 |
0.18 |
91.49 |
0.54 |
81.00 |
0.13 |
85.38 |
0.04 |
|
|
93.53 |
0.03 |
96.50 |
0.35 |
69.08 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.318416125 |
| 86.31 |
0.15 |
91.57 |
0.08 |
81.08 |
0.08 |
85.66 |
0.29 |
|
|
93.59 |
0.06 |
96.68 |
0.17 |
69.30 |
0.22 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3802796171 |
| 86.46 |
0.15 |
91.78 |
0.21 |
81.40 |
0.32 |
86.01 |
0.35 |
|
|
93.59 |
0.00 |
96.68 |
0.00 |
69.30 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3768198612 |
| 86.58 |
0.13 |
91.80 |
0.02 |
81.74 |
0.34 |
86.01 |
0.00 |
|
|
93.98 |
0.39 |
96.68 |
0.00 |
69.30 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.5989140 |
| 86.70 |
0.12 |
91.83 |
0.03 |
81.77 |
0.04 |
86.46 |
0.45 |
|
|
94.00 |
0.02 |
96.85 |
0.17 |
69.30 |
0.00 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.3557572305 |
| 86.82 |
0.11 |
91.85 |
0.01 |
81.77 |
0.00 |
87.12 |
0.66 |
|
|
94.00 |
0.00 |
96.85 |
0.00 |
69.30 |
0.00 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3373562805 |
| 86.92 |
0.10 |
91.85 |
0.00 |
81.77 |
0.00 |
87.74 |
0.62 |
|
|
94.00 |
0.00 |
96.85 |
0.00 |
69.30 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.638966128 |
| 87.00 |
0.08 |
92.01 |
0.16 |
81.88 |
0.11 |
87.83 |
0.09 |
|
|
94.13 |
0.12 |
96.85 |
0.00 |
69.30 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2689825135 |
| 87.08 |
0.08 |
92.03 |
0.03 |
81.90 |
0.01 |
87.83 |
0.01 |
|
|
94.15 |
0.02 |
97.03 |
0.17 |
69.52 |
0.22 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.1253855831 |
| 87.15 |
0.07 |
92.03 |
0.00 |
81.90 |
0.00 |
88.28 |
0.45 |
|
|
94.15 |
0.00 |
97.03 |
0.00 |
69.52 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1793154295 |
| 87.22 |
0.07 |
92.04 |
0.01 |
81.93 |
0.03 |
88.28 |
0.00 |
|
|
94.16 |
0.01 |
97.20 |
0.17 |
69.74 |
0.22 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2336749372 |
| 87.30 |
0.07 |
92.04 |
0.01 |
81.94 |
0.01 |
88.29 |
0.01 |
|
|
94.17 |
0.01 |
97.38 |
0.17 |
69.96 |
0.22 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.2573705485 |
| 87.36 |
0.07 |
92.17 |
0.13 |
81.94 |
0.01 |
88.56 |
0.27 |
|
|
94.18 |
0.02 |
97.38 |
0.00 |
69.96 |
0.00 |
/workspace/coverage/default/3.chip_tap_straps_rma.3258703357 |
| 87.42 |
0.06 |
92.18 |
0.01 |
81.94 |
0.00 |
88.68 |
0.12 |
|
|
94.18 |
0.00 |
97.38 |
0.00 |
70.18 |
0.22 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.4276657510 |
| 87.48 |
0.05 |
92.18 |
0.00 |
81.94 |
0.00 |
89.01 |
0.33 |
|
|
94.18 |
0.00 |
97.38 |
0.00 |
70.18 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3265918752 |
| 87.53 |
0.05 |
92.18 |
0.00 |
81.94 |
0.00 |
89.33 |
0.32 |
|
|
94.18 |
0.00 |
97.38 |
0.00 |
70.18 |
0.00 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2833960266 |
| 87.58 |
0.05 |
92.18 |
0.00 |
82.07 |
0.13 |
89.33 |
0.00 |
|
|
94.33 |
0.15 |
97.38 |
0.00 |
70.18 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3796175328 |
| 87.62 |
0.05 |
92.18 |
0.00 |
82.07 |
0.01 |
89.38 |
0.05 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
70.39 |
0.22 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1671005042 |
| 87.66 |
0.04 |
92.18 |
0.00 |
82.07 |
0.00 |
89.41 |
0.02 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
70.61 |
0.22 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.3305688204 |
| 87.70 |
0.04 |
92.18 |
0.00 |
82.07 |
0.00 |
89.41 |
0.01 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
70.83 |
0.22 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3705468750 |
| 87.74 |
0.04 |
92.18 |
0.00 |
82.07 |
0.00 |
89.42 |
0.01 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
71.05 |
0.22 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.3260315192 |
| 87.77 |
0.04 |
92.18 |
0.00 |
82.08 |
0.01 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
71.27 |
0.22 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.3142971951 |
| 87.81 |
0.04 |
92.18 |
0.00 |
82.08 |
0.01 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
71.49 |
0.22 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.1113658235 |
| 87.85 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
71.71 |
0.22 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2288640528 |
| 87.88 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
71.93 |
0.22 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.112599690 |
| 87.92 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
72.15 |
0.22 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1150353326 |
| 87.96 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
72.37 |
0.22 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.2045699845 |
| 87.99 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
72.59 |
0.22 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383396198 |
| 88.03 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
72.81 |
0.22 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.328260611 |
| 88.07 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
73.03 |
0.22 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.3955154268 |
| 88.10 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
73.25 |
0.22 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.2406809978 |
| 88.14 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
73.46 |
0.22 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.4155528571 |
| 88.18 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
73.68 |
0.22 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3027680755 |
| 88.21 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
73.90 |
0.22 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.4110952745 |
| 88.25 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
74.12 |
0.22 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.8248435 |
| 88.29 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
74.34 |
0.22 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2709905806 |
| 88.32 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
74.56 |
0.22 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.1023005207 |
| 88.36 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
74.78 |
0.22 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3564932724 |
| 88.40 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
75.00 |
0.22 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.1122215378 |
| 88.43 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
75.22 |
0.22 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3354316075 |
| 88.47 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
75.44 |
0.22 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.3932580171 |
| 88.51 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
75.66 |
0.22 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.284163914 |
| 88.54 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
75.88 |
0.22 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.1776595673 |
| 88.58 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
76.10 |
0.22 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3646540884 |
| 88.62 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
76.32 |
0.22 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.3335667906 |
| 88.65 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
76.54 |
0.22 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3782142359 |
| 88.69 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
76.75 |
0.22 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.566347359 |
| 88.73 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
76.97 |
0.22 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.949102517 |
| 88.76 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
77.19 |
0.22 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.3127475785 |
| 88.80 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
77.41 |
0.22 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2496370734 |
| 88.84 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
77.63 |
0.22 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.385468560 |
| 88.87 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
77.85 |
0.22 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4077092725 |
| 88.91 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
78.07 |
0.22 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1692595208 |
| 88.94 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
78.29 |
0.22 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3565828345 |
| 88.98 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
78.51 |
0.22 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.1154776199 |
| 89.02 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
78.73 |
0.22 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.3708654047 |
| 89.05 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
78.95 |
0.22 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1203663206 |
| 89.09 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
79.17 |
0.22 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1540886913 |
| 89.13 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
79.39 |
0.22 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.483755946 |
| 89.16 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
79.61 |
0.22 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2043664124 |
| 89.20 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
79.82 |
0.22 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.4254167066 |
| 89.24 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
80.04 |
0.22 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.638892634 |
| 89.27 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
80.26 |
0.22 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.932287948 |
| 89.31 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
80.48 |
0.22 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.2588306410 |
| 89.35 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
80.70 |
0.22 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3032226398 |
| 89.38 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
80.92 |
0.22 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.1841523450 |
| 89.42 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
81.14 |
0.22 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.819750227 |
| 89.46 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
81.36 |
0.22 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.976842617 |
| 89.49 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
81.58 |
0.22 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.3350633574 |
| 89.53 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
81.80 |
0.22 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1718127100 |
| 89.57 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
82.02 |
0.22 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2049405619 |
| 89.60 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
82.24 |
0.22 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.452889457 |
| 89.64 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
82.46 |
0.22 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.2022573101 |
| 89.68 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
82.68 |
0.22 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1815937787 |
| 89.71 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
82.89 |
0.22 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2096120532 |
| 89.75 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
83.11 |
0.22 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3468714284 |
| 89.79 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
83.33 |
0.22 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.517583596 |
| 89.82 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
83.55 |
0.22 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2889986428 |
| 89.86 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
83.77 |
0.22 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2467472937 |
| 89.90 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
83.99 |
0.22 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1890721779 |
| 89.93 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
84.21 |
0.22 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.381053137 |
| 89.97 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
84.43 |
0.22 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1718890313 |
| 90.00 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
84.65 |
0.22 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1535061922 |
| 90.04 |
0.04 |
92.18 |
0.00 |
82.08 |
0.00 |
89.42 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
84.87 |
0.22 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3109487174 |
| 90.07 |
0.03 |
92.18 |
0.00 |
82.08 |
0.00 |
89.62 |
0.20 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1248120320 |
| 90.11 |
0.03 |
92.18 |
0.00 |
82.28 |
0.19 |
89.62 |
0.00 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.1075464342 |
| 90.14 |
0.03 |
92.18 |
0.00 |
82.28 |
0.00 |
89.81 |
0.19 |
|
|
94.33 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.4074666872 |
| 90.17 |
0.03 |
92.23 |
0.05 |
82.38 |
0.11 |
89.81 |
0.00 |
|
|
94.36 |
0.03 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2540038751 |
| 90.20 |
0.03 |
92.26 |
0.04 |
82.44 |
0.06 |
89.86 |
0.05 |
|
|
94.41 |
0.05 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3963501025 |
| 90.23 |
0.03 |
92.26 |
0.00 |
82.44 |
0.00 |
89.86 |
0.00 |
|
|
94.41 |
0.00 |
97.55 |
0.17 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3262157530 |
| 90.26 |
0.03 |
92.33 |
0.07 |
82.47 |
0.03 |
89.87 |
0.01 |
|
|
94.46 |
0.05 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.356980697 |
| 90.28 |
0.02 |
92.39 |
0.06 |
82.53 |
0.06 |
89.87 |
0.00 |
|
|
94.48 |
0.02 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2011290648 |
| 90.31 |
0.02 |
92.43 |
0.04 |
82.56 |
0.03 |
89.90 |
0.02 |
|
|
94.52 |
0.04 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3985346751 |
| 90.33 |
0.02 |
92.48 |
0.06 |
82.63 |
0.06 |
89.90 |
0.00 |
|
|
94.54 |
0.02 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2586649680 |
| 90.35 |
0.02 |
92.54 |
0.05 |
82.68 |
0.05 |
89.91 |
0.01 |
|
|
94.56 |
0.02 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1778100333 |
| 90.37 |
0.02 |
92.59 |
0.06 |
82.74 |
0.06 |
89.91 |
0.00 |
|
|
94.58 |
0.02 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3111492506 |
| 90.39 |
0.02 |
92.62 |
0.03 |
82.74 |
0.01 |
89.99 |
0.08 |
|
|
94.58 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.269205072 |
| 90.41 |
0.02 |
92.63 |
0.01 |
82.76 |
0.02 |
90.05 |
0.06 |
|
|
94.60 |
0.02 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1844161054 |
| 90.43 |
0.02 |
92.63 |
0.00 |
82.86 |
0.10 |
90.05 |
0.00 |
|
|
94.60 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.2940079409 |
| 90.44 |
0.02 |
92.63 |
0.00 |
82.86 |
0.00 |
90.15 |
0.10 |
|
|
94.60 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.876420692 |
| 90.46 |
0.01 |
92.70 |
0.07 |
82.87 |
0.01 |
90.15 |
0.01 |
|
|
94.60 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.836990933 |
| 90.47 |
0.01 |
92.70 |
0.00 |
82.95 |
0.08 |
90.15 |
0.00 |
|
|
94.60 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.1733729048 |
| 90.48 |
0.01 |
92.70 |
0.00 |
82.99 |
0.05 |
90.17 |
0.02 |
|
|
94.60 |
0.01 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1779223818 |
| 90.49 |
0.01 |
92.71 |
0.01 |
83.03 |
0.04 |
90.17 |
0.00 |
|
|
94.63 |
0.02 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2121354387 |
| 90.51 |
0.01 |
92.71 |
0.00 |
83.03 |
0.00 |
90.24 |
0.07 |
|
|
94.63 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2064319185 |
| 90.52 |
0.01 |
92.74 |
0.03 |
83.04 |
0.01 |
90.28 |
0.04 |
|
|
94.63 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.196687523 |
| 90.53 |
0.01 |
92.74 |
0.00 |
83.04 |
0.00 |
90.34 |
0.07 |
|
|
94.63 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3899512822 |
| 90.54 |
0.01 |
92.75 |
0.01 |
83.06 |
0.02 |
90.35 |
0.01 |
|
|
94.65 |
0.02 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4122714652 |
| 90.55 |
0.01 |
92.77 |
0.02 |
83.07 |
0.01 |
90.36 |
0.01 |
|
|
94.67 |
0.02 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1618002570 |
| 90.56 |
0.01 |
92.77 |
0.00 |
83.07 |
0.00 |
90.41 |
0.05 |
|
|
94.67 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_init.2836076754 |
| 90.56 |
0.01 |
92.77 |
0.00 |
83.07 |
0.00 |
90.45 |
0.04 |
|
|
94.67 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.4038192974 |
| 90.57 |
0.01 |
92.77 |
0.00 |
83.07 |
0.01 |
90.49 |
0.04 |
|
|
94.67 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.120903580 |
| 90.58 |
0.01 |
92.77 |
0.00 |
83.10 |
0.02 |
90.51 |
0.02 |
|
|
94.67 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_gpio.616818358 |
| 90.58 |
0.01 |
92.81 |
0.03 |
83.10 |
0.01 |
90.51 |
0.00 |
|
|
94.67 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.868459599 |
| 90.59 |
0.01 |
92.81 |
0.00 |
83.10 |
0.00 |
90.54 |
0.04 |
|
|
94.67 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.825393970 |
| 90.60 |
0.01 |
92.81 |
0.00 |
83.10 |
0.00 |
90.57 |
0.03 |
|
|
94.68 |
0.01 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4117604207 |
| 90.60 |
0.01 |
92.81 |
0.00 |
83.13 |
0.03 |
90.57 |
0.00 |
|
|
94.68 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.4083898760 |
| 90.61 |
0.01 |
92.81 |
0.00 |
83.15 |
0.01 |
90.57 |
0.00 |
|
|
94.69 |
0.02 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3988530719 |
| 90.61 |
0.01 |
92.81 |
0.00 |
83.15 |
0.00 |
90.60 |
0.03 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.796010530 |
| 90.62 |
0.01 |
92.81 |
0.00 |
83.15 |
0.00 |
90.63 |
0.03 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.363619502 |
| 90.62 |
0.01 |
92.81 |
0.00 |
83.16 |
0.02 |
90.63 |
0.01 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3975374319 |
| 90.62 |
0.01 |
92.81 |
0.00 |
83.19 |
0.02 |
90.63 |
0.00 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.3187786024 |
| 90.63 |
0.01 |
92.81 |
0.00 |
83.20 |
0.01 |
90.65 |
0.01 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1359181936 |
| 90.63 |
0.01 |
92.81 |
0.01 |
83.21 |
0.01 |
90.65 |
0.01 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3743089091 |
| 90.63 |
0.01 |
92.81 |
0.00 |
83.21 |
0.00 |
90.67 |
0.02 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2107529427 |
| 90.64 |
0.01 |
92.83 |
0.02 |
83.21 |
0.00 |
90.67 |
0.00 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.2304661000 |
| 90.64 |
0.01 |
92.83 |
0.00 |
83.21 |
0.00 |
90.69 |
0.02 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1673238219 |
| 90.64 |
0.01 |
92.84 |
0.01 |
83.21 |
0.01 |
90.69 |
0.01 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.381058746 |
| 90.64 |
0.01 |
92.84 |
0.01 |
83.21 |
0.01 |
90.70 |
0.01 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.742784506 |
| 90.65 |
0.01 |
92.85 |
0.01 |
83.22 |
0.01 |
90.70 |
0.01 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.1092296883 |
| 90.65 |
0.01 |
92.85 |
0.00 |
83.23 |
0.01 |
90.70 |
0.00 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_gpio.892090223 |
| 90.65 |
0.01 |
92.85 |
0.00 |
83.23 |
0.00 |
90.72 |
0.01 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_jtag_mem_access.2100568943 |
| 90.65 |
0.01 |
92.85 |
0.00 |
83.23 |
0.00 |
90.73 |
0.01 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3456040887 |
| 90.66 |
0.01 |
92.85 |
0.01 |
83.23 |
0.00 |
90.74 |
0.01 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3066604356 |
| 90.66 |
0.01 |
92.86 |
0.01 |
83.23 |
0.00 |
90.74 |
0.01 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.514242568 |
| 90.66 |
0.01 |
92.86 |
0.00 |
83.24 |
0.01 |
90.74 |
0.00 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.9131266 |
| 90.66 |
0.01 |
92.86 |
0.00 |
83.25 |
0.01 |
90.74 |
0.00 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2620581548 |
| 90.66 |
0.01 |
92.86 |
0.00 |
83.26 |
0.01 |
90.74 |
0.00 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4220485648 |
| 90.67 |
0.01 |
92.86 |
0.00 |
83.27 |
0.01 |
90.74 |
0.00 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.359522452 |
| 90.67 |
0.01 |
92.86 |
0.00 |
83.29 |
0.01 |
90.74 |
0.00 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.3474911229 |
| 90.67 |
0.01 |
92.86 |
0.00 |
83.29 |
0.00 |
90.75 |
0.01 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3971500255 |
| 90.67 |
0.01 |
92.86 |
0.00 |
83.29 |
0.00 |
90.76 |
0.01 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.382668874 |
| 90.67 |
0.01 |
92.86 |
0.00 |
83.29 |
0.00 |
90.77 |
0.01 |
|
|
94.69 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.795651379 |
| 90.67 |
0.01 |
92.86 |
0.00 |
83.29 |
0.00 |
90.77 |
0.00 |
|
|
94.70 |
0.01 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_tap_straps_dev.3833338187 |
| 90.67 |
0.01 |
92.86 |
0.00 |
83.29 |
0.01 |
90.77 |
0.00 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2649624245 |
| 90.68 |
0.01 |
92.86 |
0.00 |
83.29 |
0.00 |
90.78 |
0.01 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3916587778 |
| 90.68 |
0.01 |
92.86 |
0.00 |
83.29 |
0.00 |
90.79 |
0.01 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.4217864204 |
| 90.68 |
0.01 |
92.86 |
0.00 |
83.29 |
0.00 |
90.79 |
0.01 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1367031245 |
| 90.68 |
0.01 |
92.86 |
0.00 |
83.29 |
0.00 |
90.80 |
0.01 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1222971515 |
| 90.68 |
0.01 |
92.86 |
0.00 |
83.29 |
0.00 |
90.80 |
0.01 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1190450356 |
| 90.68 |
0.01 |
92.86 |
0.00 |
83.29 |
0.00 |
90.81 |
0.01 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3497117934 |
| 90.68 |
0.01 |
92.86 |
0.00 |
83.29 |
0.00 |
90.81 |
0.01 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.578102965 |
| 90.68 |
0.01 |
92.86 |
0.00 |
83.30 |
0.01 |
90.81 |
0.00 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.1452615131 |
| 90.68 |
0.01 |
92.86 |
0.00 |
83.30 |
0.01 |
90.81 |
0.00 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.937845547 |
| 90.68 |
0.01 |
92.86 |
0.00 |
83.30 |
0.01 |
90.81 |
0.00 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3929796247 |
| 90.68 |
0.01 |
92.86 |
0.00 |
83.31 |
0.01 |
90.81 |
0.00 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.374430456 |
| 90.68 |
0.01 |
92.86 |
0.00 |
83.31 |
0.00 |
90.81 |
0.01 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.2521961132 |
| 90.68 |
0.01 |
92.86 |
0.00 |
83.31 |
0.00 |
90.82 |
0.01 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3335553016 |
| 90.68 |
0.01 |
92.86 |
0.00 |
83.31 |
0.00 |
90.82 |
0.01 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.57398944 |
| 90.69 |
0.01 |
92.86 |
0.00 |
83.31 |
0.00 |
90.82 |
0.01 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.4203509593 |
| 90.69 |
0.01 |
92.86 |
0.00 |
83.31 |
0.00 |
90.82 |
0.01 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.507124182 |
| 90.69 |
0.01 |
92.86 |
0.00 |
83.31 |
0.00 |
90.83 |
0.01 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.4191836033 |
| 90.69 |
0.01 |
92.86 |
0.00 |
83.31 |
0.00 |
90.83 |
0.01 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.rom_raw_unlock.3570156939 |
| 90.69 |
0.01 |
92.86 |
0.00 |
83.31 |
0.00 |
90.83 |
0.01 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1523807024 |
| 90.69 |
0.01 |
92.86 |
0.00 |
83.31 |
0.00 |
90.83 |
0.01 |
|
|
94.70 |
0.00 |
97.55 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.4003385274 |
| Name |
| /workspace/coverage/default/0.chip_sival_flash_info_access.3608460349 |
| /workspace/coverage/default/0.chip_sw_aes_enc.3404617084 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3384992490 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.809280597 |
| /workspace/coverage/default/0.chip_sw_aes_entropy.563227003 |
| /workspace/coverage/default/0.chip_sw_aes_idle.498535459 |
| /workspace/coverage/default/0.chip_sw_aes_masking_off.2000775943 |
| /workspace/coverage/default/0.chip_sw_aes_smoketest.3539104042 |
| /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2387374199 |
| /workspace/coverage/default/0.chip_sw_alert_handler_escalation.4028140810 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.47062639 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1179033082 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3802237361 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3720040923 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1345192471 |
| /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2927458015 |
| /workspace/coverage/default/0.chip_sw_alert_test.3487438896 |
| /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3064177113 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2486633640 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2037502652 |
| /workspace/coverage/default/0.chip_sw_ast_clk_outputs.3767989428 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2064497370 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.857444552 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1910345199 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3024236183 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2578155123 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.934900074 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter.4264282786 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3858169595 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3691096102 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1279033872 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.824719735 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3528546028 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3732620809 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1843892841 |
| /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3776987587 |
| /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1279714162 |
| /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1428528170 |
| /workspace/coverage/default/0.chip_sw_coremark.2111428029 |
| /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1385990937 |
| /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2242030883 |
| /workspace/coverage/default/0.chip_sw_csrng_kat_test.1665537486 |
| /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3879925173 |
| /workspace/coverage/default/0.chip_sw_csrng_smoketest.1976630460 |
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| /workspace/coverage/default/7.chip_sw_all_escalation_resets.1135426882 |
| /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1875227704 |
| /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2036879481 |
| /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3849185433 |
| /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.790220495 |
| /workspace/coverage/default/70.chip_sw_all_escalation_resets.3227052591 |
| /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.4031370563 |
| /workspace/coverage/default/71.chip_sw_all_escalation_resets.2876613220 |
| /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3229067198 |
| /workspace/coverage/default/72.chip_sw_all_escalation_resets.2249415783 |
| /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.77265704 |
| /workspace/coverage/default/74.chip_sw_all_escalation_resets.3642696724 |
| /workspace/coverage/default/75.chip_sw_all_escalation_resets.2711800129 |
| /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1366279203 |
| /workspace/coverage/default/76.chip_sw_all_escalation_resets.841605988 |
| /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3689284204 |
| /workspace/coverage/default/77.chip_sw_all_escalation_resets.2118001787 |
| /workspace/coverage/default/78.chip_sw_all_escalation_resets.3010081882 |
| /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2219930178 |
| /workspace/coverage/default/79.chip_sw_all_escalation_resets.664573485 |
| /workspace/coverage/default/8.chip_sw_all_escalation_resets.1328352485 |
| /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.497711100 |
| /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1436007982 |
| /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1948036905 |
| /workspace/coverage/default/80.chip_sw_all_escalation_resets.4160809291 |
| /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1172387697 |
| /workspace/coverage/default/81.chip_sw_all_escalation_resets.735666570 |
| /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3323655048 |
| /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3141555648 |
| /workspace/coverage/default/83.chip_sw_all_escalation_resets.256564075 |
| /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.565558957 |
| /workspace/coverage/default/84.chip_sw_all_escalation_resets.2178055610 |
| /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2805128680 |
| /workspace/coverage/default/85.chip_sw_all_escalation_resets.3841899286 |
| /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.778628306 |
| /workspace/coverage/default/86.chip_sw_all_escalation_resets.2661460299 |
| /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.258499726 |
| /workspace/coverage/default/87.chip_sw_all_escalation_resets.3772853295 |
| /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.126581796 |
| /workspace/coverage/default/89.chip_sw_all_escalation_resets.940558589 |
| /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3451542513 |
| /workspace/coverage/default/9.chip_sw_all_escalation_resets.252384595 |
| /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3236767325 |
| /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3045111932 |
| /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2374658958 |
| /workspace/coverage/default/90.chip_sw_all_escalation_resets.4178522772 |
| /workspace/coverage/default/91.chip_sw_all_escalation_resets.2456742265 |
| /workspace/coverage/default/93.chip_sw_all_escalation_resets.2418456834 |
| /workspace/coverage/default/95.chip_sw_all_escalation_resets.498162189 |
| /workspace/coverage/default/96.chip_sw_all_escalation_resets.2413147083 |
| /workspace/coverage/default/97.chip_sw_all_escalation_resets.1062178935 |
| /workspace/coverage/default/98.chip_sw_all_escalation_resets.1518322016 |
| /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3364710599 |
| /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1146487323 |
| /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3485676372 |
| /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1731848411 |
| /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1656168332 |
| /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3583695888 |
| /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4197272493 |
| /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1896807437 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T4 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2868826269 |
|
|
Jul 05 07:29:05 PM PDT 24 |
Jul 05 07:49:53 PM PDT 24 |
8307290643 ps |
| T5 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3370897953 |
|
|
Jul 05 07:44:23 PM PDT 24 |
Jul 05 07:51:08 PM PDT 24 |
3625895332 ps |
| T6 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2971740799 |
|
|
Jul 05 06:57:56 PM PDT 24 |
Jul 05 07:09:45 PM PDT 24 |
4419906750 ps |
| T18 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1843892841 |
|
|
Jul 05 07:03:07 PM PDT 24 |
Jul 05 07:24:28 PM PDT 24 |
9635318604 ps |
| T45 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.441931367 |
|
|
Jul 05 07:30:30 PM PDT 24 |
Jul 05 08:05:53 PM PDT 24 |
10351193530 ps |
| T59 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4117604207 |
|
|
Jul 05 07:04:10 PM PDT 24 |
Jul 05 07:15:13 PM PDT 24 |
4376504607 ps |
| T115 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1671005042 |
|
|
Jul 05 07:39:40 PM PDT 24 |
Jul 05 07:52:08 PM PDT 24 |
5776603994 ps |
| T125 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.3090120011 |
|
|
Jul 05 07:12:30 PM PDT 24 |
Jul 05 07:32:11 PM PDT 24 |
6269337576 ps |
| T116 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2641963750 |
|
|
Jul 05 07:36:33 PM PDT 24 |
Jul 05 07:45:33 PM PDT 24 |
5284765200 ps |
| T75 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3705468750 |
|
|
Jul 05 07:43:59 PM PDT 24 |
Jul 05 07:50:27 PM PDT 24 |
3678814648 ps |
| T96 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2433605501 |
|
|
Jul 05 07:37:56 PM PDT 24 |
Jul 05 07:49:16 PM PDT 24 |
3872745980 ps |
| T28 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3963501025 |
|
|
Jul 05 07:34:45 PM PDT 24 |
Jul 05 07:58:07 PM PDT 24 |
8510790530 ps |
| T166 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.4276657510 |
|
|
Jul 05 07:44:43 PM PDT 24 |
Jul 05 07:53:58 PM PDT 24 |
5519734226 ps |
| T76 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2467472937 |
|
|
Jul 05 07:42:28 PM PDT 24 |
Jul 05 07:49:38 PM PDT 24 |
4314761000 ps |
| T205 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.890283813 |
|
|
Jul 05 07:18:17 PM PDT 24 |
Jul 05 07:25:08 PM PDT 24 |
3932009944 ps |
| T217 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.3072065747 |
|
|
Jul 05 07:19:58 PM PDT 24 |
Jul 05 07:23:23 PM PDT 24 |
2361888440 ps |
| T19 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3937940380 |
|
|
Jul 05 06:57:29 PM PDT 24 |
Jul 05 10:58:30 PM PDT 24 |
78470046234 ps |
| T77 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3936015351 |
|
|
Jul 05 07:13:44 PM PDT 24 |
Jul 05 07:32:42 PM PDT 24 |
5761581083 ps |
| T213 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3802796171 |
|
|
Jul 05 07:41:52 PM PDT 24 |
Jul 05 07:54:07 PM PDT 24 |
5268481800 ps |
| T60 |
/workspace/coverage/default/0.chip_tap_straps_rma.1653801353 |
|
|
Jul 05 07:03:02 PM PDT 24 |
Jul 05 07:09:13 PM PDT 24 |
4398966525 ps |
| T62 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.975106876 |
|
|
Jul 05 06:58:00 PM PDT 24 |
Jul 05 06:59:55 PM PDT 24 |
1867311652 ps |
| T223 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.2749657105 |
|
|
Jul 05 07:18:21 PM PDT 24 |
Jul 05 07:21:46 PM PDT 24 |
2460428040 ps |
| T104 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2710669139 |
|
|
Jul 05 07:27:58 PM PDT 24 |
Jul 05 08:02:57 PM PDT 24 |
7952555464 ps |
| T78 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3564063323 |
|
|
Jul 05 07:19:45 PM PDT 24 |
Jul 05 07:28:53 PM PDT 24 |
3901090289 ps |
| T206 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3939464074 |
|
|
Jul 05 07:22:13 PM PDT 24 |
Jul 05 07:30:23 PM PDT 24 |
5734369660 ps |
| T61 |
/workspace/coverage/default/3.chip_tap_straps_rma.3258703357 |
|
|
Jul 05 07:35:15 PM PDT 24 |
Jul 05 07:42:25 PM PDT 24 |
4431381363 ps |
| T341 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.4155631674 |
|
|
Jul 05 07:23:45 PM PDT 24 |
Jul 05 07:43:36 PM PDT 24 |
5717686402 ps |
| T20 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.4119617720 |
|
|
Jul 05 07:12:31 PM PDT 24 |
Jul 05 08:24:47 PM PDT 24 |
14843454317 ps |
| T58 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2181548550 |
|
|
Jul 05 07:11:01 PM PDT 24 |
Jul 05 08:09:58 PM PDT 24 |
15151143750 ps |
| T308 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3533689487 |
|
|
Jul 05 07:37:38 PM PDT 24 |
Jul 05 07:47:02 PM PDT 24 |
3727709148 ps |
| T204 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3043599665 |
|
|
Jul 05 07:32:24 PM PDT 24 |
Jul 05 07:36:42 PM PDT 24 |
2834543027 ps |
| T362 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3488879336 |
|
|
Jul 05 06:57:43 PM PDT 24 |
Jul 05 07:10:19 PM PDT 24 |
4142162250 ps |
| T183 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1172387697 |
|
|
Jul 05 07:42:59 PM PDT 24 |
Jul 05 07:49:35 PM PDT 24 |
3902871100 ps |
| T152 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3005665294 |
|
|
Jul 05 06:57:26 PM PDT 24 |
Jul 05 07:10:31 PM PDT 24 |
4583190404 ps |
| T21 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.4068985284 |
|
|
Jul 05 07:02:05 PM PDT 24 |
Jul 05 07:11:54 PM PDT 24 |
9045215260 ps |
| T165 |
/workspace/coverage/default/0.rom_keymgr_functest.1251126932 |
|
|
Jul 05 07:09:06 PM PDT 24 |
Jul 05 07:20:53 PM PDT 24 |
5171346350 ps |
| T63 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2665460051 |
|
|
Jul 05 06:56:21 PM PDT 24 |
Jul 05 10:00:00 PM PDT 24 |
60491938801 ps |
| T56 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.3557572305 |
|
|
Jul 05 07:38:13 PM PDT 24 |
Jul 05 08:35:00 PM PDT 24 |
25981201855 ps |
| T25 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.269205072 |
|
|
Jul 05 06:57:41 PM PDT 24 |
Jul 05 07:10:31 PM PDT 24 |
4679556229 ps |
| T158 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1004885860 |
|
|
Jul 05 07:13:53 PM PDT 24 |
Jul 05 07:35:04 PM PDT 24 |
7750749844 ps |
| T180 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2223250982 |
|
|
Jul 05 07:26:17 PM PDT 24 |
Jul 05 08:25:59 PM PDT 24 |
14146768252 ps |
| T173 |
/workspace/coverage/default/2.rom_keymgr_functest.2137591384 |
|
|
Jul 05 07:33:39 PM PDT 24 |
Jul 05 07:43:48 PM PDT 24 |
5706090270 ps |
| T1 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2331742198 |
|
|
Jul 05 07:03:23 PM PDT 24 |
Jul 05 07:28:37 PM PDT 24 |
21630996028 ps |
| T138 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.4227809854 |
|
|
Jul 05 07:12:50 PM PDT 24 |
Jul 05 08:28:05 PM PDT 24 |
15397042612 ps |
| T139 |
/workspace/coverage/default/1.chip_tap_straps_prod.4048939133 |
|
|
Jul 05 07:20:24 PM PDT 24 |
Jul 05 07:23:10 PM PDT 24 |
2836529451 ps |
| T140 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2824770609 |
|
|
Jul 05 07:14:55 PM PDT 24 |
Jul 05 07:20:05 PM PDT 24 |
3023368578 ps |
| T141 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2178055610 |
|
|
Jul 05 07:45:54 PM PDT 24 |
Jul 05 07:54:04 PM PDT 24 |
5626614100 ps |
| T142 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3564932724 |
|
|
Jul 05 07:38:36 PM PDT 24 |
Jul 05 07:44:47 PM PDT 24 |
3910986820 ps |
| T2 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1214007829 |
|
|
Jul 05 07:33:51 PM PDT 24 |
Jul 05 07:40:56 PM PDT 24 |
7096059192 ps |
| T143 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.949102517 |
|
|
Jul 05 07:39:44 PM PDT 24 |
Jul 05 07:46:30 PM PDT 24 |
4252780180 ps |
| T79 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.702245555 |
|
|
Jul 05 07:22:10 PM PDT 24 |
Jul 05 07:53:22 PM PDT 24 |
11401899976 ps |
| T144 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1968655634 |
|
|
Jul 05 06:59:16 PM PDT 24 |
Jul 05 07:22:43 PM PDT 24 |
8116405386 ps |
| T562 |
/workspace/coverage/default/0.chip_sw_example_concurrency.2062351564 |
|
|
Jul 05 06:56:05 PM PDT 24 |
Jul 05 07:01:33 PM PDT 24 |
2739586680 ps |
| T68 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.214738897 |
|
|
Jul 05 07:36:09 PM PDT 24 |
Jul 05 07:46:28 PM PDT 24 |
5653474603 ps |
| T563 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3695377823 |
|
|
Jul 05 07:21:42 PM PDT 24 |
Jul 05 07:43:52 PM PDT 24 |
5178247884 ps |
| T81 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.1615818245 |
|
|
Jul 05 07:16:56 PM PDT 24 |
Jul 05 07:27:27 PM PDT 24 |
3707298778 ps |
| T210 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1815937787 |
|
|
Jul 05 07:35:37 PM PDT 24 |
Jul 05 07:44:47 PM PDT 24 |
5067643128 ps |
| T203 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.1647228560 |
|
|
Jul 05 07:27:34 PM PDT 24 |
Jul 05 07:47:07 PM PDT 24 |
6482328980 ps |
| T57 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2493094606 |
|
|
Jul 05 07:11:36 PM PDT 24 |
Jul 05 08:41:48 PM PDT 24 |
23595836384 ps |
| T221 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1248120320 |
|
|
Jul 05 07:28:16 PM PDT 24 |
Jul 05 07:47:55 PM PDT 24 |
5643731304 ps |
| T32 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2345701517 |
|
|
Jul 05 06:59:08 PM PDT 24 |
Jul 05 08:02:33 PM PDT 24 |
20311650062 ps |
| T564 |
/workspace/coverage/default/1.chip_sw_example_concurrency.712318065 |
|
|
Jul 05 07:20:39 PM PDT 24 |
Jul 05 07:25:35 PM PDT 24 |
3091707500 ps |
| T234 |
/workspace/coverage/default/3.chip_tap_straps_prod.2136399132 |
|
|
Jul 05 07:34:36 PM PDT 24 |
Jul 05 07:37:22 PM PDT 24 |
2538411182 ps |
| T565 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.1678654192 |
|
|
Jul 05 07:31:26 PM PDT 24 |
Jul 05 07:36:09 PM PDT 24 |
3249091085 ps |
| T415 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.539066740 |
|
|
Jul 05 07:14:13 PM PDT 24 |
Jul 05 08:56:28 PM PDT 24 |
23319469524 ps |
| T73 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3810951276 |
|
|
Jul 05 07:20:21 PM PDT 24 |
Jul 05 07:33:34 PM PDT 24 |
9256646040 ps |
| T211 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3468714284 |
|
|
Jul 05 07:41:09 PM PDT 24 |
Jul 05 07:48:58 PM PDT 24 |
4556255256 ps |
| T186 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.4191002212 |
|
|
Jul 05 07:12:45 PM PDT 24 |
Jul 05 07:23:39 PM PDT 24 |
4771699964 ps |
| T261 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1047847527 |
|
|
Jul 05 07:28:29 PM PDT 24 |
Jul 05 09:20:49 PM PDT 24 |
32822205576 ps |
| T403 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1330325714 |
|
|
Jul 05 07:41:26 PM PDT 24 |
Jul 05 07:50:59 PM PDT 24 |
4713358520 ps |
| T246 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.994527174 |
|
|
Jul 05 06:58:59 PM PDT 24 |
Jul 05 07:14:36 PM PDT 24 |
6807104010 ps |
| T266 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2555544105 |
|
|
Jul 05 06:58:36 PM PDT 24 |
Jul 05 07:06:44 PM PDT 24 |
6566123469 ps |
| T105 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1289779394 |
|
|
Jul 05 07:17:31 PM PDT 24 |
Jul 05 07:22:31 PM PDT 24 |
3425634743 ps |
| T69 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2298722843 |
|
|
Jul 05 07:14:36 PM PDT 24 |
Jul 05 07:37:44 PM PDT 24 |
9404052182 ps |
| T84 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2885155931 |
|
|
Jul 05 07:05:22 PM PDT 24 |
Jul 05 08:42:02 PM PDT 24 |
29288468568 ps |
| T267 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.4266827238 |
|
|
Jul 05 07:16:41 PM PDT 24 |
Jul 05 07:34:26 PM PDT 24 |
4858523394 ps |
| T239 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1272520300 |
|
|
Jul 05 06:59:07 PM PDT 24 |
Jul 05 07:04:37 PM PDT 24 |
3694380762 ps |
| T222 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.735666570 |
|
|
Jul 05 07:46:15 PM PDT 24 |
Jul 05 07:57:49 PM PDT 24 |
4681773080 ps |
| T64 |
/workspace/coverage/default/1.rom_raw_unlock.968169879 |
|
|
Jul 05 07:22:57 PM PDT 24 |
Jul 05 07:26:46 PM PDT 24 |
4321902866 ps |
| T74 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3488811344 |
|
|
Jul 05 07:34:22 PM PDT 24 |
Jul 05 07:45:04 PM PDT 24 |
6693770408 ps |
| T453 |
/workspace/coverage/default/0.chip_tap_straps_prod.2299148538 |
|
|
Jul 05 07:03:52 PM PDT 24 |
Jul 05 07:06:08 PM PDT 24 |
2624047408 ps |
| T85 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1523807024 |
|
|
Jul 05 07:20:16 PM PDT 24 |
Jul 05 10:40:49 PM PDT 24 |
83446895017 ps |
| T106 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3373562805 |
|
|
Jul 05 07:27:42 PM PDT 24 |
Jul 05 07:58:19 PM PDT 24 |
13178458768 ps |
| T315 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.940558589 |
|
|
Jul 05 07:44:47 PM PDT 24 |
Jul 05 07:53:18 PM PDT 24 |
4775365348 ps |
| T187 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.742784506 |
|
|
Jul 05 06:57:38 PM PDT 24 |
Jul 05 07:10:44 PM PDT 24 |
4283258996 ps |
| T259 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3262042408 |
|
|
Jul 05 07:34:36 PM PDT 24 |
Jul 05 07:39:36 PM PDT 24 |
3431311424 ps |
| T167 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2706160897 |
|
|
Jul 05 07:24:29 PM PDT 24 |
Jul 05 07:38:01 PM PDT 24 |
11004136344 ps |
| T225 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.120362639 |
|
|
Jul 05 07:11:45 PM PDT 24 |
Jul 05 07:16:06 PM PDT 24 |
2375290808 ps |
| T311 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2990943719 |
|
|
Jul 05 06:56:32 PM PDT 24 |
Jul 05 07:22:01 PM PDT 24 |
10241070392 ps |
| T353 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1948036905 |
|
|
Jul 05 07:44:39 PM PDT 24 |
Jul 05 07:50:50 PM PDT 24 |
3786848748 ps |
| T149 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1931839096 |
|
|
Jul 05 07:28:21 PM PDT 24 |
Jul 05 08:28:01 PM PDT 24 |
18824963590 ps |
| T566 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2746733549 |
|
|
Jul 05 07:26:23 PM PDT 24 |
Jul 05 07:33:52 PM PDT 24 |
5874830620 ps |
| T376 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.2022573101 |
|
|
Jul 05 07:41:30 PM PDT 24 |
Jul 05 07:50:05 PM PDT 24 |
5225913568 ps |
| T418 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.496191105 |
|
|
Jul 05 07:43:12 PM PDT 24 |
Jul 05 07:49:54 PM PDT 24 |
3636527184 ps |
| T260 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.390357031 |
|
|
Jul 05 07:26:38 PM PDT 24 |
Jul 05 07:34:27 PM PDT 24 |
4119435994 ps |
| T354 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.252384595 |
|
|
Jul 05 07:38:12 PM PDT 24 |
Jul 05 07:48:45 PM PDT 24 |
5208170120 ps |
| T567 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3691096102 |
|
|
Jul 05 07:05:58 PM PDT 24 |
Jul 05 07:09:50 PM PDT 24 |
2240981053 ps |
| T568 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.208446022 |
|
|
Jul 05 07:23:55 PM PDT 24 |
Jul 05 07:32:20 PM PDT 24 |
5679664692 ps |
| T80 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.857444552 |
|
|
Jul 05 07:02:48 PM PDT 24 |
Jul 05 07:13:51 PM PDT 24 |
3880059900 ps |
| T101 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3388261410 |
|
|
Jul 05 07:31:08 PM PDT 24 |
Jul 05 07:45:17 PM PDT 24 |
3847516416 ps |
| T474 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.784028277 |
|
|
Jul 05 07:41:10 PM PDT 24 |
Jul 05 07:49:59 PM PDT 24 |
4015397440 ps |
| T3 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3975374319 |
|
|
Jul 05 07:05:07 PM PDT 24 |
Jul 05 07:36:35 PM PDT 24 |
25366045482 ps |
| T409 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383396198 |
|
|
Jul 05 07:38:47 PM PDT 24 |
Jul 05 07:44:25 PM PDT 24 |
3605146312 ps |
| T102 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1617761263 |
|
|
Jul 05 07:30:05 PM PDT 24 |
Jul 05 07:41:38 PM PDT 24 |
5036839530 ps |
| T220 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4287639140 |
|
|
Jul 05 07:13:52 PM PDT 24 |
Jul 05 07:34:20 PM PDT 24 |
7323368032 ps |
| T65 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.467470155 |
|
|
Jul 05 07:12:23 PM PDT 24 |
Jul 05 10:07:31 PM PDT 24 |
59696771729 ps |
| T154 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1673238219 |
|
|
Jul 05 07:13:51 PM PDT 24 |
Jul 05 07:19:06 PM PDT 24 |
2649332356 ps |
| T117 |
/workspace/coverage/default/1.chip_tap_straps_dev.1142752720 |
|
|
Jul 05 07:18:33 PM PDT 24 |
Jul 05 07:34:54 PM PDT 24 |
8832195937 ps |
| T312 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3849185433 |
|
|
Jul 05 07:36:11 PM PDT 24 |
Jul 05 08:09:18 PM PDT 24 |
13232166348 ps |
| T226 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.3305688204 |
|
|
Jul 05 07:40:32 PM PDT 24 |
Jul 05 07:51:11 PM PDT 24 |
4937613370 ps |
| T236 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.3540497062 |
|
|
Jul 05 07:23:47 PM PDT 24 |
Jul 05 11:09:13 PM PDT 24 |
65772748932 ps |
| T414 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2219930178 |
|
|
Jul 05 07:43:33 PM PDT 24 |
Jul 05 07:49:36 PM PDT 24 |
3633805444 ps |
| T417 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.3350633574 |
|
|
Jul 05 07:36:25 PM PDT 24 |
Jul 05 07:50:10 PM PDT 24 |
4714858296 ps |
| T122 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.2573705485 |
|
|
Jul 05 07:40:53 PM PDT 24 |
Jul 05 07:53:13 PM PDT 24 |
4885265328 ps |
| T127 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.3313996257 |
|
|
Jul 05 07:20:09 PM PDT 24 |
Jul 05 07:26:46 PM PDT 24 |
2785254140 ps |
| T128 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.453444298 |
|
|
Jul 05 07:34:45 PM PDT 24 |
Jul 05 07:39:43 PM PDT 24 |
2882290008 ps |
| T129 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2901726082 |
|
|
Jul 05 07:39:12 PM PDT 24 |
Jul 05 08:36:20 PM PDT 24 |
11746766968 ps |
| T130 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1137471023 |
|
|
Jul 05 07:20:15 PM PDT 24 |
Jul 05 07:25:28 PM PDT 24 |
3369647252 ps |
| T131 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1658019895 |
|
|
Jul 05 07:14:21 PM PDT 24 |
Jul 05 08:29:03 PM PDT 24 |
15799276474 ps |
| T132 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.4217864204 |
|
|
Jul 05 07:02:40 PM PDT 24 |
Jul 05 07:18:34 PM PDT 24 |
7309426275 ps |
| T133 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2858816468 |
|
|
Jul 05 07:02:07 PM PDT 24 |
Jul 05 07:05:46 PM PDT 24 |
2471581140 ps |
| T134 |
/workspace/coverage/default/2.chip_sw_aes_entropy.830084912 |
|
|
Jul 05 07:27:57 PM PDT 24 |
Jul 05 07:32:42 PM PDT 24 |
2378056090 ps |
| T135 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.3724890519 |
|
|
Jul 05 07:09:29 PM PDT 24 |
Jul 05 07:16:05 PM PDT 24 |
3350102248 ps |
| T305 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.201164209 |
|
|
Jul 05 07:30:05 PM PDT 24 |
Jul 05 07:41:39 PM PDT 24 |
8091052630 ps |
| T240 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.58513468 |
|
|
Jul 05 07:15:04 PM PDT 24 |
Jul 05 07:25:10 PM PDT 24 |
4301630773 ps |
| T306 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3738885990 |
|
|
Jul 05 07:25:14 PM PDT 24 |
Jul 05 07:46:30 PM PDT 24 |
7877037578 ps |
| T307 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.795651379 |
|
|
Jul 05 07:18:29 PM PDT 24 |
Jul 05 07:36:31 PM PDT 24 |
8114224384 ps |
| T66 |
/workspace/coverage/default/0.chip_jtag_mem_access.2100568943 |
|
|
Jul 05 06:56:33 PM PDT 24 |
Jul 05 07:22:28 PM PDT 24 |
14019343288 ps |
| T13 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3111492506 |
|
|
Jul 05 07:20:46 PM PDT 24 |
Jul 05 07:25:15 PM PDT 24 |
3301506610 ps |
| T313 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3507455665 |
|
|
Jul 05 06:56:16 PM PDT 24 |
Jul 05 07:25:06 PM PDT 24 |
7777472722 ps |
| T359 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.1776595673 |
|
|
Jul 05 07:40:49 PM PDT 24 |
Jul 05 07:51:01 PM PDT 24 |
5513649804 ps |
| T441 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.648206679 |
|
|
Jul 05 07:36:07 PM PDT 24 |
Jul 05 07:44:24 PM PDT 24 |
7339885870 ps |
| T355 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2889986428 |
|
|
Jul 05 07:42:55 PM PDT 24 |
Jul 05 07:48:53 PM PDT 24 |
3111948632 ps |
| T442 |
/workspace/coverage/default/2.chip_sw_example_concurrency.3145778162 |
|
|
Jul 05 07:25:20 PM PDT 24 |
Jul 05 07:31:02 PM PDT 24 |
2833694448 ps |
| T218 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.956630862 |
|
|
Jul 05 07:31:26 PM PDT 24 |
Jul 05 07:40:29 PM PDT 24 |
8353566013 ps |
| T162 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3320441371 |
|
|
Jul 05 07:24:23 PM PDT 24 |
Jul 05 08:48:28 PM PDT 24 |
51433880374 ps |
| T410 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2219949339 |
|
|
Jul 05 07:41:40 PM PDT 24 |
Jul 05 07:48:40 PM PDT 24 |
3677234746 ps |
| T82 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2833960266 |
|
|
Jul 05 07:28:08 PM PDT 24 |
Jul 05 07:40:04 PM PDT 24 |
6779540646 ps |
| T207 |
/workspace/coverage/default/1.chip_sw_hmac_enc.4012074044 |
|
|
Jul 05 07:17:02 PM PDT 24 |
Jul 05 07:21:37 PM PDT 24 |
3332192080 ps |
| T569 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.3253373633 |
|
|
Jul 05 07:16:38 PM PDT 24 |
Jul 05 07:42:35 PM PDT 24 |
6580295996 ps |
| T570 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.2595797150 |
|
|
Jul 05 07:12:22 PM PDT 24 |
Jul 05 08:17:42 PM PDT 24 |
14401934808 ps |
| T159 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3473513082 |
|
|
Jul 05 07:18:33 PM PDT 24 |
Jul 05 07:26:52 PM PDT 24 |
5188910800 ps |
| T97 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1778100333 |
|
|
Jul 05 07:37:36 PM PDT 24 |
Jul 05 07:48:22 PM PDT 24 |
3522748468 ps |
| T176 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2091889824 |
|
|
Jul 05 07:31:58 PM PDT 24 |
Jul 05 07:38:41 PM PDT 24 |
2892259372 ps |
| T301 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1836551920 |
|
|
Jul 05 07:34:38 PM PDT 24 |
Jul 05 07:42:48 PM PDT 24 |
6181041706 ps |
| T268 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.257998332 |
|
|
Jul 05 07:12:36 PM PDT 24 |
Jul 05 08:20:34 PM PDT 24 |
15155030420 ps |
| T257 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.2422053388 |
|
|
Jul 05 07:26:47 PM PDT 24 |
Jul 05 07:30:58 PM PDT 24 |
2961192368 ps |
| T150 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.1554173429 |
|
|
Jul 05 07:34:33 PM PDT 24 |
Jul 05 07:55:55 PM PDT 24 |
7404689462 ps |
| T124 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.89080455 |
|
|
Jul 05 06:55:55 PM PDT 24 |
Jul 05 06:58:58 PM PDT 24 |
2563590840 ps |
| T302 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.105531185 |
|
|
Jul 05 07:33:14 PM PDT 24 |
Jul 05 07:41:52 PM PDT 24 |
3621173436 ps |
| T303 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1014130950 |
|
|
Jul 05 07:25:49 PM PDT 24 |
Jul 05 08:15:19 PM PDT 24 |
10908037480 ps |
| T160 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1939561482 |
|
|
Jul 05 07:31:46 PM PDT 24 |
Jul 05 07:43:05 PM PDT 24 |
5103810310 ps |
| T304 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3141835468 |
|
|
Jul 05 07:36:03 PM PDT 24 |
Jul 05 07:43:51 PM PDT 24 |
3412397480 ps |
| T447 |
/workspace/coverage/default/0.chip_tap_straps_dev.3833338187 |
|
|
Jul 05 07:03:16 PM PDT 24 |
Jul 05 07:33:40 PM PDT 24 |
15109371686 ps |
| T258 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1875009795 |
|
|
Jul 05 07:34:57 PM PDT 24 |
Jul 05 07:38:55 PM PDT 24 |
3299273624 ps |
| T571 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1389348664 |
|
|
Jul 05 06:57:01 PM PDT 24 |
Jul 05 07:14:41 PM PDT 24 |
6226711397 ps |
| T269 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.307448561 |
|
|
Jul 05 07:12:18 PM PDT 24 |
Jul 05 08:14:28 PM PDT 24 |
15019596620 ps |
| T99 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.3474911560 |
|
|
Jul 05 07:05:03 PM PDT 24 |
Jul 05 07:17:43 PM PDT 24 |
10827511336 ps |
| T270 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2173451651 |
|
|
Jul 05 07:12:06 PM PDT 24 |
Jul 05 08:04:29 PM PDT 24 |
11772348284 ps |
| T419 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3646540884 |
|
|
Jul 05 07:38:53 PM PDT 24 |
Jul 05 07:45:20 PM PDT 24 |
3525748732 ps |
| T572 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2551174685 |
|
|
Jul 05 07:05:42 PM PDT 24 |
Jul 05 07:26:21 PM PDT 24 |
5934744584 ps |
| T98 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2602198534 |
|
|
Jul 05 07:35:09 PM PDT 24 |
Jul 05 07:44:53 PM PDT 24 |
4249445490 ps |
| T177 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.323152593 |
|
|
Jul 05 07:18:27 PM PDT 24 |
Jul 05 07:33:03 PM PDT 24 |
6511499994 ps |
| T573 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.1295669925 |
|
|
Jul 05 06:56:06 PM PDT 24 |
Jul 05 07:00:56 PM PDT 24 |
2646257096 ps |
| T574 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.338673292 |
|
|
Jul 05 07:17:16 PM PDT 24 |
Jul 05 07:23:08 PM PDT 24 |
3260152744 ps |
| T575 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2827297742 |
|
|
Jul 05 07:13:12 PM PDT 24 |
Jul 05 08:19:07 PM PDT 24 |
14682589752 ps |
| T50 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.836990933 |
|
|
Jul 05 07:15:41 PM PDT 24 |
Jul 05 07:22:13 PM PDT 24 |
5943214550 ps |
| T31 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.1165654797 |
|
|
Jul 05 06:57:22 PM PDT 24 |
Jul 05 07:32:25 PM PDT 24 |
8016374756 ps |
| T576 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.717333256 |
|
|
Jul 05 07:09:44 PM PDT 24 |
Jul 05 07:15:25 PM PDT 24 |
4474904232 ps |
| T577 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3055148087 |
|
|
Jul 05 07:30:21 PM PDT 24 |
Jul 05 07:42:13 PM PDT 24 |
4183517356 ps |
| T342 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1018602254 |
|
|
Jul 05 07:37:21 PM PDT 24 |
Jul 05 07:52:05 PM PDT 24 |
4152853368 ps |
| T366 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2670693908 |
|
|
Jul 05 07:34:34 PM PDT 24 |
Jul 05 07:43:34 PM PDT 24 |
3881956568 ps |
| T309 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1438837237 |
|
|
Jul 05 07:34:57 PM PDT 24 |
Jul 05 07:48:02 PM PDT 24 |
5008409192 ps |
| T389 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2456742265 |
|
|
Jul 05 07:44:46 PM PDT 24 |
Jul 05 07:55:06 PM PDT 24 |
6381999960 ps |
| T219 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.4265028423 |
|
|
Jul 05 07:30:06 PM PDT 24 |
Jul 05 07:35:16 PM PDT 24 |
2433839566 ps |
| T112 |
/workspace/coverage/default/2.chip_sw_alert_test.1561702682 |
|
|
Jul 05 07:27:14 PM PDT 24 |
Jul 05 07:32:38 PM PDT 24 |
2955331840 ps |
| T10 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.320486237 |
|
|
Jul 05 07:32:05 PM PDT 24 |
Jul 05 08:00:33 PM PDT 24 |
19411087248 ps |
| T109 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.81235782 |
|
|
Jul 05 07:32:03 PM PDT 24 |
Jul 05 07:41:48 PM PDT 24 |
3871464430 ps |
| T475 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3772853295 |
|
|
Jul 05 07:44:15 PM PDT 24 |
Jul 05 07:56:22 PM PDT 24 |
4890798984 ps |
| T100 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.196687523 |
|
|
Jul 05 07:32:47 PM PDT 24 |
Jul 05 07:41:35 PM PDT 24 |
5046535920 ps |
| T578 |
/workspace/coverage/default/1.rom_e2e_smoke.1606875235 |
|
|
Jul 05 07:26:32 PM PDT 24 |
Jul 05 08:33:50 PM PDT 24 |
14544914840 ps |
| T351 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1611886372 |
|
|
Jul 05 06:58:37 PM PDT 24 |
Jul 05 07:31:33 PM PDT 24 |
18210512123 ps |
| T361 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2037502652 |
|
|
Jul 05 07:00:19 PM PDT 24 |
Jul 05 07:09:54 PM PDT 24 |
5827839112 ps |
| T579 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1975990040 |
|
|
Jul 05 07:12:15 PM PDT 24 |
Jul 05 08:15:19 PM PDT 24 |
14475841704 ps |
| T481 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1150353326 |
|
|
Jul 05 07:17:04 PM PDT 24 |
Jul 05 07:24:09 PM PDT 24 |
3620449444 ps |
| T178 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2159027000 |
|
|
Jul 05 07:22:10 PM PDT 24 |
Jul 05 07:26:33 PM PDT 24 |
2681694512 ps |
| T580 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2578155123 |
|
|
Jul 05 07:03:10 PM PDT 24 |
Jul 05 07:13:36 PM PDT 24 |
4341195696 ps |
| T271 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1689605298 |
|
|
Jul 05 07:13:41 PM PDT 24 |
Jul 05 07:16:25 PM PDT 24 |
1948872517 ps |
| T581 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1534243631 |
|
|
Jul 05 07:21:54 PM PDT 24 |
Jul 05 07:27:52 PM PDT 24 |
2817517150 ps |
| T582 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.4043508680 |
|
|
Jul 05 07:21:18 PM PDT 24 |
Jul 05 07:25:05 PM PDT 24 |
2984582078 ps |
| T248 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.3819639786 |
|
|
Jul 05 07:27:43 PM PDT 24 |
Jul 05 07:37:24 PM PDT 24 |
4351321536 ps |
| T583 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3608952788 |
|
|
Jul 05 07:30:47 PM PDT 24 |
Jul 05 07:44:30 PM PDT 24 |
4183934956 ps |
| T188 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.514242568 |
|
|
Jul 05 06:56:46 PM PDT 24 |
Jul 05 07:09:30 PM PDT 24 |
5030216656 ps |
| T318 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.4137238799 |
|
|
Jul 05 07:32:28 PM PDT 24 |
Jul 05 07:43:41 PM PDT 24 |
6327665329 ps |
| T163 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.638966128 |
|
|
Jul 05 07:24:15 PM PDT 24 |
Jul 05 08:44:03 PM PDT 24 |
42894926492 ps |
| T174 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3899512822 |
|
|
Jul 05 07:05:13 PM PDT 24 |
Jul 05 07:16:10 PM PDT 24 |
5422218214 ps |
| T386 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.226916018 |
|
|
Jul 05 07:40:02 PM PDT 24 |
Jul 05 07:50:00 PM PDT 24 |
5728043240 ps |
| T584 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.40679972 |
|
|
Jul 05 07:29:12 PM PDT 24 |
Jul 05 07:32:27 PM PDT 24 |
2505563976 ps |
| T29 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.488880422 |
|
|
Jul 05 07:09:11 PM PDT 24 |
Jul 05 07:14:30 PM PDT 24 |
3335349390 ps |
| T585 |
/workspace/coverage/default/0.chip_sw_hmac_multistream.2174222940 |
|
|
Jul 05 07:00:44 PM PDT 24 |
Jul 05 07:32:40 PM PDT 24 |
8209295000 ps |
| T22 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.508379240 |
|
|
Jul 05 07:22:09 PM PDT 24 |
Jul 05 07:27:55 PM PDT 24 |
3164784106 ps |
| T380 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.3708654047 |
|
|
Jul 05 07:38:57 PM PDT 24 |
Jul 05 07:49:49 PM PDT 24 |
5070162788 ps |
| T586 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.563386091 |
|
|
Jul 05 07:34:42 PM PDT 24 |
Jul 05 07:44:03 PM PDT 24 |
4237665420 ps |
| T587 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1910345199 |
|
|
Jul 05 07:02:24 PM PDT 24 |
Jul 05 07:13:08 PM PDT 24 |
4374229376 ps |
| T168 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.4074666872 |
|
|
Jul 05 06:57:39 PM PDT 24 |
Jul 05 07:02:18 PM PDT 24 |
3322486158 ps |
| T478 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.3955154268 |
|
|
Jul 05 07:36:34 PM PDT 24 |
Jul 05 07:47:20 PM PDT 24 |
4731512008 ps |
| T588 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.3846780197 |
|
|
Jul 05 07:34:22 PM PDT 24 |
Jul 05 07:40:02 PM PDT 24 |
3702977306 ps |
| T247 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3109487174 |
|
|
Jul 05 07:45:48 PM PDT 24 |
Jul 05 07:52:53 PM PDT 24 |
4670766420 ps |
| T482 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3032226398 |
|
|
Jul 05 07:41:43 PM PDT 24 |
Jul 05 07:48:21 PM PDT 24 |
4022769080 ps |
| T589 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3968343183 |
|
|
Jul 05 07:17:35 PM PDT 24 |
Jul 05 07:50:27 PM PDT 24 |
8042772492 ps |
| T47 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.318416125 |
|
|
Jul 05 06:56:36 PM PDT 24 |
Jul 05 07:02:25 PM PDT 24 |
3037770914 ps |
| T314 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.1091942751 |
|
|
Jul 05 07:41:43 PM PDT 24 |
Jul 05 07:50:33 PM PDT 24 |
4882758606 ps |
| T473 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3005580844 |
|
|
Jul 05 07:11:23 PM PDT 24 |
Jul 05 07:23:07 PM PDT 24 |
4713603374 ps |
| T472 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.112599690 |
|
|
Jul 05 06:56:08 PM PDT 24 |
Jul 05 07:10:26 PM PDT 24 |
6129652632 ps |
| T590 |
/workspace/coverage/default/2.chip_sw_kmac_idle.3480351796 |
|
|
Jul 05 07:30:12 PM PDT 24 |
Jul 05 07:35:01 PM PDT 24 |
2207694136 ps |
| T591 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.825393970 |
|
|
Jul 05 07:02:53 PM PDT 24 |
Jul 05 07:06:52 PM PDT 24 |
3162572592 ps |
| T592 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1969656881 |
|
|
Jul 05 07:34:18 PM PDT 24 |
Jul 05 07:38:22 PM PDT 24 |
2787473066 ps |
| T593 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1385990937 |
|
|
Jul 05 07:00:20 PM PDT 24 |
Jul 05 09:06:11 PM PDT 24 |
30978911052 ps |
| T594 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.2257784745 |
|
|
Jul 05 07:22:46 PM PDT 24 |
Jul 05 07:27:03 PM PDT 24 |
2597295456 ps |
| T272 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1231872093 |
|
|
Jul 05 07:11:39 PM PDT 24 |
Jul 05 08:15:40 PM PDT 24 |
14460502885 ps |
| T595 |
/workspace/coverage/default/1.rom_e2e_static_critical.513319203 |
|
|
Jul 05 07:27:05 PM PDT 24 |
Jul 05 08:43:25 PM PDT 24 |
17004809608 ps |
| T26 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2198834429 |
|
|
Jul 05 07:13:36 PM PDT 24 |
Jul 05 07:24:20 PM PDT 24 |
4333243628 ps |
| T596 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2436494511 |
|
|
Jul 05 07:21:14 PM PDT 24 |
Jul 05 07:44:31 PM PDT 24 |
6689544418 ps |
| T469 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2750782160 |
|
|
Jul 05 07:42:39 PM PDT 24 |
Jul 05 07:52:40 PM PDT 24 |
5008861040 ps |
| T145 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.222727101 |
|
|
Jul 05 07:26:13 PM PDT 24 |
Jul 05 07:34:50 PM PDT 24 |
5432168120 ps |
| T597 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.3954890922 |
|
|
Jul 05 07:24:55 PM PDT 24 |
Jul 05 07:29:15 PM PDT 24 |
2265117900 ps |
| T598 |
/workspace/coverage/default/2.chip_sw_hmac_oneshot.2116224946 |
|
|
Jul 05 07:28:55 PM PDT 24 |
Jul 05 07:33:56 PM PDT 24 |
2976332776 ps |
| T387 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2235418269 |
|
|
Jul 05 07:44:55 PM PDT 24 |
Jul 05 07:55:19 PM PDT 24 |
6032288394 ps |
| T599 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1556214691 |
|
|
Jul 05 07:25:20 PM PDT 24 |
Jul 05 07:38:55 PM PDT 24 |
4058062040 ps |
| T360 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2345155097 |
|
|
Jul 05 07:00:39 PM PDT 24 |
Jul 05 07:21:58 PM PDT 24 |
8971596575 ps |
| T185 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1241931485 |
|
|
Jul 05 07:29:46 PM PDT 24 |
Jul 05 07:47:06 PM PDT 24 |
10517819142 ps |
| T600 |
/workspace/coverage/default/1.chip_sw_hmac_oneshot.2093494002 |
|
|
Jul 05 07:17:07 PM PDT 24 |
Jul 05 07:22:06 PM PDT 24 |
2544559888 ps |
| T601 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1849913395 |
|
|
Jul 05 07:32:59 PM PDT 24 |
Jul 05 07:38:58 PM PDT 24 |
2904796885 ps |
| T388 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.385468560 |
|
|
Jul 05 07:38:55 PM PDT 24 |
Jul 05 07:49:01 PM PDT 24 |
5595630984 ps |
| T602 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2267478432 |
|
|
Jul 05 07:11:27 PM PDT 24 |
Jul 05 08:01:30 PM PDT 24 |
14399326056 ps |
| T94 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.2434438800 |
|
|
Jul 05 07:35:02 PM PDT 24 |
Jul 05 07:37:17 PM PDT 24 |
2519483405 ps |
| T208 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.47062639 |
|
|
Jul 05 06:59:58 PM PDT 24 |
Jul 05 07:20:58 PM PDT 24 |
6599419000 ps |
| T384 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2280360901 |
|
|
Jul 05 07:37:09 PM PDT 24 |
Jul 05 08:00:15 PM PDT 24 |
7394639088 ps |
| T273 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.998737046 |
|
|
Jul 05 07:11:20 PM PDT 24 |
Jul 05 08:14:48 PM PDT 24 |
15131107580 ps |
| T603 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.488627418 |
|
|
Jul 05 07:27:16 PM PDT 24 |
Jul 05 08:30:11 PM PDT 24 |
16419709056 ps |
| T123 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3802237361 |
|
|
Jul 05 06:59:57 PM PDT 24 |
Jul 05 07:25:23 PM PDT 24 |
12023894200 ps |
| T368 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2620581548 |
|
|
Jul 05 07:03:02 PM PDT 24 |
Jul 05 07:10:21 PM PDT 24 |
3453971784 ps |
| T604 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1350266888 |
|
|
Jul 05 07:39:35 PM PDT 24 |
Jul 05 08:31:04 PM PDT 24 |
14512439962 ps |
| T23 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3796175328 |
|
|
Jul 05 07:19:08 PM PDT 24 |
Jul 05 07:24:15 PM PDT 24 |
3129972495 ps |
| T334 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1110611507 |
|
|
Jul 05 07:25:58 PM PDT 24 |
Jul 05 07:31:19 PM PDT 24 |
2988424632 ps |
| T605 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.14704995 |
|
|
Jul 05 06:57:39 PM PDT 24 |
Jul 05 07:03:10 PM PDT 24 |
3491241368 ps |
| T606 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3720040923 |
|
|
Jul 05 07:00:06 PM PDT 24 |
Jul 05 07:24:25 PM PDT 24 |
7680471112 ps |
| T95 |
/workspace/coverage/default/2.chip_tap_straps_rma.552806479 |
|
|
Jul 05 07:31:15 PM PDT 24 |
Jul 05 07:33:37 PM PDT 24 |
2958132715 ps |
| T179 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.456960420 |
|
|
Jul 05 07:05:12 PM PDT 24 |
Jul 05 07:09:54 PM PDT 24 |
3382301538 ps |
| T191 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.381058746 |
|
|
Jul 05 06:56:50 PM PDT 24 |
Jul 05 07:14:28 PM PDT 24 |
5672917480 ps |