Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	172920	1			T75	299		T80	10		T161	67
values[2]	4548	1			T235	1		T634	1		T599	8
values[3]	2172	1			T545	22		T796	1		T797	2
values[4]	1678	1			T545	31		T796	1		T797	2
values[5]	1282	1			T545	26		T796	1		T797	2
values[6]	1047	1			T545	7		T796	1		T797	2
values[7]	892	1			T545	11		T796	1		T797	2
values[8]	748	1			T545	14		T796	1		T797	2
values[9]	666	1			T545	12		T796	1		T797	2
values[10]	695	1			T545	15		T796	1		T797	2
values[11]	644	1			T545	15		T796	1		T797	2
values[12]	547	1			T545	18		T796	1		T797	2
values[13]	526	1			T545	11		T796	1		T797	2
values[14]	468	1			T545	8		T796	1		T797	2
values[15]	409	1			T545	9		T796	1		T797	2
values[16]	386	1			T545	14		T796	1		T797	2
values[17]	309	1			T545	10		T796	1		T797	2
values[18]	299	1			T545	8		T796	1		T797	2
values[19]	286	1			T545	32		T796	1		T797	2
values[20]	233	1			T545	29		T796	1		T797	2
values[21]	167	1			T545	20		T796	1		T797	2
values[22]	147	1			T545	12		T796	1		T797	2
values[23]	172	1			T545	1		T796	1		T797	2
values[24]	155	1			T545	3		T796	1		T797	2
values[25]	156	1			T545	5		T796	1		T797	2
values[26]	165	1			T545	6		T796	1		T797	2
values[27]	189	1			T545	5		T796	1		T797	2
values[28]	164	1			T545	2		T796	1		T797	2
values[29]	154	1			T545	5		T796	1		T797	2
values[30]	162	1			T545	1		T796	1		T797	2
values[31]	153	1			T796	1		T797	2		T808	1
values[32]	140	1			T796	1		T797	2		T808	1
values[33]	106	1			T796	1		T797	2		T808	1
values[34]	97	1			T796	1		T797	2		T808	1
values[35]	78	1			T796	1		T797	2		T808	1
values[36]	68	1			T796	1		T797	2		T808	1
values[37]	70	1			T796	1		T797	2		T808	1
values[38]	67	1			T796	1		T797	2		T808	1
values[39]	55	1			T796	1		T797	2		T808	1
values[40]	71	1			T796	1		T797	2		T808	1
values[41]	54	1			T796	1		T797	2		T808	1
values[42]	43	1			T796	1		T797	2		T808	1
values[43]	56	1			T796	1		T797	2		T808	1
values[44]	45	1			T796	1		T797	2		T808	1
values[45]	45	1			T796	1		T797	2		T808	1
values[46]	46	1			T796	1		T797	2		T808	1
values[47]	48	1			T796	1		T797	2		T808	1
values[48]	43	1			T796	1		T797	2		T808	1
values[49]	50	1			T796	1		T797	2		T808	1
values[50]	53	1			T796	1		T797	2		T808	1
values[51]	53	1			T796	1		T797	2		T808	1
values[52]	49	1			T796	1		T797	2		T808	1
values[53]	47	1			T796	1		T797	2		T808	1
values[54]	49	1			T796	1		T797	2		T808	1
values[55]	47	1			T796	1		T797	2		T808	1
values[56]	47	1			T796	1		T797	2		T808	1
values[57]	58	1			T796	1		T797	2		T808	1
values[58]	51	1			T796	1		T797	2		T808	1
values[59]	53	1			T796	1		T797	2		T808	1
values[60]	43	1			T796	1		T797	2		T808	1
values[61]	41	1			T796	1		T797	2		T808	1
values[62]	48	1			T796	1		T797	2		T808	1
values[63]	43	1			T796	1		T797	2		T808	1
values[64]	44	1			T796	1		T797	2		T808	1
values[65]	55	1			T796	1		T797	2		T808	1
values[66]	54	1			T796	1		T797	2		T808	1
values[67]	50	1			T796	1		T797	2		T808	1
values[68]	60	1			T796	1		T797	2		T808	1
values[69]	48	1			T796	1		T797	3		T808	1
values[70]	42	1			T796	1		T797	2		T808	1
values[71]	52	1			T796	1		T797	2		T808	1
values[72]	49	1			T796	1		T797	2		T808	1
values[73]	57	1			T796	1		T797	2		T808	1
values[74]	46	1			T796	1		T797	2		T808	1
values[75]	49	1			T796	1		T797	2		T808	1
values[76]	62	1			T796	1		T797	2		T808	1
values[77]	60	1			T796	1		T797	2		T808	1
values[78]	69	1			T796	1		T797	2		T808	1
values[79]	69	1			T796	1		T797	2		T808	1
values[80]	84	1			T796	3		T797	2		T808	1
values[81]	70	1			T796	3		T797	2		T808	2
values[82]	68	1			T796	9		T797	2		T808	1
values[83]	70	1			T796	9		T797	2		T808	1
values[84]	64	1			T796	5		T797	4		T808	1
values[85]	54	1			T796	1		T797	5		T808	1
values[86]	78	1			T796	8		T797	5		T808	1
values[87]	85	1			T796	4		T797	3		T808	1
values[88]	83	1			T796	2		T797	2		T808	1
values[89]	63	1			T796	2		T797	3		T808	1
values[90]	99	1			T796	1		T797	12		T808	1
values[91]	72	1			T796	2		T797	4		T808	1
values[92]	91	1			T796	1		T797	4		T808	3
values[93]	80	1			T796	2		T797	3		T808	3
values[94]	82	1			T796	3		T797	5		T808	2
values[95]	78	1			T796	1		T797	3		T808	7
values[96]	94	1			T796	1		T797	6		T808	3
values[97]	89	1			T796	1		T797	4		T808	1
values[98]	99	1			T796	4		T797	5		T808	2
values[99]	86	1			T796	6		T797	3		T808	1
values[100]	79	1			T796	3		T797	5		T808	1
values[101]	95	1			T796	1		T797	9		T808	3
values[102]	85	1			T796	3		T797	2		T808	1
values[103]	77	1			T796	1		T797	4		T808	5
values[104]	93	1			T796	1		T797	3		T808	3
values[105]	80	1			T796	3		T797	7		T808	1
values[106]	88	1			T796	2		T797	6		T808	1
values[107]	67	1			T796	1		T797	6		T808	2
values[108]	78	1			T796	3		T797	2		T808	2
values[109]	81	1			T796	4		T797	3		T808	2
values[110]	86	1			T796	2		T797	3		T808	3
values[111]	89	1			T796	2		T797	6		T808	4
values[112]	84	1			T796	1		T797	4		T808	1
values[113]	79	1			T796	3		T797	8		T808	2
values[114]	93	1			T796	2		T797	5		T808	2
values[115]	95	1			T796	2		T797	3		T808	2
values[116]	92	1			T796	3		T797	2		T808	7
values[117]	108	1			T796	2		T797	2		T808	1
values[118]	83	1			T796	2		T797	2		T808	2
values[119]	90	1			T796	2		T797	2		T808	1
values[120]	83	1			T796	1		T797	2		T808	1
values[121]	89	1			T796	3		T797	4		T808	2
values[122]	95	1			T796	1		T797	3		T808	2
values[123]	97	1			T796	1		T797	7		T808	2
values[124]	167	1			T796	1		T797	3		T808	1
values[125]	348	1			T796	1		T797	5		T808	4
values[126]	800	1			T796	9		T797	33		T808	22
values[127]	3141	1			T796	106		T797	225		T808	119
values[128]	5472	1			T796	183		T797	409		T808	165