Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.25 95.60 94.21 95.46 95.03 97.53 99.64


Total tests in report: 2904
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
39.69 39.69 44.47 44.47 42.87 42.87 33.14 33.14 57.78 57.78 59.44 59.44 0.42 0.42 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2820483862
49.17 9.49 52.86 8.39 53.07 10.20 36.37 3.24 66.37 8.59 85.66 26.22 0.70 0.28 /workspace/coverage/default/2.chip_jtag_csr_rw.3718397271
56.14 6.97 61.19 8.33 56.05 2.98 38.60 2.22 66.56 0.19 85.66 0.00 28.80 28.09 /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.4013730044
61.50 5.35 72.78 11.60 63.45 7.40 41.52 2.92 76.75 10.20 85.66 0.00 28.80 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_20.2272962855
64.95 3.46 78.67 5.88 67.78 4.33 45.46 3.94 78.78 2.03 90.21 4.55 28.80 0.00 /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1060577918
68.37 3.42 80.48 1.81 69.03 1.25 50.10 4.64 78.90 0.12 90.21 0.00 41.51 12.71 /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.291489683
71.29 2.92 80.48 0.00 69.10 0.07 50.10 0.00 78.90 0.00 90.21 0.00 58.95 17.44 /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.4233608114
73.87 2.58 83.21 2.72 75.84 6.74 50.49 0.38 83.76 4.85 90.21 0.00 59.73 0.79 /workspace/coverage/cover_reg_top/6.chip_csr_rw.886907778
76.44 2.56 85.95 2.74 78.88 3.04 57.18 6.70 86.13 2.37 90.73 0.52 59.73 0.00 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1471963848
78.60 2.17 85.95 0.00 79.11 0.23 57.18 0.00 86.13 0.00 90.73 0.00 72.51 12.77 /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1798890447
80.66 2.06 85.95 0.00 79.11 0.00 69.55 12.37 86.13 0.00 90.73 0.00 72.51 0.00 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3972021921
82.15 1.49 88.19 2.24 81.15 2.04 71.71 2.16 88.60 2.47 90.73 0.00 72.51 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_0.3075734140
83.49 1.34 88.19 0.00 81.15 0.00 71.71 0.00 88.60 0.00 90.73 0.00 80.53 8.02 /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2282699470
84.77 1.28 88.48 0.29 81.30 0.15 78.63 6.91 88.78 0.18 90.91 0.17 80.53 0.00 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.805254253
85.84 1.07 88.48 0.00 81.49 0.19 78.63 0.00 88.80 0.02 90.91 0.00 86.73 6.20 /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2772909415
86.82 0.98 89.06 0.57 82.24 0.74 80.57 1.94 89.31 0.51 90.91 0.00 88.84 2.10 /workspace/coverage/default/0.chip_sw_alert_test.1228411915
87.67 0.85 89.06 0.00 82.35 0.11 80.57 0.00 89.31 0.00 90.91 0.00 93.83 4.99 /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3936322249
88.50 0.83 90.70 1.64 83.88 1.54 81.19 0.62 90.50 1.19 90.91 0.00 93.83 0.00 /workspace/coverage/default/1.chip_sw_gpio.2480230210
89.21 0.71 90.86 0.16 83.99 0.11 81.20 0.01 90.63 0.13 94.76 3.85 93.83 0.00 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1682161939
89.87 0.66 91.57 0.71 85.51 1.52 81.32 0.12 92.24 1.61 94.76 0.00 93.83 0.00 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.694758463
90.45 0.58 91.58 0.01 88.55 3.04 81.32 0.00 92.24 0.00 94.76 0.00 94.24 0.41 /workspace/coverage/cover_reg_top/9.chip_tl_errors.217497403
90.93 0.48 91.58 0.00 88.55 0.00 84.18 2.86 92.24 0.00 94.76 0.00 94.24 0.00 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.651487880
91.37 0.44 92.17 0.58 89.18 0.63 84.98 0.80 92.90 0.66 94.76 0.00 94.24 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_10.604580485
91.77 0.40 92.75 0.58 89.65 0.47 85.25 0.27 93.47 0.57 95.28 0.52 94.24 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1168122574
92.14 0.37 92.76 0.01 89.65 0.01 87.45 2.20 93.47 0.00 95.28 0.00 94.24 0.00 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1253493550
92.43 0.29 92.96 0.20 89.81 0.16 88.71 1.26 93.60 0.13 95.28 0.00 94.24 0.00 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.206837347
92.69 0.26 93.19 0.23 90.06 0.25 88.98 0.27 93.71 0.11 95.98 0.70 94.24 0.00 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3404014491
92.95 0.26 93.19 0.00 90.14 0.08 88.98 0.00 93.73 0.02 95.98 0.00 95.71 1.47 /workspace/coverage/cover_reg_top/53.xbar_access_same_device.1346821044
93.15 0.20 93.39 0.20 90.28 0.14 89.35 0.38 93.85 0.12 96.33 0.35 95.71 0.00 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.217174602
93.35 0.20 93.39 0.00 90.28 0.00 90.53 1.18 93.85 0.00 96.33 0.00 95.71 0.00 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.841263953
93.51 0.16 93.39 0.00 90.37 0.09 90.53 0.00 93.87 0.02 96.33 0.00 96.58 0.87 /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2760200147
93.66 0.15 93.60 0.21 90.69 0.32 90.88 0.35 93.87 0.00 96.33 0.00 96.58 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3358866850
93.80 0.14 93.77 0.18 91.28 0.58 90.91 0.03 93.93 0.06 96.33 0.00 96.58 0.00 /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1723199797
93.93 0.14 93.77 0.00 91.28 0.00 91.69 0.78 93.93 0.00 96.33 0.00 96.62 0.04 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.690428466
94.07 0.13 93.77 0.00 91.28 0.00 91.69 0.00 93.93 0.00 96.33 0.00 97.40 0.79 /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2487754970
94.19 0.12 93.77 0.00 91.30 0.02 91.71 0.02 93.93 0.00 96.33 0.00 98.10 0.69 /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.2241530140
94.31 0.12 94.04 0.27 91.43 0.12 91.78 0.07 94.00 0.07 96.50 0.17 98.11 0.01 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.669455007
94.42 0.11 94.05 0.01 91.45 0.02 92.25 0.47 94.02 0.02 96.68 0.17 98.11 0.00 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1537451350
94.52 0.10 94.05 0.00 91.45 0.00 92.83 0.58 94.02 0.00 96.68 0.00 98.11 0.00 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.745499883
94.61 0.09 94.05 0.00 91.69 0.24 92.83 0.01 94.30 0.28 96.68 0.00 98.11 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3018609135
94.68 0.08 94.05 0.00 91.69 0.00 93.28 0.45 94.30 0.00 96.68 0.00 98.11 0.00 /workspace/coverage/default/0.chip_sw_edn_auto_mode.1177748826
94.75 0.06 94.17 0.13 91.69 0.01 93.52 0.24 94.31 0.02 96.68 0.00 98.11 0.00 /workspace/coverage/default/1.chip_tap_straps_rma.1813302514
94.80 0.06 94.27 0.10 91.83 0.14 93.54 0.02 94.39 0.08 96.68 0.00 98.11 0.00 /workspace/coverage/default/0.chip_jtag_csr_rw.3088426105
94.86 0.05 94.32 0.05 91.87 0.04 93.56 0.02 94.43 0.03 96.85 0.17 98.12 0.01 /workspace/coverage/default/5.chip_sw_all_escalation_resets.690566737
94.91 0.05 94.33 0.01 92.02 0.14 93.57 0.01 94.59 0.16 96.85 0.00 98.12 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3523854057
94.96 0.05 94.33 0.00 92.02 0.00 93.87 0.30 94.59 0.00 96.85 0.00 98.12 0.00 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1880296174
95.01 0.05 94.33 0.00 92.31 0.29 93.87 0.00 94.59 0.00 96.85 0.00 98.12 0.00 /workspace/coverage/cover_reg_top/13.chip_tl_errors.1950022635
95.06 0.05 94.47 0.14 92.40 0.09 93.87 0.00 94.64 0.05 96.85 0.00 98.12 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.616821987
95.10 0.04 94.47 0.00 92.42 0.02 94.08 0.21 94.65 0.01 96.85 0.00 98.13 0.01 /workspace/coverage/default/0.rom_e2e_shutdown_output.941251929
95.14 0.04 94.47 0.00 92.42 0.00 94.32 0.24 94.65 0.00 96.85 0.00 98.13 0.00 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.994744070
95.18 0.04 94.47 0.00 92.50 0.08 94.32 0.00 94.66 0.02 96.85 0.00 98.27 0.14 /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.3111885572
95.22 0.04 94.48 0.01 92.52 0.01 94.32 0.00 94.69 0.02 97.03 0.17 98.28 0.01 /workspace/coverage/default/28.chip_sw_all_escalation_resets.3509702920
95.26 0.04 94.49 0.01 92.53 0.01 94.35 0.03 94.69 0.01 97.20 0.17 98.28 0.00 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3627147378
95.29 0.04 94.49 0.01 92.54 0.01 94.36 0.01 94.70 0.01 97.38 0.17 98.30 0.01 /workspace/coverage/default/66.chip_sw_all_escalation_resets.2194972569
95.33 0.04 94.49 0.01 92.55 0.01 94.37 0.01 94.71 0.01 97.55 0.17 98.31 0.01 /workspace/coverage/default/88.chip_sw_all_escalation_resets.201233498
95.36 0.03 94.53 0.03 92.60 0.05 94.48 0.11 94.72 0.01 97.55 0.00 98.31 0.00 /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2515531627
95.40 0.03 94.56 0.03 92.65 0.05 94.56 0.08 94.74 0.02 97.55 0.00 98.31 0.00 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3059472214
95.42 0.03 94.63 0.07 92.68 0.03 94.57 0.01 94.79 0.05 97.55 0.00 98.31 0.00 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3512422429
95.45 0.03 94.63 0.00 92.84 0.16 94.57 0.00 94.79 0.00 97.55 0.00 98.31 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_0.3093165153
95.47 0.02 94.63 0.00 92.91 0.07 94.57 0.00 94.81 0.02 97.55 0.00 98.37 0.06 /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3907518855
95.50 0.02 94.65 0.02 92.98 0.07 94.58 0.02 94.85 0.04 97.55 0.00 98.37 0.00 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3055475617
95.52 0.02 94.72 0.07 93.03 0.05 94.58 0.00 94.87 0.02 97.55 0.00 98.37 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3174395275
95.54 0.02 94.72 0.00 93.03 0.00 94.70 0.12 94.87 0.00 97.55 0.00 98.37 0.00 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1576210744
95.56 0.02 94.75 0.03 93.08 0.05 94.71 0.01 94.90 0.02 97.55 0.00 98.37 0.00 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1680619386
95.58 0.02 94.80 0.05 93.13 0.05 94.71 0.00 94.91 0.02 97.55 0.00 98.37 0.00 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3958275994
95.60 0.02 94.80 0.00 93.25 0.12 94.71 0.00 94.91 0.00 97.55 0.00 98.37 0.00 /workspace/coverage/cover_reg_top/18.chip_tl_errors.4273355846
95.62 0.02 94.80 0.00 93.30 0.05 94.71 0.00 94.93 0.02 97.55 0.00 98.40 0.04 /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3692313414
95.63 0.02 94.85 0.05 93.33 0.03 94.72 0.01 94.94 0.01 97.55 0.00 98.40 0.00 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4152636741
95.65 0.02 94.85 0.00 93.39 0.05 94.72 0.00 94.95 0.02 97.55 0.00 98.43 0.02 /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.4246761239
95.66 0.02 94.85 0.01 93.41 0.03 94.76 0.04 94.96 0.01 97.55 0.00 98.44 0.01 /workspace/coverage/default/93.chip_sw_all_escalation_resets.3562058955
95.68 0.01 94.90 0.04 93.44 0.02 94.78 0.02 94.96 0.00 97.55 0.00 98.44 0.00 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2237931576
95.69 0.01 94.90 0.00 93.44 0.00 94.86 0.08 94.96 0.00 97.55 0.00 98.44 0.00 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1960963468
95.70 0.01 94.90 0.00 93.52 0.08 94.86 0.00 94.96 0.00 97.55 0.00 98.44 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_0.4229440019
95.72 0.01 94.90 0.00 93.52 0.00 94.86 0.00 94.96 0.00 97.55 0.00 98.51 0.07 /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.2113998668
95.73 0.01 94.90 0.00 93.58 0.06 94.86 0.00 94.96 0.00 97.55 0.00 98.51 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_20.2174933391
95.74 0.01 94.90 0.00 93.60 0.02 94.86 0.00 94.97 0.01 97.55 0.00 98.54 0.04 /workspace/coverage/cover_reg_top/16.xbar_stress_all.2129866814
95.75 0.01 94.90 0.00 93.60 0.00 94.92 0.06 94.97 0.00 97.55 0.00 98.54 0.00 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2798059401
95.76 0.01 94.90 0.00 93.62 0.02 94.92 0.00 94.97 0.00 97.55 0.00 98.58 0.04 /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.4020942083
95.77 0.01 94.91 0.02 93.63 0.01 94.94 0.01 94.99 0.02 97.55 0.00 98.58 0.00 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2106409666
95.77 0.01 94.94 0.02 93.64 0.01 94.94 0.01 95.00 0.02 97.55 0.00 98.58 0.00 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1889846932
95.78 0.01 94.96 0.02 93.64 0.01 94.94 0.01 95.02 0.02 97.55 0.00 98.58 0.00 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.548307930
95.79 0.01 94.96 0.01 93.69 0.04 94.94 0.00 95.02 0.00 97.55 0.00 98.58 0.00 /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.2240507541
95.80 0.01 94.96 0.00 93.72 0.04 94.95 0.01 95.02 0.00 97.55 0.00 98.58 0.00 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3598600979
95.80 0.01 94.96 0.00 93.76 0.04 94.95 0.01 95.02 0.00 97.55 0.00 98.58 0.00 /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.574690393
95.81 0.01 94.96 0.00 93.76 0.00 94.99 0.04 95.02 0.00 97.55 0.00 98.58 0.00 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2337585293
95.82 0.01 94.96 0.00 93.80 0.04 94.99 0.00 95.02 0.00 97.55 0.00 98.58 0.00 /workspace/coverage/cover_reg_top/20.chip_tl_errors.3306539831
95.82 0.01 94.96 0.00 93.80 0.01 94.99 0.00 95.02 0.00 97.55 0.00 98.61 0.04 /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2787207273
95.83 0.01 94.96 0.00 93.80 0.00 95.03 0.04 95.02 0.00 97.55 0.00 98.61 0.00 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2959255075
95.84 0.01 94.96 0.00 93.80 0.00 95.07 0.04 95.02 0.00 97.55 0.00 98.61 0.00 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3745087171
95.84 0.01 94.96 0.00 93.80 0.00 95.07 0.00 95.02 0.00 97.55 0.00 98.65 0.04 /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.1393767172
95.85 0.01 94.96 0.00 93.80 0.00 95.10 0.04 95.02 0.00 97.55 0.00 98.65 0.00 /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.326789372
95.85 0.01 94.96 0.00 93.80 0.00 95.14 0.04 95.02 0.00 97.55 0.00 98.65 0.00 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2683034517
95.86 0.01 94.96 0.00 93.83 0.03 95.14 0.00 95.02 0.00 97.55 0.00 98.65 0.00 /workspace/coverage/default/2.chip_sw_gpio.3513670555
95.86 0.01 94.96 0.00 93.83 0.01 95.17 0.03 95.02 0.00 97.55 0.00 98.65 0.00 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2574852888
95.87 0.01 94.96 0.00 93.84 0.01 95.17 0.00 95.02 0.00 97.55 0.00 98.67 0.02 /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.230397882
95.87 0.01 94.97 0.01 93.84 0.00 95.19 0.02 95.02 0.00 97.55 0.00 98.67 0.00 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.4277603172
95.88 0.01 94.97 0.00 93.86 0.02 95.20 0.01 95.02 0.00 97.55 0.00 98.67 0.00 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1292381297
95.88 0.01 94.97 0.00 93.89 0.03 95.20 0.00 95.02 0.00 97.55 0.00 98.67 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_20.696720654
95.89 0.01 94.97 0.00 93.89 0.00 95.23 0.03 95.02 0.00 97.55 0.00 98.67 0.00 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3748238093
95.89 0.01 94.97 0.00 93.89 0.00 95.26 0.03 95.02 0.00 97.55 0.00 98.67 0.00 /workspace/coverage/default/2.chip_sw_kmac_entropy.3113388635
95.90 0.01 94.97 0.00 93.90 0.01 95.26 0.00 95.02 0.00 97.55 0.00 98.68 0.01 /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.572293953
95.90 0.01 94.97 0.00 93.92 0.01 95.26 0.00 95.02 0.00 97.55 0.00 98.70 0.01 /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.3429023011
95.91 0.01 94.97 0.00 93.94 0.02 95.26 0.00 95.02 0.00 97.55 0.00 98.70 0.00 /workspace/coverage/cover_reg_top/25.chip_tl_errors.2353876148
95.91 0.01 94.97 0.00 93.96 0.02 95.26 0.00 95.02 0.00 97.55 0.00 98.70 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_10.3860041535
95.91 0.01 94.99 0.02 93.97 0.01 95.26 0.00 95.02 0.00 97.55 0.00 98.70 0.00 /workspace/coverage/default/1.chip_jtag_csr_rw.1229125372
95.92 0.01 94.99 0.00 93.97 0.00 95.26 0.00 95.02 0.00 97.55 0.00 98.72 0.02 /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1909269962
95.92 0.01 94.99 0.00 93.97 0.00 95.28 0.02 95.02 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.635860893
95.93 0.01 94.99 0.00 93.97 0.00 95.30 0.02 95.02 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.330843013
95.93 0.01 94.99 0.00 93.98 0.01 95.30 0.00 95.02 0.00 97.55 0.00 98.73 0.01 /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.329270946
95.93 0.01 95.00 0.01 93.99 0.01 95.30 0.00 95.02 0.00 97.55 0.00 98.73 0.00 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1251513653
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96.14 0.01 95.03 0.00 94.17 0.00 95.42 0.01 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1461657850
96.14 0.01 95.03 0.00 94.17 0.00 95.43 0.01 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3205794372
96.14 0.01 95.03 0.00 94.17 0.00 95.43 0.01 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3620392308
96.14 0.01 95.03 0.00 94.17 0.00 95.44 0.01 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3175472223
96.14 0.01 95.03 0.00 94.17 0.00 95.44 0.01 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2779614502
96.14 0.01 95.03 0.00 94.17 0.01 95.44 0.00 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.1461126736
96.14 0.01 95.03 0.00 94.17 0.01 95.44 0.00 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.1813648372
96.14 0.01 95.03 0.00 94.18 0.01 95.44 0.00 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/cover_reg_top/23.chip_tl_errors.3515596547
96.15 0.01 95.03 0.00 94.18 0.01 95.44 0.00 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.2714001945
96.15 0.01 95.03 0.00 94.18 0.01 95.44 0.00 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.704643559
96.15 0.01 95.03 0.00 94.19 0.01 95.44 0.00 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.2137112679
96.15 0.01 95.03 0.00 94.19 0.01 95.44 0.00 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.2535413449
96.15 0.01 95.03 0.00 94.19 0.01 95.44 0.00 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.3845881953
96.15 0.01 95.03 0.00 94.20 0.01 95.44 0.00 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.1206805027
96.15 0.01 95.03 0.00 94.20 0.01 95.44 0.00 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/default/0.chip_sw_gpio.2740169354
96.15 0.01 95.03 0.00 94.20 0.01 95.44 0.00 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/default/0.chip_sw_hmac_enc.3963929358
96.15 0.01 95.03 0.00 94.21 0.01 95.44 0.00 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3324879512
96.15 0.01 95.03 0.00 94.21 0.01 95.44 0.00 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2846694075
96.15 0.01 95.03 0.00 94.21 0.00 95.45 0.01 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1873270049
96.15 0.01 95.03 0.00 94.21 0.00 95.45 0.01 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1077294036
96.15 0.01 95.03 0.00 94.21 0.00 95.45 0.01 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.602730997
96.15 0.01 95.03 0.00 94.21 0.00 95.45 0.01 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.632853321
96.15 0.01 95.03 0.00 94.21 0.00 95.45 0.01 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.659288536
96.15 0.01 95.03 0.00 94.21 0.00 95.46 0.01 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3556446853
96.15 0.01 95.03 0.00 94.21 0.00 95.46 0.01 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.640868823
96.15 0.01 95.03 0.00 94.21 0.00 95.46 0.01 95.03 0.00 97.55 0.00 99.64 0.00 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.339692350


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3313930146
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2037257988
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3300115289
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1402986605
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.351295820
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.213840353
/workspace/coverage/cover_reg_top/0.chip_tl_errors.3164967640
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.326044404
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.4074598158
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1946025485
/workspace/coverage/cover_reg_top/0.xbar_error_random.3052095182
/workspace/coverage/cover_reg_top/0.xbar_random.3775886471
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2987508223
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1216651813
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1824544253
/workspace/coverage/cover_reg_top/0.xbar_same_source.2247450667
/workspace/coverage/cover_reg_top/0.xbar_smoke.5836280
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2603708025
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.847375364
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1877098838
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3467156584
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.919453724
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3713449760
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3829008387
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2034615525
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2534351041
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1801976628
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1126564064
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.29221864
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2154150122
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1679850037
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.3795928405
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3385663373
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2944411505
/workspace/coverage/cover_reg_top/1.xbar_error_random.1409227524
/workspace/coverage/cover_reg_top/1.xbar_random.1427914763
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2793403742
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2434624676
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3799405947
/workspace/coverage/cover_reg_top/1.xbar_same_source.4162872192
/workspace/coverage/cover_reg_top/1.xbar_smoke.3445294285
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3729878058
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3209166330
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.4001789044
/workspace/coverage/cover_reg_top/1.xbar_stress_all.4134097858
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.844555539
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.551769222
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3362145747
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3056384845
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2313964474
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2840827364
/workspace/coverage/cover_reg_top/10.chip_tl_errors.2803964124
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1479747911
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2048438906
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.613244283
/workspace/coverage/cover_reg_top/10.xbar_error_random.4029246224
/workspace/coverage/cover_reg_top/10.xbar_random.3837297035
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3452588693
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1107201747
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.938335863
/workspace/coverage/cover_reg_top/10.xbar_same_source.3421088139
/workspace/coverage/cover_reg_top/10.xbar_smoke.4174697785
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3254002206
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1896022787
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3676850262
/workspace/coverage/cover_reg_top/10.xbar_stress_all.3230916904
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3145199459
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3843438855
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.2775814089
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2139099421
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.844331502
/workspace/coverage/cover_reg_top/11.chip_tl_errors.1498972899
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.361131277
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1164218377
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.722150103
/workspace/coverage/cover_reg_top/11.xbar_error_random.1088181709
/workspace/coverage/cover_reg_top/11.xbar_random.344078711
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.186671272
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3517009935
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1413201217
/workspace/coverage/cover_reg_top/11.xbar_same_source.4052526976
/workspace/coverage/cover_reg_top/11.xbar_smoke.1578021037
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2732307797
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2753566228
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3999528572
/workspace/coverage/cover_reg_top/11.xbar_stress_all.4262668124
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.264673534
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3744898729
/workspace/coverage/cover_reg_top/12.chip_csr_rw.100697630
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2274260130
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2651376510
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3493288476
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3941596448
/workspace/coverage/cover_reg_top/12.xbar_error_random.97868552
/workspace/coverage/cover_reg_top/12.xbar_random.541984361
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.4004723715
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2755214985
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2064420281
/workspace/coverage/cover_reg_top/12.xbar_same_source.614188135
/workspace/coverage/cover_reg_top/12.xbar_smoke.1043796095
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1828714600
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3979805562
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.4078072992
/workspace/coverage/cover_reg_top/12.xbar_stress_all.211985772
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1600579039
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.4172112464
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.111695027
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2276631851
/workspace/coverage/cover_reg_top/13.chip_csr_rw.4172852845
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.707742081
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.261387819
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.4147021059
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2745340543
/workspace/coverage/cover_reg_top/13.xbar_error_random.1238363712
/workspace/coverage/cover_reg_top/13.xbar_random.843306922
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1434406531
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.795315023
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3547589538
/workspace/coverage/cover_reg_top/13.xbar_same_source.234861851
/workspace/coverage/cover_reg_top/13.xbar_smoke.608306023
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3161968052
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1017109298
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3219683311
/workspace/coverage/cover_reg_top/13.xbar_stress_all.2848106111
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1149135560
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.291905316
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.962358755
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.370655742
/workspace/coverage/cover_reg_top/14.chip_csr_rw.3655647379
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.1097242647
/workspace/coverage/cover_reg_top/14.chip_tl_errors.4244388984
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.1900611606
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.2038242838
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1004333047
/workspace/coverage/cover_reg_top/14.xbar_error_random.3208171113
/workspace/coverage/cover_reg_top/14.xbar_random.661529124
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.417777151
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1500546460
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.64955870
/workspace/coverage/cover_reg_top/14.xbar_same_source.877218108
/workspace/coverage/cover_reg_top/14.xbar_smoke.2875453699
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2255320254
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1316608604
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3759797740
/workspace/coverage/cover_reg_top/14.xbar_stress_all.1685527221
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.3109526120
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.5751939
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.1426701894
/workspace/coverage/cover_reg_top/15.chip_csr_rw.965776042
/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.917882658
/workspace/coverage/cover_reg_top/15.chip_tl_errors.909061141
/workspace/coverage/cover_reg_top/15.xbar_access_same_device.3097015105
/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.2359422343
/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2266521688
/workspace/coverage/cover_reg_top/15.xbar_error_random.2807104948
/workspace/coverage/cover_reg_top/15.xbar_random.4065274230
/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.2444263693
/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.1250863504
/workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.4105652790
/workspace/coverage/cover_reg_top/15.xbar_same_source.2019333223
/workspace/coverage/cover_reg_top/15.xbar_smoke.1484957470
/workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.696076214
/workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2505951500
/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.4257284231
/workspace/coverage/cover_reg_top/15.xbar_stress_all.3784881456
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.942557846
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3115833048
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.2753044241
/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.1742899136
/workspace/coverage/cover_reg_top/16.chip_csr_rw.2889664108
/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.1182311409
/workspace/coverage/cover_reg_top/16.chip_tl_errors.3007805579
/workspace/coverage/cover_reg_top/16.xbar_access_same_device.886526027
/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2095767687
/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.2478553435
/workspace/coverage/cover_reg_top/16.xbar_error_random.2473405542
/workspace/coverage/cover_reg_top/16.xbar_random.2894726573
/workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2384910297
/workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.2199536583
/workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.3669848333
/workspace/coverage/cover_reg_top/16.xbar_same_source.3427535794
/workspace/coverage/cover_reg_top/16.xbar_smoke.140810549
/workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.2632376291
/workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.4085518830
/workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1352178913
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.1091409950
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.584185057
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.503048712
/workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.326449167
/workspace/coverage/cover_reg_top/17.chip_csr_rw.900611055
/workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.76229245
/workspace/coverage/cover_reg_top/17.xbar_access_same_device.774611664
/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.3037345386
/workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.1973290452
/workspace/coverage/cover_reg_top/17.xbar_error_random.4185708427
/workspace/coverage/cover_reg_top/17.xbar_random.3850486997
/workspace/coverage/cover_reg_top/17.xbar_random_large_delays.3198131983
/workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.1070985351
/workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.2396422661
/workspace/coverage/cover_reg_top/17.xbar_same_source.171790130
/workspace/coverage/cover_reg_top/17.xbar_smoke.2392109191
/workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.1358989404
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/workspace/coverage/default/42.chip_sw_all_escalation_resets.163949658
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.4027330379
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1050108084
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1733437303
/workspace/coverage/default/44.chip_sw_all_escalation_resets.3198486171
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2872098762
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1489347743
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3012212536
/workspace/coverage/default/47.chip_sw_all_escalation_resets.3105711799
/workspace/coverage/default/48.chip_sw_all_escalation_resets.1526560403
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3193756489
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2915813424
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3164717889
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3151082433
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1514148462
/workspace/coverage/default/50.chip_sw_all_escalation_resets.4054064177
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2127551754
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2910488556
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3137016286
/workspace/coverage/default/52.chip_sw_all_escalation_resets.944194434
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3423105582
/workspace/coverage/default/53.chip_sw_all_escalation_resets.3144668015
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3907466585
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2204637978
/workspace/coverage/default/56.chip_sw_all_escalation_resets.1611893892
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3287056493
/workspace/coverage/default/57.chip_sw_all_escalation_resets.271744391
/workspace/coverage/default/58.chip_sw_all_escalation_resets.2844609632
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3549532407
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2054452668
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2217967441
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.4142188142
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3437433903
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3398721804
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3449850696
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.800329304
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.215540308
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3294657851
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1968089639
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3295217569
/workspace/coverage/default/64.chip_sw_all_escalation_resets.162867108
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.876723664
/workspace/coverage/default/65.chip_sw_all_escalation_resets.3096764364
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2867517972
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1540053533
/workspace/coverage/default/69.chip_sw_all_escalation_resets.44344951
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.948842586
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3147643299
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2564062315
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.827857402
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.261271027
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2038362924
/workspace/coverage/default/70.chip_sw_all_escalation_resets.1773128911
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1302556652
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3162060584
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1313768365
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3536780105
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2786774894
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1088139065
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3606957299
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2663997952
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4062655625
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1906084706
/workspace/coverage/default/76.chip_sw_all_escalation_resets.368912858
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3756017125
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3933499002
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3814705677
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3384685420
/workspace/coverage/default/79.chip_sw_all_escalation_resets.212624037
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4238744963
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2428671230
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3828344778
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.184189435
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1769063609
/workspace/coverage/default/80.chip_sw_all_escalation_resets.7803701
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2032460846
/workspace/coverage/default/81.chip_sw_all_escalation_resets.100386325
/workspace/coverage/default/82.chip_sw_all_escalation_resets.42640107
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3856935680
/workspace/coverage/default/84.chip_sw_all_escalation_resets.3338745302
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2174673039
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2929725536
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.326414446
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1932952596
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1860245743
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3494340419
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1375148315
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4043224540
/workspace/coverage/default/9.chip_sw_all_escalation_resets.620116630
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.4085097823
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3300505429
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3847290666
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2556907250
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3513021026
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2674458196
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1560767021
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3354375052
/workspace/coverage/default/96.chip_sw_all_escalation_resets.662173602
/workspace/coverage/default/97.chip_sw_all_escalation_resets.2955674697
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2112765559
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3261427342
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2173966058
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1437215675
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2146837834
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.248489283
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1607215817
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3501073323
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3457965336




Total test records in report: 2904
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspace/coverage/default/0.chip_sw_csrng_kat_test.3050474432 Jul 06 07:31:25 PM PDT 24 Jul 06 07:35:52 PM PDT 24 3204463424 ps
T5 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2302973675 Jul 06 07:35:57 PM PDT 24 Jul 06 07:48:02 PM PDT 24 5091582052 ps
T6 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.4289725148 Jul 06 07:33:21 PM PDT 24 Jul 06 07:53:49 PM PDT 24 7858536408 ps
T17 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.206837347 Jul 06 07:39:24 PM PDT 24 Jul 06 07:51:29 PM PDT 24 8537546912 ps
T45 /workspace/coverage/default/55.chip_sw_all_escalation_resets.661450440 Jul 06 08:01:54 PM PDT 24 Jul 06 08:12:56 PM PDT 24 4418832554 ps
T85 /workspace/coverage/default/0.chip_sw_aes_masking_off.3062338833 Jul 06 07:31:25 PM PDT 24 Jul 06 07:36:49 PM PDT 24 3359357692 ps
T55 /workspace/coverage/default/2.rom_e2e_static_critical.353152907 Jul 06 07:56:09 PM PDT 24 Jul 06 09:06:25 PM PDT 24 17181674800 ps
T86 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2035922864 Jul 06 07:32:03 PM PDT 24 Jul 06 07:50:15 PM PDT 24 6965473572 ps
T66 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2820483862 Jul 06 07:27:40 PM PDT 24 Jul 06 07:40:34 PM PDT 24 4703273822 ps
T63 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.669455007 Jul 06 08:02:50 PM PDT 24 Jul 06 08:10:52 PM PDT 24 4156493160 ps
T59 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2683034517 Jul 06 07:40:10 PM PDT 24 Jul 06 07:51:45 PM PDT 24 4558954952 ps
T227 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1292381297 Jul 06 08:00:05 PM PDT 24 Jul 06 08:24:46 PM PDT 24 7543122640 ps
T56 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1471963848 Jul 06 07:58:40 PM PDT 24 Jul 06 09:03:18 PM PDT 24 15645844427 ps
T199 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.217174602 Jul 06 07:46:19 PM PDT 24 Jul 06 07:54:29 PM PDT 24 5086322071 ps
T57 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.158652432 Jul 06 07:51:16 PM PDT 24 Jul 06 08:03:06 PM PDT 24 4947541759 ps
T110 /workspace/coverage/default/0.chip_sw_power_sleep_load.2044118013 Jul 06 07:34:09 PM PDT 24 Jul 06 07:44:53 PM PDT 24 11262942300 ps
T296 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3606957299 Jul 06 08:03:14 PM PDT 24 Jul 06 08:08:49 PM PDT 24 3500082268 ps
T81 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.690428466 Jul 06 07:31:26 PM PDT 24 Jul 06 07:37:59 PM PDT 24 2905346583 ps
T18 /workspace/coverage/default/0.rom_e2e_shutdown_output.941251929 Jul 06 07:34:16 PM PDT 24 Jul 06 08:43:13 PM PDT 24 23763511793 ps
T168 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.4027330379 Jul 06 08:00:39 PM PDT 24 Jul 06 08:06:40 PM PDT 24 4387908288 ps
T322 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2291694489 Jul 06 07:33:09 PM PDT 24 Jul 06 07:43:29 PM PDT 24 3935811040 ps
T388 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3933499002 Jul 06 08:04:31 PM PDT 24 Jul 06 08:12:32 PM PDT 24 3575343352 ps
T159 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1576210744 Jul 06 07:28:36 PM PDT 24 Jul 06 07:49:50 PM PDT 24 9192615594 ps
T60 /workspace/coverage/default/0.chip_sw_alert_test.1228411915 Jul 06 07:31:49 PM PDT 24 Jul 06 07:37:05 PM PDT 24 2689185600 ps
T185 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.760237993 Jul 06 07:30:31 PM PDT 24 Jul 06 07:49:08 PM PDT 24 8084981020 ps
T116 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.958982022 Jul 06 07:31:55 PM PDT 24 Jul 06 07:36:20 PM PDT 24 2907932723 ps
T694 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1472971421 Jul 06 07:57:29 PM PDT 24 Jul 06 08:04:02 PM PDT 24 3623515052 ps
T186 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2211444208 Jul 06 07:29:16 PM PDT 24 Jul 06 07:50:18 PM PDT 24 9052043860 ps
T73 /workspace/coverage/default/2.chip_tap_straps_prod.3855258612 Jul 06 07:50:38 PM PDT 24 Jul 06 08:04:23 PM PDT 24 7620752848 ps
T857 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2378422711 Jul 06 07:37:15 PM PDT 24 Jul 06 07:42:40 PM PDT 24 3321366182 ps
T318 /workspace/coverage/default/2.chip_plic_all_irqs_20.2272962855 Jul 06 07:50:34 PM PDT 24 Jul 06 08:05:52 PM PDT 24 5223322604 ps
T208 /workspace/coverage/default/34.chip_sw_all_escalation_resets.3127694140 Jul 06 07:59:43 PM PDT 24 Jul 06 08:10:39 PM PDT 24 5859426500 ps
T195 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2474381345 Jul 06 07:31:05 PM PDT 24 Jul 06 07:40:03 PM PDT 24 4030675376 ps
T190 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1537451350 Jul 06 07:53:41 PM PDT 24 Jul 06 08:03:10 PM PDT 24 5758487684 ps
T58 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1472123146 Jul 06 07:49:47 PM PDT 24 Jul 06 07:59:30 PM PDT 24 4449049030 ps
T294 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3398721804 Jul 06 08:03:42 PM PDT 24 Jul 06 08:11:38 PM PDT 24 3566728252 ps
T295 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.555662476 Jul 06 07:59:43 PM PDT 24 Jul 06 08:05:21 PM PDT 24 3436708168 ps
T267 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1155686792 Jul 06 07:48:02 PM PDT 24 Jul 06 08:13:14 PM PDT 24 13854544027 ps
T232 /workspace/coverage/default/99.chip_sw_all_escalation_resets.3593748234 Jul 06 08:05:12 PM PDT 24 Jul 06 08:15:20 PM PDT 24 4240392750 ps
T127 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.842188123 Jul 06 07:43:11 PM PDT 24 Jul 06 07:50:45 PM PDT 24 3255640884 ps
T33 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3894344076 Jul 06 07:46:42 PM PDT 24 Jul 06 07:53:50 PM PDT 24 3686925490 ps
T117 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1382348883 Jul 06 07:37:43 PM PDT 24 Jul 06 07:42:50 PM PDT 24 2743431614 ps
T118 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3546692881 Jul 06 07:31:34 PM PDT 24 Jul 06 07:36:19 PM PDT 24 2696387526 ps
T265 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2428538131 Jul 06 07:54:34 PM PDT 24 Jul 06 07:58:34 PM PDT 24 2938062660 ps
T19 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1941562042 Jul 06 07:36:07 PM PDT 24 Jul 06 07:38:55 PM PDT 24 4188003744 ps
T153 /workspace/coverage/default/1.chip_sw_power_idle_load.2717435084 Jul 06 07:43:13 PM PDT 24 Jul 06 07:54:43 PM PDT 24 4350325440 ps
T128 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1253493550 Jul 06 07:50:12 PM PDT 24 Jul 06 08:13:57 PM PDT 24 5546731696 ps
T20 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1952900159 Jul 06 07:38:50 PM PDT 24 Jul 06 09:38:56 PM PDT 24 23949171050 ps
T64 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.805254253 Jul 06 07:32:36 PM PDT 24 Jul 06 08:10:01 PM PDT 24 26370399782 ps
T129 /workspace/coverage/default/1.chip_sw_otbn_randomness.2161390212 Jul 06 07:38:15 PM PDT 24 Jul 06 07:54:43 PM PDT 24 6325911768 ps
T387 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2096061603 Jul 06 07:36:28 PM PDT 24 Jul 06 08:50:45 PM PDT 24 15603236260 ps
T30 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2244890495 Jul 06 07:30:59 PM PDT 24 Jul 06 07:37:01 PM PDT 24 5489862904 ps
T676 /workspace/coverage/default/0.chip_sw_hmac_smoketest.787572074 Jul 06 07:33:28 PM PDT 24 Jul 06 07:38:35 PM PDT 24 3094512470 ps
T27 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3059472214 Jul 06 07:29:31 PM PDT 24 Jul 06 07:50:13 PM PDT 24 8866696817 ps
T696 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3384685420 Jul 06 08:04:37 PM PDT 24 Jul 06 08:12:14 PM PDT 24 3892547896 ps
T166 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3756017125 Jul 06 08:03:34 PM PDT 24 Jul 06 08:11:17 PM PDT 24 3848741240 ps
T441 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2941212499 Jul 06 07:44:37 PM PDT 24 Jul 06 07:47:47 PM PDT 24 3157659448 ps
T233 /workspace/coverage/default/93.chip_sw_all_escalation_resets.3562058955 Jul 06 08:04:46 PM PDT 24 Jul 06 08:13:15 PM PDT 24 4663254900 ps
T234 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2346083464 Jul 06 07:54:35 PM PDT 24 Jul 06 08:08:24 PM PDT 24 4991425166 ps
T175 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2844959660 Jul 06 07:57:43 PM PDT 24 Jul 06 08:43:38 PM PDT 24 11523898135 ps
T858 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.464207387 Jul 06 07:30:42 PM PDT 24 Jul 06 07:39:46 PM PDT 24 3935725500 ps
T416 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3288593559 Jul 06 07:58:23 PM PDT 24 Jul 06 08:04:11 PM PDT 24 3612113512 ps
T196 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1880296174 Jul 06 07:27:39 PM PDT 24 Jul 06 07:37:30 PM PDT 24 5499655990 ps
T223 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3240772884 Jul 06 07:29:19 PM PDT 24 Jul 06 07:34:21 PM PDT 24 3387334450 ps
T410 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1000377950 Jul 06 07:47:34 PM PDT 24 Jul 06 08:45:09 PM PDT 24 14756328954 ps
T859 /workspace/coverage/default/0.chip_sw_coremark.1214386836 Jul 06 07:31:46 PM PDT 24 Jul 07 12:05:20 AM PDT 24 71658618896 ps
T70 /workspace/coverage/default/3.chip_tap_straps_dev.4011439605 Jul 06 07:53:39 PM PDT 24 Jul 06 07:58:39 PM PDT 24 4275076524 ps
T675 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2442836037 Jul 06 07:51:44 PM PDT 24 Jul 06 07:55:32 PM PDT 24 2903412934 ps
T191 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2708915245 Jul 06 07:31:23 PM PDT 24 Jul 06 07:41:24 PM PDT 24 4735937144 ps
T351 /workspace/coverage/default/13.chip_sw_all_escalation_resets.2984870656 Jul 06 07:57:13 PM PDT 24 Jul 06 08:07:00 PM PDT 24 5106509330 ps
T352 /workspace/coverage/default/12.chip_sw_all_escalation_resets.3522365128 Jul 06 07:57:04 PM PDT 24 Jul 06 08:09:23 PM PDT 24 6065698996 ps
T31 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3055475617 Jul 06 07:28:47 PM PDT 24 Jul 06 07:37:45 PM PDT 24 3580128534 ps
T24 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3404014491 Jul 06 07:38:37 PM PDT 24 Jul 06 07:50:41 PM PDT 24 5093632196 ps
T681 /workspace/coverage/default/41.chip_sw_all_escalation_resets.3621281211 Jul 06 07:59:39 PM PDT 24 Jul 06 08:11:18 PM PDT 24 5123507024 ps
T124 /workspace/coverage/default/2.chip_sw_edn_boot_mode.2558353747 Jul 06 07:51:25 PM PDT 24 Jul 06 08:01:26 PM PDT 24 3420039080 ps
T860 /workspace/coverage/default/0.chip_sw_example_concurrency.1327257869 Jul 06 07:29:25 PM PDT 24 Jul 06 07:33:18 PM PDT 24 2801125316 ps
T397 /workspace/coverage/default/35.chip_sw_all_escalation_resets.1057117082 Jul 06 08:00:28 PM PDT 24 Jul 06 08:12:50 PM PDT 24 6231508056 ps
T695 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2979985377 Jul 06 08:00:04 PM PDT 24 Jul 06 08:08:36 PM PDT 24 3352771960 ps
T238 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.302744695 Jul 06 07:46:27 PM PDT 24 Jul 06 08:12:29 PM PDT 24 8964896440 ps
T317 /workspace/coverage/default/52.chip_sw_all_escalation_resets.944194434 Jul 06 08:01:08 PM PDT 24 Jul 06 08:10:57 PM PDT 24 5488735414 ps
T411 /workspace/coverage/default/0.rom_e2e_static_critical.2270663075 Jul 06 07:35:29 PM PDT 24 Jul 06 08:45:50 PM PDT 24 16680391516 ps
T132 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3358866850 Jul 06 07:36:06 PM PDT 24 Jul 06 07:42:08 PM PDT 24 4844532712 ps
T342 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1312021732 Jul 06 07:27:08 PM PDT 24 Jul 06 07:32:44 PM PDT 24 3535715420 ps
T861 /workspace/coverage/default/2.rom_e2e_smoke.1618426303 Jul 06 07:59:13 PM PDT 24 Jul 06 09:07:40 PM PDT 24 14970736830 ps
T682 /workspace/coverage/default/19.chip_sw_all_escalation_resets.2572484357 Jul 06 07:59:10 PM PDT 24 Jul 06 08:11:50 PM PDT 24 5224928800 ps
T862 /workspace/coverage/default/0.rom_e2e_smoke.1735642820 Jul 06 07:35:27 PM PDT 24 Jul 06 08:43:08 PM PDT 24 14799763112 ps
T863 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1339130183 Jul 06 07:40:21 PM PDT 24 Jul 06 07:50:24 PM PDT 24 3846682280 ps
T315 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3109556885 Jul 06 07:56:44 PM PDT 24 Jul 06 08:03:57 PM PDT 24 3903013684 ps
T121 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1527876259 Jul 06 07:35:21 PM PDT 24 Jul 06 08:08:12 PM PDT 24 8003303150 ps
T162 /workspace/coverage/default/1.chip_plic_all_irqs_10.604580485 Jul 06 07:39:34 PM PDT 24 Jul 06 07:49:36 PM PDT 24 4588516784 ps
T65 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2798059401 Jul 06 07:31:21 PM PDT 24 Jul 06 07:50:29 PM PDT 24 10331506570 ps
T326 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1857430995 Jul 06 07:46:26 PM PDT 24 Jul 06 08:15:11 PM PDT 24 11076552734 ps
T114 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3883335799 Jul 06 07:36:22 PM PDT 24 Jul 06 08:46:48 PM PDT 24 18638832200 ps
T271 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1358034456 Jul 06 07:31:29 PM PDT 24 Jul 06 08:49:44 PM PDT 24 16423998032 ps
T646 /workspace/coverage/default/2.chip_sw_aes_masking_off.177634365 Jul 06 07:49:25 PM PDT 24 Jul 06 07:55:20 PM PDT 24 3620772345 ps
T224 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2351367165 Jul 06 07:50:10 PM PDT 24 Jul 06 08:28:15 PM PDT 24 8912430004 ps
T169 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1879746561 Jul 06 07:37:51 PM PDT 24 Jul 06 07:47:02 PM PDT 24 4614007804 ps
T864 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.4013216469 Jul 06 07:35:34 PM PDT 24 Jul 06 08:50:25 PM PDT 24 15067565292 ps
T179 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3620392308 Jul 06 07:36:24 PM PDT 24 Jul 06 07:42:37 PM PDT 24 4558206026 ps
T703 /workspace/coverage/default/51.chip_sw_all_escalation_resets.2910488556 Jul 06 08:00:36 PM PDT 24 Jul 06 08:12:54 PM PDT 24 5527530444 ps
T314 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2174673039 Jul 06 08:04:10 PM PDT 24 Jul 06 08:10:30 PM PDT 24 4212487880 ps
T197 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2821590443 Jul 06 07:36:34 PM PDT 24 Jul 06 07:43:21 PM PDT 24 4750960792 ps
T67 /workspace/coverage/default/1.chip_tap_straps_rma.1813302514 Jul 06 07:39:13 PM PDT 24 Jul 06 07:49:49 PM PDT 24 6494688608 ps
T693 /workspace/coverage/default/47.chip_sw_all_escalation_resets.3105711799 Jul 06 08:04:16 PM PDT 24 Jul 06 08:14:36 PM PDT 24 5393209610 ps
T111 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2574852888 Jul 06 07:30:47 PM PDT 24 Jul 06 07:38:32 PM PDT 24 18404610384 ps
T334 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1570284678 Jul 06 07:32:50 PM PDT 24 Jul 06 07:46:03 PM PDT 24 4616311080 ps
T684 /workspace/coverage/default/86.chip_sw_all_escalation_resets.2363284142 Jul 06 08:04:52 PM PDT 24 Jul 06 08:15:19 PM PDT 24 4327837544 ps
T231 /workspace/coverage/default/3.chip_sw_uart_tx_rx.1483129525 Jul 06 07:54:33 PM PDT 24 Jul 06 08:06:04 PM PDT 24 4564027340 ps
T348 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.4164857046 Jul 06 07:45:45 PM PDT 24 Jul 06 07:57:28 PM PDT 24 3456552140 ps
T112 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2784938260 Jul 06 07:42:57 PM PDT 24 Jul 07 02:57:14 AM PDT 24 192817354896 ps
T229 /workspace/coverage/default/1.chip_sw_pattgen_ios.181611109 Jul 06 07:32:28 PM PDT 24 Jul 06 07:37:18 PM PDT 24 2973376840 ps
T710 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3553491408 Jul 06 08:02:08 PM PDT 24 Jul 06 08:09:58 PM PDT 24 3841377034 ps
T698 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.4050052390 Jul 06 07:45:00 PM PDT 24 Jul 06 07:59:23 PM PDT 24 5298998090 ps
T450 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2424296003 Jul 06 07:53:27 PM PDT 24 Jul 06 07:58:00 PM PDT 24 3209976000 ps
T363 /workspace/coverage/default/62.chip_sw_all_escalation_resets.3294657851 Jul 06 08:02:41 PM PDT 24 Jul 06 08:11:31 PM PDT 24 4174577698 ps
T207 /workspace/coverage/default/4.chip_tap_straps_prod.3585056054 Jul 06 07:55:26 PM PDT 24 Jul 06 07:57:38 PM PDT 24 3097196326 ps
T25 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.161745446 Jul 06 07:34:01 PM PDT 24 Jul 06 07:38:39 PM PDT 24 3070081224 ps
T451 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2970020859 Jul 06 07:34:30 PM PDT 24 Jul 06 07:39:38 PM PDT 24 3504904424 ps
T865 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.3360032961 Jul 06 07:36:22 PM PDT 24 Jul 06 07:41:35 PM PDT 24 3153949400 ps
T349 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2445393126 Jul 06 07:41:06 PM PDT 24 Jul 06 07:45:26 PM PDT 24 2515935433 ps
T228 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3522477234 Jul 06 07:53:58 PM PDT 24 Jul 06 08:07:01 PM PDT 24 4805383218 ps
T259 /workspace/coverage/default/5.chip_sw_all_escalation_resets.690566737 Jul 06 07:56:16 PM PDT 24 Jul 06 08:04:42 PM PDT 24 5100995666 ps
T237 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3972021921 Jul 06 07:49:05 PM PDT 24 Jul 06 08:19:58 PM PDT 24 8921590568 ps
T275 /workspace/coverage/default/1.rom_keymgr_functest.2275560075 Jul 06 07:42:38 PM PDT 24 Jul 06 07:50:05 PM PDT 24 3413147682 ps
T240 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1151717394 Jul 06 07:36:47 PM PDT 24 Jul 06 08:16:00 PM PDT 24 9412844870 ps
T276 /workspace/coverage/default/0.chip_sw_aes_idle.410795221 Jul 06 07:28:27 PM PDT 24 Jul 06 07:32:44 PM PDT 24 2119179440 ps
T28 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.652483066 Jul 06 07:38:21 PM PDT 24 Jul 06 07:47:41 PM PDT 24 4544101024 ps
T115 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3745087171 Jul 06 07:40:32 PM PDT 24 Jul 06 08:14:29 PM PDT 24 10797250889 ps
T54 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3193690230 Jul 06 07:36:31 PM PDT 24 Jul 06 08:40:51 PM PDT 24 14519289284 ps
T277 /workspace/coverage/default/0.chip_sw_csrng_smoketest.4233908947 Jul 06 07:34:29 PM PDT 24 Jul 06 07:37:47 PM PDT 24 2445287108 ps
T1 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2334639499 Jul 06 07:53:18 PM PDT 24 Jul 06 08:00:10 PM PDT 24 7222335114 ps
T71 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3205794372 Jul 06 07:29:53 PM PDT 24 Jul 06 10:23:49 PM PDT 24 60051947580 ps
T103 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2184982463 Jul 06 07:48:03 PM PDT 24 Jul 06 08:12:25 PM PDT 24 7942046866 ps
T104 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2533686393 Jul 06 07:48:34 PM PDT 24 Jul 06 07:53:59 PM PDT 24 3735903720 ps
T105 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3497003088 Jul 06 07:29:25 PM PDT 24 Jul 06 07:36:00 PM PDT 24 3470523475 ps
T2 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1168122574 Jul 06 07:34:30 PM PDT 24 Jul 06 08:10:29 PM PDT 24 27088173210 ps
T106 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.4028492693 Jul 06 07:59:11 PM PDT 24 Jul 06 08:04:52 PM PDT 24 3710121712 ps
T107 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1621113445 Jul 06 07:31:03 PM PDT 24 Jul 06 07:34:57 PM PDT 24 2966958720 ps
T108 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2032460846 Jul 06 08:04:08 PM PDT 24 Jul 06 08:09:42 PM PDT 24 3436277840 ps
T109 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.824448998 Jul 06 08:00:20 PM PDT 24 Jul 06 08:30:59 PM PDT 24 8851576994 ps
T173 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3916661207 Jul 06 07:48:37 PM PDT 24 Jul 06 07:50:32 PM PDT 24 2380631992 ps
T866 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1014961299 Jul 06 07:37:52 PM PDT 24 Jul 06 08:51:09 PM PDT 24 14384149100 ps
T741 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3423105582 Jul 06 08:01:32 PM PDT 24 Jul 06 08:09:22 PM PDT 24 4284790192 ps
T867 /workspace/coverage/default/0.chip_tap_straps_prod.321431355 Jul 06 07:31:07 PM PDT 24 Jul 06 07:33:46 PM PDT 24 2189111667 ps
T355 /workspace/coverage/default/61.chip_sw_all_escalation_resets.576407577 Jul 06 08:01:36 PM PDT 24 Jul 06 08:14:33 PM PDT 24 5475228648 ps
T180 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.2851728662 Jul 06 07:51:34 PM PDT 24 Jul 06 08:01:04 PM PDT 24 5986072040 ps
T174 /workspace/coverage/default/1.rom_volatile_raw_unlock.1072177642 Jul 06 07:42:54 PM PDT 24 Jul 06 07:44:59 PM PDT 24 3109803597 ps
T868 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2143823114 Jul 06 07:30:51 PM PDT 24 Jul 06 07:36:47 PM PDT 24 3393203168 ps
T225 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1251513653 Jul 06 07:47:05 PM PDT 24 Jul 06 08:01:48 PM PDT 24 4854390852 ps
T869 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1000328291 Jul 06 07:46:49 PM PDT 24 Jul 06 07:56:17 PM PDT 24 5998613576 ps
T412 /workspace/coverage/default/59.chip_sw_all_escalation_resets.3549532407 Jul 06 08:02:20 PM PDT 24 Jul 06 08:11:52 PM PDT 24 5143909324 ps
T368 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.267992020 Jul 06 07:47:34 PM PDT 24 Jul 06 07:55:07 PM PDT 24 3665576600 ps
T870 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2797387457 Jul 06 07:56:40 PM PDT 24 Jul 06 08:02:21 PM PDT 24 3072874180 ps
T278 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1019877256 Jul 06 07:36:29 PM PDT 24 Jul 06 09:23:43 PM PDT 24 23199000140 ps
T119 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3590424080 Jul 06 07:34:54 PM PDT 24 Jul 06 07:56:15 PM PDT 24 6699567959 ps
T125 /workspace/coverage/default/0.chip_sw_edn_auto_mode.1177748826 Jul 06 07:27:03 PM PDT 24 Jul 06 07:43:01 PM PDT 24 5397632636 ps
T677 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2227228092 Jul 06 08:05:16 PM PDT 24 Jul 06 08:11:39 PM PDT 24 3698497750 ps
T871 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2536023056 Jul 06 07:43:09 PM PDT 24 Jul 06 07:47:21 PM PDT 24 3024183644 ps
T182 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3030324453 Jul 06 07:41:56 PM PDT 24 Jul 06 08:16:16 PM PDT 24 20571900891 ps
T126 /workspace/coverage/default/1.chip_sw_edn_kat.3065877805 Jul 06 07:37:02 PM PDT 24 Jul 06 07:47:10 PM PDT 24 3417241900 ps
T389 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2740417946 Jul 06 07:36:02 PM PDT 24 Jul 06 07:40:55 PM PDT 24 2625179750 ps
T82 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3345703754 Jul 06 07:36:35 PM PDT 24 Jul 06 07:41:54 PM PDT 24 3295165188 ps
T872 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3234551458 Jul 06 07:35:18 PM PDT 24 Jul 06 07:47:04 PM PDT 24 4263793034 ps
T873 /workspace/coverage/default/1.chip_sw_aes_enc.2502370790 Jul 06 07:36:49 PM PDT 24 Jul 06 07:43:43 PM PDT 24 3553980984 ps
T356 /workspace/coverage/default/96.chip_sw_all_escalation_resets.662173602 Jul 06 08:04:59 PM PDT 24 Jul 06 08:15:32 PM PDT 24 5498548882 ps
T874 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2252056143 Jul 06 07:36:02 PM PDT 24 Jul 06 07:40:10 PM PDT 24 2817857752 ps
T700 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2672584651 Jul 06 07:39:05 PM PDT 24 Jul 06 07:58:14 PM PDT 24 7098452360 ps
T198 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2446147290 Jul 06 07:49:13 PM PDT 24 Jul 06 08:00:28 PM PDT 24 4599719536 ps
T875 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1426824918 Jul 06 07:53:15 PM PDT 24 Jul 06 07:57:16 PM PDT 24 3375921590 ps
T876 /workspace/coverage/default/1.chip_sw_example_manufacturer.945284499 Jul 06 07:31:51 PM PDT 24 Jul 06 07:35:09 PM PDT 24 2872837752 ps
T877 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1590902913 Jul 06 07:33:23 PM PDT 24 Jul 06 07:50:34 PM PDT 24 10552432058 ps
T878 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3054120501 Jul 06 07:46:27 PM PDT 24 Jul 06 07:51:07 PM PDT 24 2336736010 ps
T701 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.3747648606 Jul 06 07:30:02 PM PDT 24 Jul 06 07:48:35 PM PDT 24 8107038548 ps
T183 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.397050625 Jul 06 07:27:06 PM PDT 24 Jul 06 07:58:00 PM PDT 24 20107632377 ps
T289 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3322646245 Jul 06 07:37:41 PM PDT 24 Jul 06 07:44:22 PM PDT 24 3160151100 ps
T879 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.226119921 Jul 06 07:30:03 PM PDT 24 Jul 06 09:08:51 PM PDT 24 28274589450 ps
T378 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2904957836 Jul 06 07:51:50 PM PDT 24 Jul 06 08:00:42 PM PDT 24 5800991648 ps
T188 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2644500295 Jul 06 07:30:15 PM PDT 24 Jul 06 07:32:51 PM PDT 24 2884589406 ps
T29 /workspace/coverage/default/1.chip_sw_gpio.2480230210 Jul 06 07:34:29 PM PDT 24 Jul 06 07:44:25 PM PDT 24 4144598416 ps
T880 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3137016286 Jul 06 08:01:20 PM PDT 24 Jul 06 08:09:14 PM PDT 24 3887387072 ps
T154 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.632853321 Jul 06 07:29:10 PM PDT 24 Jul 06 08:36:48 PM PDT 24 17338746672 ps
T230 /workspace/coverage/default/2.chip_sw_pattgen_ios.1597138297 Jul 06 07:48:45 PM PDT 24 Jul 06 07:52:30 PM PDT 24 2828183230 ps
T226 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1347650080 Jul 06 07:32:56 PM PDT 24 Jul 06 07:44:16 PM PDT 24 4439816900 ps
T881 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3830810064 Jul 06 07:28:51 PM PDT 24 Jul 06 07:38:48 PM PDT 24 5715174084 ps
T882 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2869668949 Jul 06 07:58:22 PM PDT 24 Jul 06 08:07:20 PM PDT 24 3672477550 ps
T883 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2438542909 Jul 06 07:34:16 PM PDT 24 Jul 06 07:48:52 PM PDT 24 6143603440 ps
T319 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3437433903 Jul 06 07:56:44 PM PDT 24 Jul 06 08:06:07 PM PDT 24 4069631570 ps
T346 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2058331508 Jul 06 07:30:04 PM PDT 24 Jul 06 07:43:31 PM PDT 24 4438791157 ps
T120 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1871392732 Jul 06 07:49:46 PM PDT 24 Jul 06 08:03:30 PM PDT 24 5440002044 ps
T652 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1223651373 Jul 06 07:34:36 PM PDT 24 Jul 06 08:08:59 PM PDT 24 20339915239 ps
T324 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1357090303 Jul 06 07:29:47 PM PDT 24 Jul 06 07:42:38 PM PDT 24 5319228840 ps
T176 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2486262151 Jul 06 07:37:12 PM PDT 24 Jul 06 09:04:24 PM PDT 24 47795712490 ps
T340 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.136314317 Jul 06 07:45:17 PM PDT 24 Jul 06 07:56:07 PM PDT 24 4454646470 ps
T884 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3025728278 Jul 06 07:45:11 PM PDT 24 Jul 06 07:49:50 PM PDT 24 2463509412 ps
T665 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.258959211 Jul 06 07:46:35 PM PDT 24 Jul 06 07:51:14 PM PDT 24 3397372464 ps
T3 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.616821987 Jul 06 07:28:15 PM PDT 24 Jul 06 07:34:47 PM PDT 24 4636695280 ps
T420 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1944255002 Jul 06 07:29:59 PM PDT 24 Jul 06 07:35:47 PM PDT 24 3062067416 ps
T421 /workspace/coverage/default/2.chip_sw_aes_entropy.3945027347 Jul 06 07:49:39 PM PDT 24 Jul 06 07:53:07 PM PDT 24 2619300352 ps
T184 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3284339101 Jul 06 07:34:32 PM PDT 24 Jul 06 08:39:23 PM PDT 24 15160974432 ps
T422 /workspace/coverage/default/1.chip_sw_example_rom.1024365568 Jul 06 07:37:48 PM PDT 24 Jul 06 07:40:04 PM PDT 24 2091427700 ps
T260 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1736292851 Jul 06 07:28:41 PM PDT 24 Jul 06 07:39:30 PM PDT 24 7034413400 ps
T423 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3240512103 Jul 06 07:57:03 PM PDT 24 Jul 06 08:05:01 PM PDT 24 4634597567 ps
T155 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1089921820 Jul 06 07:31:48 PM PDT 24 Jul 06 08:38:27 PM PDT 24 19552306143 ps
T424 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.4179276618 Jul 06 07:31:14 PM PDT 24 Jul 06 07:37:22 PM PDT 24 3163878710 ps
T425 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2536683432 Jul 06 07:41:11 PM PDT 24 Jul 06 08:01:34 PM PDT 24 7074908973 ps
T236 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2514740994 Jul 06 07:34:14 PM PDT 24 Jul 06 07:57:05 PM PDT 24 9872530736 ps
T705 /workspace/coverage/default/81.chip_sw_all_escalation_resets.100386325 Jul 06 08:03:21 PM PDT 24 Jul 06 08:16:21 PM PDT 24 5730289784 ps
T279 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4207105073 Jul 06 07:28:08 PM PDT 24 Jul 06 07:30:13 PM PDT 24 2330352941 ps
T133 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.283693661 Jul 06 07:42:15 PM PDT 24 Jul 06 07:48:13 PM PDT 24 4729028856 ps
T885 /workspace/coverage/default/1.chip_sw_csrng_smoketest.2235539702 Jul 06 07:45:18 PM PDT 24 Jul 06 07:48:23 PM PDT 24 2347132376 ps
T886 /workspace/coverage/default/2.chip_sw_kmac_idle.273543326 Jul 06 07:49:50 PM PDT 24 Jul 06 07:53:34 PM PDT 24 2519911664 ps
T887 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1548043447 Jul 06 07:48:56 PM PDT 24 Jul 06 07:59:21 PM PDT 24 7580492440 ps
T760 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1860245743 Jul 06 08:05:12 PM PDT 24 Jul 06 08:11:01 PM PDT 24 3688553610 ps
T146 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2929410050 Jul 06 07:46:29 PM PDT 24 Jul 06 07:54:19 PM PDT 24 8313185212 ps
T666 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3199038654 Jul 06 07:28:04 PM PDT 24 Jul 06 07:32:45 PM PDT 24 3491378520 ps
T888 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.713512397 Jul 06 07:52:54 PM PDT 24 Jul 06 08:02:13 PM PDT 24 3756500224 ps
T241 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1664073434 Jul 06 07:47:21 PM PDT 24 Jul 06 08:14:31 PM PDT 24 8414332984 ps
T889 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2735402361 Jul 06 07:35:05 PM PDT 24 Jul 06 08:46:19 PM PDT 24 14669242811 ps
T281 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3627147378 Jul 06 07:32:12 PM PDT 24 Jul 06 07:45:21 PM PDT 24 5013744456 ps
T187 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.841263953 Jul 06 07:29:58 PM PDT 24 Jul 06 09:07:11 PM PDT 24 46590547360 ps
T283 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2001705430 Jul 06 07:50:24 PM PDT 24 Jul 06 07:57:14 PM PDT 24 3446944678 ps
T284 /workspace/coverage/default/2.chip_plic_all_irqs_0.3075734140 Jul 06 07:50:05 PM PDT 24 Jul 06 08:09:06 PM PDT 24 5836322294 ps
T285 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3856935680 Jul 06 08:04:40 PM PDT 24 Jul 06 08:11:19 PM PDT 24 3886935288 ps
T286 /workspace/coverage/default/2.chip_sw_hmac_smoketest.438457499 Jul 06 07:53:01 PM PDT 24 Jul 06 07:58:52 PM PDT 24 3490814752 ps
T287 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1932952596 Jul 06 08:04:55 PM PDT 24 Jul 06 08:10:21 PM PDT 24 3873016616 ps
T288 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.4172451222 Jul 06 07:28:23 PM PDT 24 Jul 06 07:35:49 PM PDT 24 3607410100 ps
T192 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1503791717 Jul 06 07:40:15 PM PDT 24 Jul 06 07:57:05 PM PDT 24 8119972303 ps
T32 /workspace/coverage/default/0.chip_sw_usbdev_stream.1955756093 Jul 06 07:29:49 PM PDT 24 Jul 06 08:52:48 PM PDT 24 18507232286 ps
T189 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1815432910 Jul 06 07:32:04 PM PDT 24 Jul 06 07:34:58 PM PDT 24 3515582803 ps
T122 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1484782045 Jul 06 07:34:01 PM PDT 24 Jul 06 07:44:04 PM PDT 24 3570826836 ps
T308 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.822855453 Jul 06 07:37:00 PM PDT 24 Jul 06 07:42:49 PM PDT 24 3111178241 ps
T309 /workspace/coverage/default/18.chip_sw_all_escalation_resets.3798203194 Jul 06 07:58:51 PM PDT 24 Jul 06 08:08:43 PM PDT 24 5520590248 ps
T310 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.4128954056 Jul 06 07:28:45 PM PDT 24 Jul 06 07:30:46 PM PDT 24 2664204462 ps
T311 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2920011996 Jul 06 08:02:30 PM PDT 24 Jul 06 08:08:07 PM PDT 24 3102710552 ps
T312 /workspace/coverage/default/0.chip_sw_example_rom.2175953392 Jul 06 07:28:31 PM PDT 24 Jul 06 07:30:31 PM PDT 24 2107327032 ps
T290 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.2341436433 Jul 06 07:55:23 PM PDT 24 Jul 06 08:12:07 PM PDT 24 6517826940 ps
T216 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2785067020 Jul 06 07:37:51 PM PDT 24 Jul 06 07:48:32 PM PDT 24 4259431766 ps
T390 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3391311415 Jul 06 07:38:47 PM PDT 24 Jul 06 09:44:40 PM PDT 24 24408021290 ps
T890 /workspace/coverage/default/2.chip_sw_power_sleep_load.2169503125 Jul 06 07:52:30 PM PDT 24 Jul 06 08:03:51 PM PDT 24 9592738648 ps
T891 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3175472223 Jul 06 07:29:59 PM PDT 24 Jul 06 07:37:53 PM PDT 24 5617899972 ps
T316 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3648280180 Jul 06 07:46:30 PM PDT 24 Jul 06 08:22:14 PM PDT 24 26889321658 ps
T892 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2567368781 Jul 06 07:38:25 PM PDT 24 Jul 06 07:59:10 PM PDT 24 12601467329 ps
T34 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.4277603172 Jul 06 07:32:26 PM PDT 24 Jul 06 08:40:43 PM PDT 24 20286218638 ps
T893 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.787553076 Jul 06 07:34:12 PM PDT 24 Jul 06 07:41:06 PM PDT 24 5022704256 ps
T452 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1586414403 Jul 06 07:48:34 PM PDT 24 Jul 06 08:13:21 PM PDT 24 6258994836 ps
T263 /workspace/coverage/default/0.chip_sw_plic_sw_irq.672773312 Jul 06 07:35:06 PM PDT 24 Jul 06 07:40:20 PM PDT 24 2595370180 ps
T647 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3068636401 Jul 06 07:52:36 PM PDT 24 Jul 06 09:04:27 PM PDT 24 24792474086 ps
T280 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2629521468 Jul 06 07:38:05 PM PDT 24 Jul 06 09:25:49 PM PDT 24 23379906842 ps
T709 /workspace/coverage/default/0.chip_sw_otbn_smoketest.2917333460 Jul 06 07:31:44 PM PDT 24 Jul 06 07:47:05 PM PDT 24 5248088560 ps
T791 /workspace/coverage/default/37.chip_sw_all_escalation_resets.1694231376 Jul 06 07:59:44 PM PDT 24 Jul 06 08:11:40 PM PDT 24 5294203888 ps
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