Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	149738	1			T75	854		T80	4		T161	78
values[2]	10514	1			T547	1		T599	6		T550	7
values[3]	4955	1			T547	1		T599	2		T545	3
values[4]	2707	1			T545	3		T548	34		T512	13
values[5]	1604	1			T548	22		T512	11		T796	1
values[6]	1194	1			T548	24		T512	14		T796	1
values[7]	826	1			T548	14		T512	5		T796	1
values[8]	714	1			T548	27		T512	6		T796	1
values[9]	646	1			T548	26		T512	13		T796	1
values[10]	640	1			T548	18		T512	10		T796	1
values[11]	581	1			T548	18		T512	14		T796	1
values[12]	590	1			T548	10		T512	9		T796	1
values[13]	638	1			T548	29		T512	13		T796	1
values[14]	627	1			T548	13		T512	3		T796	1
values[15]	575	1			T548	11		T512	27		T796	1
values[16]	559	1			T548	20		T512	6		T796	1
values[17]	582	1			T548	23		T512	4		T796	1
values[18]	492	1			T548	8		T512	7		T796	1
values[19]	510	1			T548	3		T512	6		T796	1
values[20]	632	1			T548	4		T512	16		T796	1
values[21]	555	1			T548	10		T512	10		T796	1
values[22]	488	1			T548	21		T512	14		T796	1
values[23]	516	1			T548	6		T512	15		T796	1
values[24]	552	1			T548	12		T512	4		T796	1
values[25]	503	1			T548	4		T512	4		T796	1
values[26]	460	1			T548	8		T512	6		T796	1
values[27]	409	1			T548	8		T512	4		T796	1
values[28]	406	1			T548	14		T512	10		T796	1
values[29]	458	1			T512	9		T796	1		T802	3
values[30]	419	1			T512	15		T796	1		T802	3
values[31]	504	1			T512	13		T796	1		T802	2
values[32]	417	1			T512	9		T796	1		T802	8
values[33]	467	1			T512	7		T796	1		T802	6
values[34]	411	1			T512	7		T796	1		T802	4
values[35]	397	1			T512	9		T796	1		T802	2
values[36]	436	1			T512	14		T796	1		T802	5
values[37]	439	1			T512	9		T796	1		T802	13
values[38]	430	1			T512	18		T796	1		T802	2
values[39]	351	1			T512	6		T796	2		T802	3
values[40]	360	1			T512	6		T796	1		T802	1
values[41]	304	1			T512	12		T796	1		T581	5
values[42]	355	1			T512	19		T796	1		T581	7
values[43]	278	1			T512	14		T796	1		T581	4
values[44]	282	1			T512	6		T796	1		T581	6
values[45]	228	1			T512	5		T796	1		T581	7
values[46]	296	1			T512	10		T796	1		T581	9
values[47]	272	1			T512	8		T796	1		T581	16
values[48]	299	1			T796	1		T581	40		T795	1
values[49]	195	1			T796	1		T581	2		T795	2
values[50]	183	1			T796	1		T795	1		T459	1
values[51]	166	1			T796	1		T795	1		T459	1
values[52]	135	1			T796	1		T795	1		T459	1
values[53]	115	1			T796	1		T795	1		T459	1
values[54]	104	1			T796	1		T795	1		T459	1
values[55]	100	1			T796	2		T795	1		T459	1
values[56]	98	1			T796	1		T795	1		T459	1
values[57]	98	1			T796	1		T795	1		T459	1
values[58]	67	1			T796	1		T795	1		T459	1
values[59]	79	1			T796	1		T795	1		T459	1
values[60]	79	1			T796	1		T795	1		T459	1
values[61]	72	1			T796	1		T795	1		T459	1
values[62]	64	1			T796	1		T795	1		T459	1
values[63]	68	1			T796	1		T795	1		T459	1
values[64]	88	1			T796	1		T795	1		T459	1
values[65]	88	1			T796	1		T795	1		T459	1
values[66]	84	1			T796	1		T795	1		T459	1
values[67]	77	1			T796	1		T795	1		T459	1
values[68]	78	1			T796	1		T795	1		T459	1
values[69]	86	1			T796	1		T795	1		T459	1
values[70]	80	1			T796	1		T795	1		T459	1
values[71]	92	1			T796	1		T795	1		T459	1
values[72]	81	1			T796	1		T795	1		T459	1
values[73]	96	1			T796	1		T795	1		T459	1
values[74]	96	1			T796	1		T795	1		T459	1
values[75]	60	1			T796	1		T795	1		T459	1
values[76]	67	1			T796	1		T795	1		T459	1
values[77]	121	1			T796	1		T795	1		T459	1
values[78]	100	1			T796	2		T795	1		T459	1
values[79]	88	1			T796	1		T795	1		T459	1
values[80]	87	1			T796	1		T795	1		T459	1
values[81]	86	1			T796	1		T795	1		T459	1
values[82]	82	1			T796	1		T795	1		T459	1
values[83]	99	1			T796	1		T795	1		T459	1
values[84]	85	1			T796	1		T795	2		T459	1
values[85]	81	1			T796	1		T795	1		T459	1
values[86]	96	1			T796	1		T795	1		T459	1
values[87]	84	1			T796	1		T795	1		T459	1
values[88]	103	1			T796	1		T795	1		T459	1
values[89]	92	1			T796	1		T795	1		T459	1
values[90]	81	1			T796	1		T795	1		T459	1
values[91]	90	1			T796	1		T795	1		T459	1
values[92]	88	1			T796	1		T795	1		T459	1
values[93]	78	1			T796	1		T795	1		T459	1
values[94]	59	1			T796	1		T795	1		T459	1
values[95]	73	1			T796	1		T795	1		T459	1
values[96]	84	1			T796	1		T795	1		T459	1
values[97]	64	1			T796	1		T795	1		T459	1
values[98]	66	1			T796	1		T795	1		T459	1
values[99]	81	1			T796	1		T795	1		T459	2
values[100]	75	1			T796	1		T795	1		T459	1
values[101]	64	1			T796	1		T795	1		T459	1
values[102]	60	1			T796	1		T795	1		T459	1
values[103]	71	1			T796	1		T795	1		T459	1
values[104]	64	1			T796	1		T795	1		T459	1
values[105]	70	1			T796	1		T795	1		T459	1
values[106]	52	1			T796	1		T795	1		T459	1
values[107]	56	1			T796	1		T795	1		T459	1
values[108]	57	1			T796	1		T795	2		T459	1
values[109]	55	1			T796	1		T795	1		T459	1
values[110]	57	1			T796	1		T795	1		T459	1
values[111]	56	1			T796	1		T795	1		T459	2
values[112]	45	1			T796	1		T795	1		T459	1
values[113]	34	1			T796	1		T795	1		T459	2
values[114]	39	1			T796	1		T795	2		T459	1
values[115]	32	1			T796	1		T795	2		T459	1
values[116]	32	1			T796	1		T795	4		T459	2
values[117]	45	1			T796	1		T795	1		T459	1
values[118]	42	1			T796	2		T795	1		T459	1
values[119]	44	1			T796	1		T795	2		T459	2
values[120]	39	1			T796	2		T795	2		T459	6
values[121]	42	1			T796	2		T795	4		T459	2
values[122]	38	1			T796	1		T795	3		T459	2
values[123]	42	1			T796	1		T795	1		T459	1
values[124]	42	1			T796	2		T795	1		T459	1
values[125]	41	1			T796	1		T795	2		T459	1
values[126]	93	1			T796	5		T795	4		T459	7
values[127]	1125	1			T796	42		T795	48		T459	89
values[128]	5320	1			T796	289		T795	258		T459	346