Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	472	1			T75	1		T634	1		T545	4
all_values[1]	472	1			T634	1		T546	1		T545	5
all_values[2]	483	1			T131	1		T634	2		T546	2
all_values[3]	515	1			T156	1		T634	2		T712	1
all_values[4]	513	1			T131	1		T546	1		T545	5
all_values[5]	487	1			T75	1		T634	1		T545	3
all_values[6]	470	1			T75	1		T545	8		T548	1
all_values[7]	480	1			T75	1		T545	8		T852	2
all_values[8]	458	1			T634	3		T545	2		T649	1
all_values[9]	480	1			T634	1		T546	1		T545	4
all_values[10]	485	1			T634	3		T545	2		T796	1
all_values[11]	510	1			T156	2		T545	1		T800	1
all_values[12]	463	1			T75	1		T131	1		T634	3
all_values[13]	485	1			T156	1		T634	4		T546	2
all_values[14]	464	1			T156	1		T634	2		T546	1
all_values[15]	484	1			T156	1		T634	3		T545	5
all_values[16]	461	1			T75	1		T156	1		T634	2
all_values[17]	481	1			T75	1		T76	1		T131	1
all_values[18]	483	1			T76	1		T156	1		T160	1
all_values[19]	468	1			T634	3		T545	4		T796	1
all_values[20]	456	1			T75	1		T131	1		T634	2
all_values[21]	458	1			T76	2		T131	1		T634	1
all_values[22]	504	1			T75	1		T131	1		T634	1
all_values[23]	513	1			T75	2		T156	1		T634	1
all_values[24]	494	1			T75	2		T634	2		T545	1
all_values[25]	509	1			T156	1		T634	3		T545	2
all_values[26]	480	1			T156	1		T634	2		T545	4
all_values[27]	485	1			T75	2		T131	1		T634	3
all_values[28]	447	1			T75	2		T76	1		T156	1
all_values[29]	480	1			T634	1		T546	1		T545	1
all_values[30]	446	1			T634	1		T545	3		T800	1
all_values[31]	471	1			T75	1		T156	1		T160	1
all_values[32]	492	1			T634	1		T545	4		T649	1
all_values[33]	503	1			T131	1		T634	2		T545	2
all_values[34]	444	1			T634	3		T545	5		T800	2
all_values[35]	494	1			T75	1		T156	1		T634	3
all_values[36]	498	1			T156	1		T634	1		T545	2
all_values[37]	482	1			T131	1		T634	2		T712	1
all_values[38]	518	1			T76	1		T634	4		T545	3
all_values[39]	467	1			T156	2		T131	1		T634	1
all_values[40]	451	1			T160	1		T634	1		T545	2
all_values[41]	488	1			T75	1		T156	1		T131	1
all_values[42]	514	1			T634	3		T546	1		T517	1
all_values[43]	485	1			T634	2		T545	3		T477	1
all_values[44]	476	1			T77	1		T634	2		T545	4
all_values[45]	498	1			T75	1		T160	1		T634	3
all_values[46]	496	1			T75	1		T634	3		T546	1
all_values[47]	533	1			T634	2		T545	3		T549	1
all_values[48]	450	1			T75	1		T156	1		T634	3
all_values[49]	490	1			T75	1		T131	1		T634	2