Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3607	1			T75	3		T634	7		T517	4
all_values[1]	3538	1			T75	3		T634	4		T517	2
all_values[2]	3573	1			T75	3		T634	4		T517	5
all_values[3]	3584	1			T75	3		T634	3		T517	5
all_values[4]	3530	1			T75	3		T634	3		T517	2
all_values[5]	3696	1			T75	2		T634	8		T517	2
all_values[6]	3539	1			T75	1		T634	5		T517	1
all_values[7]	3664	1			T75	5		T634	8		T545	13
all_values[8]	3644	1			T75	5		T634	13		T517	6
all_values[9]	3485	1			T75	4		T634	7		T517	3
all_values[10]	3608	1			T75	4		T634	4		T517	1
all_values[11]	3677	1			T75	5		T634	7		T517	4
all_values[12]	3573	1			T75	2		T634	8		T517	2
all_values[13]	3603	1			T75	2		T634	6		T517	2
all_values[14]	3633	1			T75	6		T634	4		T517	2
all_values[15]	3698	1			T75	8		T634	2		T517	4
all_values[16]	3643	1			T75	3		T634	10		T517	3
all_values[17]	3566	1			T75	4		T634	5		T517	1
all_values[18]	3676	1			T75	4		T634	3		T517	2
all_values[19]	3431	1			T75	4		T634	7		T517	4
all_values[20]	3608	1			T75	3		T634	7		T517	6
all_values[21]	3592	1			T75	3		T634	7		T517	2
all_values[22]	3617	1			T75	4		T634	5		T517	3
all_values[23]	3568	1			T75	4		T634	1		T517	3
all_values[24]	3502	1			T75	6		T634	7		T517	2
all_values[25]	3528	1			T75	5		T634	10		T517	4
all_values[26]	3626	1			T75	2		T634	7		T517	1
all_values[27]	3547	1			T75	2		T634	3		T517	3
all_values[28]	3581	1			T75	4		T634	5		T517	4
all_values[29]	3657	1			T634	7		T517	4		T545	14
all_values[30]	3583	1			T75	1		T634	3		T517	3
all_values[31]	3644	1			T75	1		T634	5		T517	4
all_values[32]	3615	1			T75	6		T634	4		T517	4
all_values[33]	3532	1			T75	1		T634	7		T517	3
all_values[34]	3689	1			T75	6		T634	5		T517	5
all_values[35]	3564	1			T75	5		T634	6		T517	1
all_values[36]	3605	1			T75	1		T634	4		T517	3
all_values[37]	3641	1			T75	3		T634	6		T517	3
all_values[38]	3640	1			T75	2		T634	2		T517	2
all_values[39]	3551	1			T75	5		T634	4		T545	14
all_values[40]	3564	1			T75	4		T634	3		T517	3
all_values[41]	3578	1			T75	5		T634	4		T517	2
all_values[42]	3548	1			T75	1		T634	4		T517	3
all_values[43]	3655	1			T75	2		T634	3		T517	1
all_values[44]	3566	1			T75	2		T634	5		T545	10
all_values[45]	3528	1			T75	3		T634	5		T517	3
all_values[46]	3601	1			T75	2		T634	2		T517	5
all_values[47]	3678	1			T75	3		T634	3		T517	4
all_values[48]	3475	1			T75	7		T634	7		T517	5
all_values[49]	3541	1			T75	4		T634	8		T517	5
all_values[50]	3653	1			T75	4		T634	6		T517	1
all_values[51]	3642	1			T75	1		T634	9		T517	5
all_values[52]	3660	1			T75	3		T634	3		T517	1
all_values[53]	3486	1			T75	1		T634	2		T517	3
all_values[54]	3604	1			T75	5		T634	5		T517	3
all_values[55]	3622	1			T75	2		T634	5		T517	2
all_values[56]	3529	1			T75	3		T634	4		T517	1
all_values[57]	3460	1			T75	4		T634	5		T517	2
all_values[58]	3527	1			T75	1		T634	9		T517	2
all_values[59]	3582	1			T75	4		T634	7		T517	5
all_values[60]	3616	1			T75	1		T634	5		T517	3
all_values[61]	3615	1			T75	5		T634	4		T517	6
all_values[62]	3499	1			T75	10		T634	4		T517	1
all_values[63]	3612	1			T75	4		T634	8		T517	3