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 LINE       36665
 EXPRESSION (addr_hit[559] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T130,T544,T472
1	1	1	Covered	T3,T8,T14

 LINE       36668
 EXPRESSION (addr_hit[560] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T130,T544,T467
1	1	1	Covered	T8,T150,T151

 LINE       36671
 EXPRESSION (addr_hit[561] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T130,T472,T566
1	1	1	Covered	T8,T16,T150

 LINE       36674
 EXPRESSION (addr_hit[562] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T130,T561,T521
1	1	1	Covered	T8,T477,T150

 LINE       36677
 EXPRESSION (addr_hit[563] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T130,T544,T526
1	1	1	Covered	T8,T13,T150

 LINE       36680
 EXPRESSION (addr_hit[564] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T130,T527,T561
1	1	1	Covered	T1,T2,T10

 LINE       36683
 EXPRESSION (addr_hit[565] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T130,T457,T469
1	1	1	Covered	T8,T150,T151

 LINE       36686
 EXPRESSION (addr_hit[566] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T130,T554,T467
1	1	1	Covered	T8,T150,T151

 LINE       36689
 EXPRESSION (addr_hit[567] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T130,T554,T470
1	1	1	Covered	T1,T2,T3

 LINE       40162
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3