Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3517117	1			T83	101		T84	4131		T85	961
values[2]	729330	1			T83	71		T84	901		T85	80
values[3]	106637	1			T84	118		T85	3		T87	19
values[4]	56619	1			T84	51		T87	19		T261	38
values[5]	37487	1			T84	14		T87	19		T261	31
values[6]	27666	1			T84	3		T87	19		T261	29
values[7]	22572	1			T84	1		T87	19		T261	25
values[8]	19511	1			T87	19		T261	18		T539	44
values[9]	17023	1			T87	19		T261	42		T539	73
values[10]	15277	1			T87	19		T261	35		T539	77
values[11]	14213	1			T87	19		T261	12		T539	51
values[12]	13487	1			T87	20		T261	32		T539	59
values[13]	12806	1			T87	20		T261	26		T539	86
values[14]	12238	1			T87	19		T261	25		T539	61
values[15]	11734	1			T87	19		T261	28		T539	60
values[16]	11096	1			T87	20		T261	20		T539	50
values[17]	10841	1			T87	19		T261	19		T539	36
values[18]	10452	1			T87	19		T261	32		T539	41
values[19]	9688	1			T87	19		T261	32		T539	32
values[20]	9624	1			T87	19		T261	41		T539	29
values[21]	9224	1			T87	19		T261	37		T539	27
values[22]	8945	1			T87	19		T261	25		T539	38
values[23]	9107	1			T87	19		T261	22		T539	73
values[24]	8699	1			T87	19		T261	19		T539	84
values[25]	8261	1			T87	19		T261	35		T539	50
values[26]	7748	1			T87	20		T261	41		T539	35
values[27]	7365	1			T87	20		T261	28		T539	42
values[28]	7505	1			T87	19		T261	21		T539	41
values[29]	6874	1			T87	19		T261	19		T539	31
values[30]	6313	1			T87	19		T261	35		T539	11
values[31]	5814	1			T87	19		T261	27		T539	17
values[32]	5538	1			T87	19		T261	21		T539	19
values[33]	5132	1			T87	19		T261	10		T539	7
values[34]	4672	1			T87	20		T261	16		T539	19
values[35]	4232	1			T87	19		T261	11		T539	20
values[36]	4067	1			T87	19		T261	5		T539	11
values[37]	4005	1			T87	19		T261	7		T539	7
values[38]	3777	1			T87	19		T261	3		T539	10
values[39]	3671	1			T87	19		T261	4		T539	9
values[40]	3526	1			T87	19		T261	10		T539	4
values[41]	3276	1			T87	19		T261	6		T539	2
values[42]	3382	1			T87	19		T261	7		T539	9
values[43]	3263	1			T87	19		T261	12		T539	4
values[44]	3262	1			T87	19		T261	6		T539	6
values[45]	3250	1			T87	19		T261	3		T539	7
values[46]	3165	1			T87	19		T261	11		T539	3
values[47]	3078	1			T87	19		T261	6		T539	5
values[48]	3136	1			T87	19		T261	3		T539	7
values[49]	2988	1			T87	22		T261	11		T539	8
values[50]	2945	1			T87	20		T261	10		T539	8
values[51]	2894	1			T87	19		T261	4		T539	7
values[52]	2844	1			T87	20		T261	7		T539	7
values[53]	2825	1			T87	20		T261	5		T539	5
values[54]	2758	1			T87	19		T261	7		T539	5
values[55]	2724	1			T87	19		T261	3		T539	4
values[56]	2692	1			T87	19		T261	2		T539	7
values[57]	2643	1			T87	19		T261	1		T539	2
values[58]	2631	1			T87	19		T261	4		T539	4
values[59]	2554	1			T87	19		T261	2		T539	4
values[60]	2536	1			T87	19		T261	1		T539	3
values[61]	2758	1			T87	19		T261	8		T539	5
values[62]	3996	1			T87	19		T261	1		T492	23
values[63]	11027	1			T87	21		T261	5		T492	88
values[64]	230784	1			T87	3417		T261	1		T492	529

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4558551	1			T83	88		T84	5326		T85	1077
values[2]	785764	1			T83	28		T84	837		T85	72
values[3]	84970	1			T83	1		T84	132		T85	4
values[4]	14779	1			T84	35		T87	94		T136	2
values[5]	5597	1			T84	44		T87	24		T543	16
values[6]	3370	1			T84	50		T87	9		T543	3
values[7]	2446	1			T84	38		T87	2		T505	1
values[8]	2099	1			T84	25		T87	2		T505	1
values[9]	1762	1			T84	18		T87	1		T505	1
values[10]	1592	1			T84	9		T87	1		T505	4
values[11]	1493	1			T84	4		T87	1		T505	1
values[12]	1386	1			T84	4		T87	1		T505	7
values[13]	1332	1			T84	2		T87	1		T505	3
values[14]	1162	1			T84	3		T87	1		T505	1
values[15]	1187	1			T84	2		T87	1		T505	2
values[16]	1130	1			T84	4		T87	1		T505	5
values[17]	1007	1			T84	6		T87	1		T505	1
values[18]	1014	1			T84	17		T87	1		T505	1
values[19]	985	1			T84	14		T87	1		T505	1
values[20]	867	1			T84	11		T87	1		T505	1
values[21]	804	1			T84	6		T87	1		T505	2
values[22]	822	1			T84	11		T87	1		T505	1
values[23]	771	1			T84	5		T87	1		T505	2
values[24]	723	1			T84	7		T87	1		T505	1
values[25]	742	1			T84	3		T87	1		T505	1
values[26]	712	1			T84	3		T87	1		T505	1
values[27]	651	1			T84	3		T87	1		T505	2
values[28]	586	1			T84	7		T87	1		T505	1
values[29]	586	1			T84	5		T87	1		T505	4
values[30]	580	1			T84	4		T87	1		T505	1
values[31]	534	1			T84	1		T87	1		T505	1
values[32]	542	1			T84	1		T87	1		T505	1
values[33]	560	1			T84	2		T87	1		T505	1
values[34]	547	1			T84	7		T87	1		T505	1
values[35]	492	1			T84	2		T87	1		T505	3
values[36]	452	1			T84	3		T87	1		T505	1
values[37]	439	1			T84	4		T87	1		T505	1
values[38]	415	1			T84	2		T87	1		T505	2
values[39]	444	1			T84	1		T87	1		T505	2
values[40]	440	1			T84	1		T87	1		T505	2
values[41]	444	1			T84	2		T87	1		T505	2
values[42]	461	1			T84	1		T87	1		T505	1
values[43]	490	1			T84	9		T87	1		T505	1
values[44]	454	1			T84	7		T87	1		T505	2
values[45]	440	1			T84	1		T87	1		T505	1
values[46]	445	1			T84	1		T87	1		T505	1
values[47]	409	1			T87	1		T505	2		T454	4
values[48]	416	1			T87	1		T505	2		T454	5
values[49]	397	1			T87	1		T505	7		T454	6
values[50]	391	1			T87	1		T505	5		T454	6
values[51]	424	1			T87	1		T505	2		T454	7
values[52]	404	1			T87	1		T505	1		T454	4
values[53]	400	1			T87	1		T505	1		T454	7
values[54]	371	1			T87	1		T505	2		T454	9
values[55]	351	1			T87	1		T505	2		T454	7
values[56]	340	1			T87	1		T505	3		T454	4
values[57]	356	1			T87	1		T505	1		T454	5
values[58]	346	1			T87	1		T505	2		T454	4
values[59]	331	1			T87	1		T505	5		T454	5
values[60]	337	1			T87	1		T505	2		T454	7
values[61]	373	1			T87	1		T505	3		T454	7
values[62]	577	1			T87	1		T505	6		T454	5
values[63]	2337	1			T87	1		T505	9		T454	11
values[64]	26599	1			T87	136		T505	84		T454	370

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	536342	1			T83	1		T84	751		T85	105
values[2]	2509532	1			T83	88		T84	3111		T85	762
values[3]	1139056	1			T83	44		T84	819		T85	103
values[4]	149419	1			T84	132		T87	19		T135	1
values[5]	75524	1			T84	68		T87	19		T261	65
values[6]	49041	1			T84	45		T87	19		T261	62
values[7]	34685	1			T84	12		T87	19		T261	40
values[8]	27630	1			T84	7		T87	19		T261	27
values[9]	22917	1			T84	9		T87	19		T261	25
values[10]	20208	1			T84	13		T87	19		T261	31
values[11]	18753	1			T84	5		T87	20		T261	34
values[12]	16949	1			T84	6		T87	19		T261	40
values[13]	15774	1			T84	7		T87	19		T261	44
values[14]	14989	1			T84	6		T87	19		T261	45
values[15]	14314	1			T84	5		T87	19		T261	19
values[16]	13488	1			T84	11		T87	19		T261	16
values[17]	13201	1			T84	9		T87	19		T261	33
values[18]	12727	1			T84	6		T87	20		T261	49
values[19]	12300	1			T84	4		T87	20		T261	30
values[20]	11417	1			T84	4		T87	19		T261	37
values[21]	10886	1			T84	8		T87	19		T261	28
values[22]	10413	1			T84	3		T87	20		T261	25
values[23]	10440	1			T84	6		T87	19		T261	44
values[24]	9876	1			T84	5		T87	19		T261	32
values[25]	9273	1			T84	6		T87	19		T261	29
values[26]	8901	1			T84	11		T87	19		T261	38
values[27]	8406	1			T84	4		T87	19		T261	25
values[28]	7690	1			T84	5		T87	19		T261	19
values[29]	7036	1			T84	4		T87	19		T261	15
values[30]	6567	1			T84	3		T87	19		T261	1
values[31]	6267	1			T84	5		T87	21		T261	7
values[32]	5959	1			T84	6		T87	19		T261	12
values[33]	5518	1			T84	5		T87	20		T261	3
values[34]	5046	1			T84	6		T87	20		T261	3
values[35]	4723	1			T84	7		T87	19		T261	2
values[36]	4516	1			T84	5		T87	19		T261	1
values[37]	4237	1			T84	5		T87	19		T539	7
values[38]	4045	1			T84	11		T87	19		T539	7
values[39]	3936	1			T84	7		T87	19		T539	9
values[40]	3819	1			T84	1		T87	19		T539	12
values[41]	3763	1			T84	1		T87	20		T539	4
values[42]	3648	1			T84	1		T87	19		T539	5
values[43]	3554	1			T84	9		T87	19		T539	5
values[44]	3460	1			T84	10		T87	19		T539	3
values[45]	3410	1			T84	7		T87	20		T539	1
values[46]	3410	1			T84	2		T87	19		T539	3
values[47]	3406	1			T84	1		T87	20		T539	1
values[48]	3330	1			T84	2		T87	19		T539	1
values[49]	3259	1			T84	1		T87	19		T539	2
values[50]	3232	1			T84	1		T87	19		T539	2
values[51]	3211	1			T84	4		T87	19		T539	3
values[52]	3070	1			T84	4		T87	19		T539	3
values[53]	3012	1			T84	8		T87	19		T539	1
values[54]	2966	1			T84	5		T87	19		T539	1
values[55]	2918	1			T84	3		T87	20		T539	2
values[56]	2800	1			T84	2		T87	19		T492	21
values[57]	2739	1			T84	1		T87	19		T492	25
values[58]	2704	1			T84	1		T87	19		T492	29
values[59]	2849	1			T84	5		T87	19		T492	18
values[60]	2693	1			T84	8		T87	19		T492	19
values[61]	2754	1			T84	10		T87	19		T492	26
values[62]	3772	1			T84	19		T87	20		T492	28
values[63]	9096	1			T84	43		T87	26		T492	81
values[64]	223449	1			T84	43		T87	3538		T492	214