Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2047123	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36814806

1

T4

17333

T5

79880

T6

5759

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27048559	1			T4	8323		T5	68602		T6	2239
values[0x0]	10351263	1			T4	9010		T5	11278		T6	3520
values[0x1]	1462107	1			T4	1494		T5	5		T6	319

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	714106	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38147823

1

T4

18827

T5

79885

T6

6078

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18133267	1			T4	9414		T5	39943		T6	3039
valid_sources[0x01]	18134083	1			T4	9413		T5	39942		T6	3039
valid_sources[0x02]	41875	1			T76	1		T9	6		T134	3
valid_sources[0x03]	41515	1			T58	1		T76	1		T134	1
valid_sources[0x04]	41637	1			T378	82		T379	3170		T739	1
valid_sources[0x05]	41277	1			T58	1		T76	1		T134	3
valid_sources[0x06]	41587	1			T86	1		T378	92		T379	3231
valid_sources[0x07]	42271	1			T76	1		T134	2		T378	83
valid_sources[0x08]	41892	1			T58	4		T76	2		T378	68
valid_sources[0x09]	42040	1			T58	1		T76	2		T86	3
valid_sources[0x0a]	41358	1			T134	1		T378	77		T379	3282
valid_sources[0x0b]	41476	1			T58	3		T86	2		T8	1
valid_sources[0x0c]	42196	1			T58	3		T86	4		T134	1
valid_sources[0x0d]	42380	1			T9	1		T134	3		T378	106
valid_sources[0x0e]	42214	1			T378	78		T379	3117		T739	3
valid_sources[0x0f]	41111	1			T86	1		T8	6		T134	1
valid_sources[0x10]	41716	1			T76	2		T134	1		T378	125
valid_sources[0x11]	41447	1			T76	1		T9	2		T378	95
valid_sources[0x12]	42141	1			T76	1		T86	2		T134	4
valid_sources[0x13]	42059	1			T134	3		T378	94		T379	3153
valid_sources[0x14]	41505	1			T86	1		T9	2		T134	1
valid_sources[0x15]	42081	1			T58	1		T134	1		T378	42
valid_sources[0x16]	41949	1			T76	2		T86	2		T134	2
valid_sources[0x17]	42673	1			T58	6		T378	48		T379	3245
valid_sources[0x18]	41653	1			T58	1		T76	2		T134	2
valid_sources[0x19]	42001	1			T86	1		T134	1		T378	64
valid_sources[0x1a]	41158	1			T58	2		T9	2		T378	74
valid_sources[0x1b]	42271	1			T58	2		T86	3		T134	4
valid_sources[0x1c]	40638	1			T58	2		T86	2		T134	1
valid_sources[0x1d]	42041	1			T86	1		T8	1		T9	1
valid_sources[0x1e]	41666	1			T58	1		T76	1		T9	3
valid_sources[0x1f]	44059	1			T76	4		T9	2		T134	3
valid_sources[0x20]	40949	1			T86	2		T9	1		T134	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26247159

1

T4

8323

T5

68602

T6

2239

values[0x0]

all_enables

biggest_size

10302357

1

T4

9010

T5

11278

T6

3520

values[0x1]

all_enables

biggest_size

265290

1

T58

21

T76

20

T86

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2809284	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

442902

1

T83

32

T84

11

T85

151

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1099417	1			T83	51		T84	105		T85	327
values[0x0]	1051601	1			T83	67		T84	14		T85	336
values[0x1]	1101168	1			T83	54		T84	102		T85	381

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2176033	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1076153

1

T83

67

T84

73

T85

350

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51265	1			T83	2		T84	3		T85	40
valid_sources[0x01]	50622	1			T83	5		T84	6		T85	10
valid_sources[0x02]	51071	1			T83	1		T84	2		T85	37
valid_sources[0x03]	51737	1			T84	2		T85	18		T87	66
valid_sources[0x04]	51584	1			T83	3		T84	5		T85	25
valid_sources[0x05]	51226	1			T84	4		T85	11		T87	76
valid_sources[0x06]	50967	1			T83	1		T84	4		T85	7
valid_sources[0x07]	51194	1			T84	1		T87	54		T136	9
valid_sources[0x08]	50573	1			T83	3		T84	5		T85	37
valid_sources[0x09]	50988	1			T83	5		T84	1		T87	76
valid_sources[0x0a]	51628	1			T83	5		T84	2		T85	32
valid_sources[0x0b]	49926	1			T83	4		T84	4		T87	79
valid_sources[0x0c]	50236	1			T83	1		T84	2		T87	75
valid_sources[0x0d]	50590	1			T83	3		T84	3		T85	31
valid_sources[0x0e]	49917	1			T83	3		T84	1		T85	30
valid_sources[0x0f]	50910	1			T83	4		T84	5		T85	42
valid_sources[0x10]	50611	1			T83	3		T84	4		T85	14
valid_sources[0x11]	51447	1			T83	6		T84	5		T85	6
valid_sources[0x12]	50428	1			T84	1		T87	75		T136	3
valid_sources[0x13]	51376	1			T83	1		T84	3		T87	67
valid_sources[0x14]	50122	1			T83	8		T84	1		T85	2
valid_sources[0x15]	50723	1			T83	2		T84	3		T85	36
valid_sources[0x16]	50870	1			T83	2		T84	1		T85	10
valid_sources[0x17]	52027	1			T83	1		T84	2		T85	21
valid_sources[0x18]	50565	1			T83	3		T84	1		T85	40
valid_sources[0x19]	49204	1			T83	2		T84	2		T85	26
valid_sources[0x1a]	50245	1			T83	3		T84	4		T87	81
valid_sources[0x1b]	50389	1			T83	1		T84	4		T85	16
valid_sources[0x1c]	51392	1			T83	3		T84	4		T85	35
valid_sources[0x1d]	49938	1			T84	2		T85	17		T87	71
valid_sources[0x1e]	50698	1			T83	3		T84	5		T85	27
valid_sources[0x1f]	49364	1			T83	1		T84	1		T85	7
valid_sources[0x20]	51901	1			T84	7		T85	4		T87	78

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46134

1

T83

2

T84

4

T85

20

values[0x0]

all_enables

biggest_size

350441

1

T83

27

T84

4

T85

120

values[0x1]

all_enables

biggest_size

46327

1

T83

3

T84

3

T85

11

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3006304	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

488782

1

T83

19

T84

45

T85

172

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1195972	1			T83	39		T84	130		T85	388
values[0x0]	1102128	1			T83	38		T84	28		T85	362
values[0x1]	1196986	1			T83	40		T84	169		T85	403

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2305752	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1189334

1

T83

37

T84

119

T85

425

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53819	1			T84	2		T87	70		T136	10
valid_sources[0x01]	53677	1			T84	2		T85	19		T87	85
valid_sources[0x02]	54434	1			T84	1		T85	31		T87	76
valid_sources[0x03]	54603	1			T84	4		T85	3		T87	85
valid_sources[0x04]	54914	1			T84	6		T87	39		T136	9
valid_sources[0x05]	55659	1			T84	4		T85	55		T87	50
valid_sources[0x06]	55245	1			T84	10		T85	45		T87	93
valid_sources[0x07]	54612	1			T85	11		T87	74		T136	7
valid_sources[0x08]	55082	1			T83	11		T84	3		T85	40
valid_sources[0x09]	55047	1			T83	13		T84	4		T85	67
valid_sources[0x0a]	54801	1			T84	7		T85	11		T87	47
valid_sources[0x0b]	55123	1			T84	3		T85	71		T87	68
valid_sources[0x0c]	55318	1			T83	13		T84	5		T85	10
valid_sources[0x0d]	55172	1			T84	7		T85	1		T87	35
valid_sources[0x0e]	53820	1			T84	6		T85	70		T87	85
valid_sources[0x0f]	54935	1			T83	3		T84	7		T85	11
valid_sources[0x10]	54593	1			T84	1		T85	1		T87	98
valid_sources[0x11]	55206	1			T83	13		T84	6		T85	13
valid_sources[0x12]	54250	1			T84	4		T87	92		T135	1
valid_sources[0x13]	54889	1			T84	8		T87	46		T136	13
valid_sources[0x14]	54412	1			T87	71		T136	12		T261	10
valid_sources[0x15]	54711	1			T84	8		T85	21		T87	52
valid_sources[0x16]	54526	1			T83	4		T84	6		T85	25
valid_sources[0x17]	55465	1			T83	1		T84	2		T85	8
valid_sources[0x18]	54946	1			T84	5		T85	81		T87	74
valid_sources[0x19]	54109	1			T84	6		T85	15		T87	67
valid_sources[0x1a]	54170	1			T84	5		T87	152		T136	13
valid_sources[0x1b]	54987	1			T84	8		T87	100		T136	7
valid_sources[0x1c]	54163	1			T84	5		T85	19		T87	100
valid_sources[0x1d]	54342	1			T83	1		T84	8		T85	39
valid_sources[0x1e]	54123	1			T84	6		T87	54		T136	9
valid_sources[0x1f]	54732	1			T83	4		T84	5		T85	19
valid_sources[0x20]	54348	1			T83	5		T84	4		T85	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51289

1

T83

2

T84

16

T85

16

values[0x0]

all_enables

biggest_size

386524

1

T83

16

T84

15

T85

138

values[0x1]

all_enables

biggest_size

50969

1

T83

1

T84

14

T85

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2830645	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

447927

1

T83

17

T84

19

T85

136

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1109587	1			T83	52		T84	109		T85	289
values[0x0]	1059222	1			T83	41		T84	18		T85	329
values[0x1]	1109763	1			T83	40		T84	104		T85	352

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2192289	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1086283

1

T83

43

T84

83

T85

301

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50916	1			T83	1		T84	2		T85	15
valid_sources[0x01]	50647	1			T84	5		T85	6		T87	73
valid_sources[0x02]	51545	1			T83	2		T84	5		T85	16
valid_sources[0x03]	51235	1			T83	11		T85	15		T87	68
valid_sources[0x04]	51301	1			T84	1		T85	9		T87	88
valid_sources[0x05]	50891	1			T84	4		T85	13		T87	65
valid_sources[0x06]	51695	1			T83	9		T84	3		T85	17
valid_sources[0x07]	51048	1			T83	16		T84	3		T85	11
valid_sources[0x08]	50614	1			T84	5		T85	9		T87	72
valid_sources[0x09]	51531	1			T83	4		T84	3		T85	9
valid_sources[0x0a]	52137	1			T84	7		T85	25		T87	69
valid_sources[0x0b]	51235	1			T84	5		T85	21		T87	72
valid_sources[0x0c]	51402	1			T84	4		T85	16		T87	88
valid_sources[0x0d]	50203	1			T83	2		T84	4		T85	14
valid_sources[0x0e]	50762	1			T83	4		T84	5		T85	11
valid_sources[0x0f]	50934	1			T83	4		T84	3		T85	12
valid_sources[0x10]	50878	1			T83	3		T84	3		T85	15
valid_sources[0x11]	51410	1			T83	3		T84	3		T85	14
valid_sources[0x12]	50440	1			T83	1		T84	7		T85	17
valid_sources[0x13]	51077	1			T83	2		T84	5		T85	12
valid_sources[0x14]	51577	1			T84	3		T85	19		T87	61
valid_sources[0x15]	51872	1			T84	6		T85	14		T87	71
valid_sources[0x16]	50957	1			T85	19		T87	74		T136	23
valid_sources[0x17]	52066	1			T85	18		T87	73		T136	2
valid_sources[0x18]	51695	1			T83	1		T84	5		T85	12
valid_sources[0x19]	50918	1			T83	1		T84	6		T85	11
valid_sources[0x1a]	50711	1			T84	4		T85	16		T87	74
valid_sources[0x1b]	50971	1			T84	3		T85	14		T87	73
valid_sources[0x1c]	51301	1			T84	4		T85	15		T87	65
valid_sources[0x1d]	50625	1			T84	2		T85	13		T87	72
valid_sources[0x1e]	50436	1			T84	2		T85	20		T87	72
valid_sources[0x1f]	50944	1			T83	5		T84	4		T85	17
valid_sources[0x20]	52207	1			T84	5		T85	12		T87	84

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47132

1

T83

3

T84

5

T85

4

values[0x0]

all_enables

biggest_size

354302

1

T83

13

T84

7

T85

118

values[0x1]

all_enables

biggest_size

46493

1

T83

1

T84

7

T85

14