Toggle Coverage for Module :
hmac
| Total | Covered | Percent |
Totals |
33 |
33 |
100.00 |
Total Bits |
316 |
316 |
100.00 |
Total Bits 0->1 |
158 |
158 |
100.00 |
Total Bits 1->0 |
158 |
158 |
100.00 |
| | | |
Ports |
33 |
33 |
100.00 |
Port Bits |
316 |
316 |
100.00 |
Port Bits 0->1 |
158 |
158 |
100.00 |
Port Bits 1->0 |
158 |
158 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T4,T5,T44 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T5,T44 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T5,T56,T18 |
Yes |
T5,T56,T18 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T5,T56,T18 |
Yes |
T5,T56,T18 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T5,T45,T56 |
Yes |
T5,T45,T56 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T5,T56,T18 |
Yes |
T5,T56,T18 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T5,T45,T56 |
Yes |
T5,T45,T56 |
INPUT |
tl_i.a_address[12:0] |
Yes |
Yes |
*T83,*T84,*T85 |
Yes |
T83,T84,T85 |
INPUT |
tl_i.a_address[15:13] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[16] |
Yes |
Yes |
*T5,*T45,*T56 |
Yes |
T5,T45,T56 |
INPUT |
tl_i.a_address[19:17] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[20] |
Yes |
Yes |
*T5,*T45,*T56 |
Yes |
T5,T45,T56 |
INPUT |
tl_i.a_address[23:21] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[24] |
Yes |
Yes |
*T5,*T45,*T56 |
Yes |
T5,T45,T56 |
INPUT |
tl_i.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T5,*T45,*T56 |
Yes |
T5,T45,T56 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T83,*T84,*T85 |
Yes |
T83,T84,T85 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T772,T773,T774 |
Yes |
T772,T773,T774 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T5,T45,T56 |
Yes |
T5,T45,T56 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T5,T45,T56 |
Yes |
T5,T45,T56 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T5,T56,T18 |
Yes |
T5,T56,T18 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T5,T56,T18 |
Yes |
T5,T56,T18 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T5,T56,T18 |
Yes |
T5,T56,T18 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T83,*T84,*T85 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T5,*T56,*T18 |
Yes |
T5,T56,T18 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T5,T56,T18 |
Yes |
T5,T56,T18 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T327,T308,T61 |
Yes |
T327,T308,T61 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T327,T328,T88 |
Yes |
T327,T328,T88 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T327,T328,T88 |
Yes |
T327,T328,T88 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T327,T308,T61 |
Yes |
T327,T308,T61 |
OUTPUT |
intr_hmac_done_o |
Yes |
Yes |
T330,T353,T310 |
Yes |
T330,T353,T310 |
OUTPUT |
intr_fifo_empty_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_hmac_err_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
idle_o[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T44 |
OUTPUT |
*Tests covering at least one bit in the range