Toggle Coverage for Module :
i2c
| Total | Covered | Percent |
Totals |
54 |
48 |
88.89 |
Total Bits |
352 |
328 |
93.18 |
Total Bits 0->1 |
176 |
164 |
93.18 |
Total Bits 1->0 |
176 |
164 |
93.18 |
| | | |
Ports |
54 |
48 |
88.89 |
Port Bits |
352 |
328 |
93.18 |
Port Bits 0->1 |
176 |
164 |
93.18 |
Port Bits 1->0 |
176 |
164 |
93.18 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T4,T5,T44 |
Yes |
T4,T5,T6 |
INPUT |
ram_cfg_i.rf_cfg.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.rf_cfg.cfg_en |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.rf_cfg.test |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.ram_cfg.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.ram_cfg.cfg_en |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.ram_cfg.test |
No |
No |
|
No |
|
INPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T330,T231,T227 |
Yes |
T330,T231,T227 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T330,T231,T227 |
Yes |
T330,T231,T227 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[6:0] |
Yes |
Yes |
*T83,*T84,*T85 |
Yes |
T83,T84,T85 |
INPUT |
tl_i.a_address[15:7] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[17:16] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[18] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[19] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[29:20] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T58,*T75,*T76 |
Yes |
T58,T75,T76 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T58,T76,T86 |
Yes |
T58,T76,T86 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T330,T231,T227 |
Yes |
T330,T231,T227 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T330,T231,T227 |
Yes |
T330,T231,T227 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T330,T231,T227 |
Yes |
T330,T231,T227 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T330,T231,T227 |
Yes |
T330,T231,T227 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T330,T231,T227 |
Yes |
T330,T231,T227 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
T83,*T84,*T85 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T330,*T231,*T227 |
Yes |
T330,T231,T227 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T330,T231,T227 |
Yes |
T330,T231,T227 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T358,T369,T61 |
Yes |
T358,T369,T61 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T88,T89,T90 |
Yes |
T88,T89,T90 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T88,T89,T90 |
Yes |
T88,T89,T90 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T358,T369,T61 |
Yes |
T358,T369,T61 |
OUTPUT |
cio_scl_i |
Yes |
Yes |
T231,T227,T228 |
Yes |
T231,T227,T228 |
INPUT |
cio_scl_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_scl_en_o |
Yes |
Yes |
T231,T227,T228 |
Yes |
T231,T227,T228 |
OUTPUT |
cio_sda_i |
Yes |
Yes |
T231,T227,T228 |
Yes |
T231,T227,T228 |
INPUT |
cio_sda_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_sda_en_o |
Yes |
Yes |
T231,T227,T228 |
Yes |
T231,T227,T228 |
OUTPUT |
intr_fmt_threshold_o |
Yes |
Yes |
T330,T231,T227 |
Yes |
T330,T231,T227 |
OUTPUT |
intr_rx_threshold_o |
Yes |
Yes |
T330,T231,T227 |
Yes |
T330,T231,T227 |
OUTPUT |
intr_acq_threshold_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_rx_overflow_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_controller_halt_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_scl_interference_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_sda_interference_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_stretch_timeout_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_sda_unstable_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_cmd_complete_o |
Yes |
Yes |
T330,T231,T227 |
Yes |
T330,T231,T227 |
OUTPUT |
intr_tx_stretch_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_tx_threshold_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_acq_stretch_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_unexp_stop_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_host_timeout_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0
| Total | Covered | Percent |
Totals |
54 |
48 |
88.89 |
Total Bits |
348 |
324 |
93.10 |
Total Bits 0->1 |
174 |
162 |
93.10 |
Total Bits 1->0 |
174 |
162 |
93.10 |
| | | |
Ports |
54 |
48 |
88.89 |
Port Bits |
348 |
324 |
93.10 |
Port Bits 0->1 |
174 |
162 |
93.10 |
Port Bits 1->0 |
174 |
162 |
93.10 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T4,T5,T44 |
Yes |
T4,T5,T6 |
INPUT |
ram_cfg_i.rf_cfg.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.rf_cfg.cfg_en |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.rf_cfg.test |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.ram_cfg.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.ram_cfg.cfg_en |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.ram_cfg.test |
No |
No |
|
No |
|
INPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T330,T227,T228 |
Yes |
T330,T227,T228 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T330,T227,T228 |
Yes |
T330,T227,T228 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[6:0] |
Yes |
Yes |
*T83,*T84,*T85 |
Yes |
T83,T84,T85 |
INPUT |
tl_i.a_address[18:7] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[19] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[29:20] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T58,*T75,*T76 |
Yes |
T58,T75,T76 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T58,T76,T86 |
Yes |
T58,T76,T86 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T330,T227,T228 |
Yes |
T330,T227,T228 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T330,T227,T228 |
Yes |
T330,T227,T228 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T330,T227,T228 |
Yes |
T330,T227,T228 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T330,T227,T228 |
Yes |
T330,T227,T228 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T330,T227,T228 |
Yes |
T330,T227,T228 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T84,*T85,*T135 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T330,*T227,*T228 |
Yes |
T330,T227,T228 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T330,T227,T228 |
Yes |
T330,T227,T228 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T61,T62,T171 |
Yes |
T61,T62,T171 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T88,T89,T90 |
Yes |
T88,T89,T90 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T88,T89,T90 |
Yes |
T88,T89,T90 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T61,T62,T171 |
Yes |
T61,T62,T171 |
OUTPUT |
cio_scl_i |
Yes |
Yes |
T227,T228,T355 |
Yes |
T227,T228,T355 |
INPUT |
cio_scl_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_scl_en_o |
Yes |
Yes |
T227,T228,T355 |
Yes |
T227,T228,T355 |
OUTPUT |
cio_sda_i |
Yes |
Yes |
T227,T228,T355 |
Yes |
T227,T228,T355 |
INPUT |
cio_sda_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_sda_en_o |
Yes |
Yes |
T227,T228,T355 |
Yes |
T227,T228,T355 |
OUTPUT |
intr_fmt_threshold_o |
Yes |
Yes |
T330,T227,T228 |
Yes |
T330,T227,T228 |
OUTPUT |
intr_rx_threshold_o |
Yes |
Yes |
T330,T227,T228 |
Yes |
T330,T227,T228 |
OUTPUT |
intr_acq_threshold_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_rx_overflow_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_controller_halt_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_scl_interference_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_sda_interference_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_stretch_timeout_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_sda_unstable_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_cmd_complete_o |
Yes |
Yes |
T330,T227,T228 |
Yes |
T330,T227,T228 |
OUTPUT |
intr_tx_stretch_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_tx_threshold_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_acq_stretch_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_unexp_stop_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_host_timeout_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1
| Total | Covered | Percent |
Totals |
54 |
48 |
88.89 |
Total Bits |
350 |
326 |
93.14 |
Total Bits 0->1 |
175 |
163 |
93.14 |
Total Bits 1->0 |
175 |
163 |
93.14 |
| | | |
Ports |
54 |
48 |
88.89 |
Port Bits |
350 |
326 |
93.14 |
Port Bits 0->1 |
175 |
163 |
93.14 |
Port Bits 1->0 |
175 |
163 |
93.14 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T4,T5,T44 |
Yes |
T4,T5,T6 |
INPUT |
ram_cfg_i.rf_cfg.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.rf_cfg.cfg_en |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.rf_cfg.test |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.ram_cfg.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.ram_cfg.cfg_en |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.ram_cfg.test |
No |
No |
|
No |
|
INPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T330,T230,T342 |
Yes |
T330,T230,T342 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T330,T230,T342 |
Yes |
T330,T230,T342 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[6:0] |
Yes |
Yes |
*T83,*T84,*T85 |
Yes |
T83,T84,T85 |
INPUT |
tl_i.a_address[15:7] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[16] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[18:17] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[19] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[29:20] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T58,*T75,*T76 |
Yes |
T58,T75,T76 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T58,T76,T86 |
Yes |
T58,T76,T86 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T330,T61,T230 |
Yes |
T330,T61,T230 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T330,T61,T230 |
Yes |
T330,T61,T230 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T330,T230,T342 |
Yes |
T330,T230,T342 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T330,T230,T342 |
Yes |
T330,T61,T230 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T330,T230,T342 |
Yes |
T330,T61,T230 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T84,*T85,*T135 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T84,T85,T135 |
Yes |
T84,T85,T135 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T330,*T230,*T342 |
Yes |
T330,T230,T342 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T330,T61,T230 |
Yes |
T330,T61,T230 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T358,T61,T62 |
Yes |
T358,T61,T62 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T88,T89,T90 |
Yes |
T88,T89,T90 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T88,T89,T90 |
Yes |
T88,T89,T90 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T358,T61,T62 |
Yes |
T358,T61,T62 |
OUTPUT |
cio_scl_i |
Yes |
Yes |
T230,T342,T390 |
Yes |
T230,T342,T390 |
INPUT |
cio_scl_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_scl_en_o |
Yes |
Yes |
T230,T342,T390 |
Yes |
T230,T342,T390 |
OUTPUT |
cio_sda_i |
Yes |
Yes |
T230,T342,T390 |
Yes |
T230,T342,T390 |
INPUT |
cio_sda_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_sda_en_o |
Yes |
Yes |
T230,T342,T390 |
Yes |
T230,T342,T390 |
OUTPUT |
intr_fmt_threshold_o |
Yes |
Yes |
T330,T230,T342 |
Yes |
T330,T230,T342 |
OUTPUT |
intr_rx_threshold_o |
Yes |
Yes |
T330,T230,T342 |
Yes |
T330,T230,T342 |
OUTPUT |
intr_acq_threshold_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_rx_overflow_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_controller_halt_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_scl_interference_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_sda_interference_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_stretch_timeout_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_sda_unstable_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_cmd_complete_o |
Yes |
Yes |
T330,T230,T342 |
Yes |
T330,T230,T342 |
OUTPUT |
intr_tx_stretch_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_tx_threshold_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_acq_stretch_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_unexp_stop_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_host_timeout_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2
| Total | Covered | Percent |
Totals |
54 |
48 |
88.89 |
Total Bits |
350 |
326 |
93.14 |
Total Bits 0->1 |
175 |
163 |
93.14 |
Total Bits 1->0 |
175 |
163 |
93.14 |
| | | |
Ports |
54 |
48 |
88.89 |
Port Bits |
350 |
326 |
93.14 |
Port Bits 0->1 |
175 |
163 |
93.14 |
Port Bits 1->0 |
175 |
163 |
93.14 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T4,T5,T44 |
Yes |
T4,T5,T6 |
INPUT |
ram_cfg_i.rf_cfg.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.rf_cfg.cfg_en |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.rf_cfg.test |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.ram_cfg.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.ram_cfg.cfg_en |
No |
No |
|
No |
|
INPUT |
ram_cfg_i.ram_cfg.test |
No |
No |
|
No |
|
INPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T330,T231,T391 |
Yes |
T330,T231,T391 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T330,T231,T391 |
Yes |
T330,T231,T391 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[6:0] |
Yes |
Yes |
*T83,*T84,*T85 |
Yes |
T83,T84,T85 |
INPUT |
tl_i.a_address[16:7] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[17] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[18] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[19] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[29:20] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T58,*T75,*T76 |
Yes |
T58,T75,T76 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T58,T76,T86 |
Yes |
T58,T76,T86 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T330,T231,T61 |
Yes |
T330,T231,T61 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T330,T231,T61 |
Yes |
T330,T231,T61 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T330,T231,T335 |
Yes |
T330,T231,T335 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T330,T231,T391 |
Yes |
T330,T231,T61 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T330,T231,T391 |
Yes |
T330,T231,T61 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T83,*T84,*T85 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T330,*T231,*T391 |
Yes |
T330,T231,T391 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T330,T231,T61 |
Yes |
T330,T231,T61 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T369,T61,T62 |
Yes |
T369,T61,T62 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T88,T89,T90 |
Yes |
T88,T89,T90 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T88,T89,T90 |
Yes |
T88,T89,T90 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T369,T61,T62 |
Yes |
T369,T61,T62 |
OUTPUT |
cio_scl_i |
Yes |
Yes |
T231,T9,T356 |
Yes |
T231,T9,T356 |
INPUT |
cio_scl_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_scl_en_o |
Yes |
Yes |
T231,T356,T392 |
Yes |
T231,T356,T392 |
OUTPUT |
cio_sda_i |
Yes |
Yes |
T231,T356,T346 |
Yes |
T231,T356,T346 |
INPUT |
cio_sda_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_sda_en_o |
Yes |
Yes |
T231,T356,T346 |
Yes |
T231,T356,T346 |
OUTPUT |
intr_fmt_threshold_o |
Yes |
Yes |
T330,T231,T335 |
Yes |
T330,T231,T335 |
OUTPUT |
intr_rx_threshold_o |
Yes |
Yes |
T330,T231,T335 |
Yes |
T330,T231,T335 |
OUTPUT |
intr_acq_threshold_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_rx_overflow_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_controller_halt_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_scl_interference_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_sda_interference_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_stretch_timeout_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_sda_unstable_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_cmd_complete_o |
Yes |
Yes |
T330,T231,T335 |
Yes |
T330,T231,T335 |
OUTPUT |
intr_tx_stretch_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_tx_threshold_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_acq_stretch_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_unexp_stop_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
intr_host_timeout_o |
Yes |
Yes |
T330,T335,T333 |
Yes |
T330,T335,T333 |
OUTPUT |
*Tests covering at least one bit in the range