Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio31
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio31
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T25,T26,T330 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio31
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T25,T26,T330 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T25,T26,T330 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio32
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio32
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T25,T26,T330 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio32
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T25,T26,T330 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T25,T26,T330 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio33
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio33
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T25,T26,T330 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio33
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T25,T26,T330 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T25,T26,T330 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio34
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio34
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T25,T26,T330 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio34
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T25,T26,T330 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T25,T26,T330 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio35
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio35
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T25,T26,T330 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio35
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T25,T26,T330 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T25,T26,T330 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio36
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio36
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T25,T26,T330 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio36
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T25,T26,T330 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T25,T26,T330 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio37
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio37
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio37
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio38
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio38
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio38
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio39
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio39
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio39
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio40
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio40
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio40
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio41
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio41
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio41
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio42
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio42
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio42
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio43
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio43
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio43
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio44
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio44
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio44
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio45
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio45
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio45
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio46
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio46
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio46
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio47
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio47
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio47
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio48
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio48
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio48
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio49
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio49
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio49
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio50
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio50
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio50
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio51
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio51
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio51
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio52
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio52
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio52
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio53
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio53
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio53
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio54
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio54
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio54
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio55
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio55
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio55
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio56
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio56
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio56
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio57
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio57
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio57
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio58
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio58
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio58
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio59
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio59
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio59
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio60
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio60
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio60
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio61
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio61
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio61
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio62
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio62
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T330,T262,T263 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio62
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T330,T262,T263 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T330,T262,T263 |
0 |
0 |
Covered |
T4,T5,T6 |