Unified Coverage Report :: Module :: prim_filter

Module : prim_filter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter	71.33	72.73	55.56			85.71
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter	71.33	72.73	55.56			85.71
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter	91.53	100.00	88.89			85.71
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter	91.53	100.00	88.89			85.71
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter	91.53	100.00	88.89			85.71
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity	100.00	100.00	100.00			100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset	100.00	100.00	100.00			100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense	100.00	100.00	100.00			100.00
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter	100.00	100.00	100.00			100.00
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter	100.00	100.00	100.00			100.00
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.33	72.73	55.56			85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.27	82.35	55.56			90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
45.52	52.63	38.46			45.45		gen_wkup_detect[1].u_pinmux_wkup

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.33	72.73	55.56			85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.27	82.35	55.56			90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
45.52	52.63	38.46			45.45		gen_wkup_detect[2].u_pinmux_wkup

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.53	100.00	88.89			85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.27	100.00	88.89			90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
64.07	68.42	69.23			54.55		gen_wkup_detect[0].u_pinmux_wkup

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.53	100.00	88.89			85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.27	100.00	88.89			90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
64.07	68.42	69.23			54.55		gen_wkup_detect[4].u_pinmux_wkup

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.53	100.00	88.89			85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.27	100.00	88.89			90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
59.28	63.16	69.23			45.45		gen_wkup_detect[7].u_pinmux_wkup

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.98	100.00	93.18			94.74	100.00	u_usbdev_aon_wake

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.98	100.00	93.18			94.74	100.00	u_usbdev_aon_wake

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.98	100.00	93.18			94.74	100.00	u_usbdev_aon_wake

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
45.05	52.63	46.15			36.36		gen_wkup_detect[3].u_pinmux_wkup

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
64.07	68.42	69.23			54.55		gen_wkup_detect[5].u_pinmux_wkup

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
59.28	63.16	69.23			45.45		gen_wkup_detect[6].u_pinmux_wkup

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_async.prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
			MISSING_ELSE
55	1	1
56	1	1
59	1	1
60	1	1
62	1	1
66	1	1
70	1	1

---

Cond Coverage for Module : prim_filter

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

Branch Coverage for Module : prim_filter

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	70	2	2	100.00
IF	48	3	3	100.00
IF	59	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	70	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	48	if ((!rst_ni))
-2-:	50	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	59	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	8	72.73
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
			==> MISSING_ELSE
55	0	1
56	0	1
59	1	1
60	1	1
62	1	1
66	0	1
70	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	70	2	2	100.00
IF	48	3	2	66.67
IF	59	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	70	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	48	if ((!rst_ni))
-2-:	50	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

	LineNo.	Expression
-1-:	59	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	8	72.73
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
			==> MISSING_ELSE
55	0	1
56	0	1
59	1	1
60	1	1
62	1	1
66	0	1
70	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	70	2	2	100.00
IF	48	3	2	66.67
IF	59	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	70	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	48	if ((!rst_ni))
-2-:	50	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

	LineNo.	Expression
-1-:	59	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
			MISSING_ELSE
55	1	1
56	1	1
59	1	1
60	1	1
62	1	1
66	1	1
70	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T12
0	1	Covered	T8,T11,T12
1	0	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T8,T11,T12
1	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T12

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	70	2	1	50.00
IF	48	3	3	100.00
IF	59	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	70	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	48	if ((!rst_ni))
-2-:	50	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T8,T11,T12

	LineNo.	Expression
-1-:	59	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
			MISSING_ELSE
55	1	1
56	1	1
59	1	1
60	1	1
62	1	1
66	1	1
70	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T14
0	1	Covered	T1,T8,T14
1	0	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T8,T14
1	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T14

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	70	2	1	50.00
IF	48	3	3	100.00
IF	59	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	70	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	48	if ((!rst_ni))
-2-:	50	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T8,T14

	LineNo.	Expression
-1-:	59	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
			MISSING_ELSE
55	1	1
56	1	1
59	1	1
60	1	1
62	1	1
66	1	1
70	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9
0	1	Covered	T9
1	0	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T9
1	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	70	2	1	50.00
IF	48	3	3	100.00
IF	59	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	70	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	48	if ((!rst_ni))
-2-:	50	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T9

	LineNo.	Expression
-1-:	59	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
			MISSING_ELSE
55	1	1
56	1	1
59	1	1
60	1	1
62	1	1
66	1	1
70	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	70	1	1	100.00
IF	48	3	3	100.00
IF	59	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	70	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Unreachable

	LineNo.	Expression
-1-:	48	if ((!rst_ni))
-2-:	50	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	59	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
			MISSING_ELSE
55	1	1
56	1	1
59	1	1
60	1	1
62	1	1
66	1	1
70	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T29,T30
0	1	Covered	T2,T29,T30
1	0	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T2,T29,T30
1	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T29,T30

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	70	1	1	100.00
IF	48	3	3	100.00
IF	59	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	70	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Unreachable

	LineNo.	Expression
-1-:	48	if ((!rst_ni))
-2-:	50	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T2,T29,T30

	LineNo.	Expression
-1-:	59	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
			MISSING_ELSE
55	1	1
56	1	1
59	1	1
60	1	1
62	1	1
66	1	1
70	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	70	1	1	100.00
IF	48	3	3	100.00
IF	59	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	70	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Unreachable

	LineNo.	Expression
-1-:	48	if ((!rst_ni))
-2-:	50	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	59	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
			MISSING_ELSE
55	1	1
56	1	1
59	1	1
60	1	1
62	1	1
66	1	1
70	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8
0	1	Covered	T8
1	0	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T8
1	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	70	2	2	100.00
IF	48	3	3	100.00
IF	59	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	70	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	48	if ((!rst_ni))
-2-:	50	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T8

	LineNo.	Expression
-1-:	59	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
			MISSING_ELSE
55	1	1
56	1	1
59	1	1
60	1	1
62	1	1
66	1	1
70	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	70	2	2	100.00
IF	48	3	3	100.00
IF	59	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	70	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	48	if ((!rst_ni))
-2-:	50	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	59	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	48	4	4	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	3	3	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
			MISSING_ELSE
55	1	1
56	1	1
59	1	1
60	1	1
62	1	1
66	1	1
70	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9
0	1	Covered	T8,T9
1	0	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T8,T9
1	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	70	2	2	100.00
IF	48	3	3	100.00
IF	59	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	70	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	48	if ((!rst_ni))
-2-:	50	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T8,T9

	LineNo.	Expression
-1-:	59	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6