Toggle Coverage for Module :
adc_ctrl
| Total | Covered | Percent |
Totals |
37 |
37 |
100.00 |
Total Bits |
324 |
324 |
100.00 |
Total Bits 0->1 |
162 |
162 |
100.00 |
Total Bits 1->0 |
162 |
162 |
100.00 |
| | | |
Ports |
37 |
37 |
100.00 |
Port Bits |
324 |
324 |
100.00 |
Port Bits 0->1 |
162 |
162 |
100.00 |
Port Bits 1->0 |
162 |
162 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
clk_aon_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T4,T5,T44 |
Yes |
T4,T5,T6 |
INPUT |
rst_aon_ni |
Yes |
Yes |
T4,T5,T44 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T115,T330,T3 |
Yes |
T115,T330,T3 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T115,T330,T3 |
Yes |
T115,T330,T3 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[6:0] |
Yes |
Yes |
*T83,*T84,*T85 |
Yes |
T83,T84,T85 |
INPUT |
tl_i.a_address[17:7] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[18] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[21:19] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[22] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[29:23] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T58,*T75,*T76 |
Yes |
T58,T75,T76 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T83,T84,T85 |
Yes |
T83,T84,T85 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T58,T76,T86 |
Yes |
T58,T76,T86 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T115,T330,T3 |
Yes |
T115,T330,T3 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T115,T330,T3 |
Yes |
T115,T330,T3 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T84,T85,T135 |
Yes |
T84,T85,T135 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T330,T3,T7 |
Yes |
T330,T3,T7 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T115,T330,T3 |
Yes |
T115,T330,T3 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T115,T3,T7 |
Yes |
T115,T330,T3 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T84,T85,T135 |
Yes |
T84,T85,T135 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T84,*T85,*T135 |
Yes |
T83,T84,T85 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T84,T85,T135 |
Yes |
T84,T85,T135 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T115,*T330,*T3 |
Yes |
T115,T330,T3 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T115,T330,T3 |
Yes |
T115,T330,T3 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T324,T61,T62 |
Yes |
T324,T61,T62 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T88,T89,T90 |
Yes |
T88,T89,T90 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T88,T89,T90 |
Yes |
T88,T89,T90 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T324,T61,T62 |
Yes |
T324,T61,T62 |
OUTPUT |
adc_o.pd |
Yes |
Yes |
T115,T3,T7 |
Yes |
T115,T3,T7 |
OUTPUT |
adc_o.channel_sel[1:0] |
Yes |
Yes |
T115,T3,T7 |
Yes |
T115,T3,T7 |
OUTPUT |
adc_i.data_valid |
Yes |
Yes |
T115,T3,T7 |
Yes |
T115,T3,T7 |
INPUT |
adc_i.data[9:0] |
Yes |
Yes |
T3,T7,T116 |
Yes |
T3,T7,T116 |
INPUT |
intr_match_pending_o |
Yes |
Yes |
T330,T116,T361 |
Yes |
T330,T116,T361 |
OUTPUT |
wkup_req_o |
Yes |
Yes |
T3,T7,T64 |
Yes |
T3,T7,T116 |
OUTPUT |
*Tests covering at least one bit in the range