Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	516738293	59988914	0	0
DepthKnown_A	516738293	516631474	0	0
RvalidKnown_A	516738293	516631474	0	0
WreadyKnown_A	516738293	516631474	0	0
gen_passthru_fifo.paramCheckPass	1017	1017	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	59988914	0	0
T4	278828	36659	0	0
T5	862854	105510	0	0
T6	204222	26710	0	0
T15	213648	21481	0	0
T16	152738	19342	0	0
T44	199003	17580	0	0
T45	217490	19383	0	0
T92	69384	6906	0	0
T93	90956	10940	0	0
T94	89313	10096	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	516631474	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	516631474	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	516631474	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	516738293	46197848	0	0
DepthKnown_A	516738293	516631474	0	0
RvalidKnown_A	516738293	516631474	0	0
WreadyKnown_A	516738293	516631474	0	0
gen_passthru_fifo.paramCheckPass	1017	1017	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	46197848	0	0
T4	278828	27020	0	0
T5	862854	88048	0	0
T6	204222	23982	0	0
T15	213648	17575	0	0
T16	152738	15269	0	0
T44	199003	13818	0	0
T45	217490	15120	0	0
T92	69384	5174	0	0
T93	90956	8389	0	0
T94	89313	7722	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	516631474	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	516631474	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	516631474	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	516738293	43060460	0	0
DepthKnown_A	516738293	516631474	0	0
RvalidKnown_A	516738293	516631474	0	0
WreadyKnown_A	516738293	516631474	0	0
gen_passthru_fifo.paramCheckPass	1017	1017	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	43060460	0	0
T4	278828	19204	0	0
T5	862854	130432	0	0
T6	204222	6287	0	0
T15	213648	20290	0	0
T16	152738	13260	0	0
T44	199003	10592	0	0
T45	217490	11047	0	0
T92	69384	4112	0	0
T93	90956	5804	0	0
T94	89313	5083	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	516631474	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	516631474	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	516631474	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	516738293	36305460	0	0
DepthKnown_A	516738293	516631474	0	0
RvalidKnown_A	516738293	516631474	0	0
WreadyKnown_A	516738293	516631474	0	0
gen_passthru_fifo.paramCheckPass	1017	1017	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	36305460	0	0
T4	278828	18827	0	0
T5	862854	79885	0	0
T6	204222	6078	0	0
T15	213648	20084	0	0
T16	152738	13044	0	0
T44	199003	10347	0	0
T45	217490	10802	0	0
T92	69384	3993	0	0
T93	90956	5674	0	0
T94	89313	4937	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	516631474	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	516631474	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	516631474	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	607275639	97675	0	0
DepthKnown_A	607275639	607156573	0	0
RvalidKnown_A	607275639	607156573	0	0
WreadyKnown_A	607275639	607156573	0	0
gen_passthru_fifo.paramCheckPass	2908	2908	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	97675	0	0
T4	278828	151	0	0
T5	862854	27	0	0
T6	204222	78	0	0
T15	213648	53	0	0
T16	152738	56	0	0
T44	199003	30	0	0
T45	217490	30	0	0
T92	69384	15	0	0
T93	90956	13	0	0
T94	89313	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2908	2908	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	607275639	100588	0	0
DepthKnown_A	607275639	607156573	0	0
RvalidKnown_A	607275639	607156573	0	0
WreadyKnown_A	607275639	607156573	0	0
gen_passthru_fifo.paramCheckPass	2908	2908	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	100588	0	0
T4	278828	151	0	0
T5	862854	27	0	0
T6	204222	78	0	0
T15	213648	53	0	0
T16	152738	56	0	0
T44	199003	30	0	0
T45	217490	30	0	0
T92	69384	15	0	0
T93	90956	13	0	0
T94	89313	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2908	2908	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	607275639	51511	0	0
DepthKnown_A	607275639	607156573	0	0
RvalidKnown_A	607275639	607156573	0	0
WreadyKnown_A	607275639	607156573	0	0
gen_passthru_fifo.paramCheckPass	2908	2908	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	51511	0	0
T4	278828	95	0	0
T5	862854	0	0	0
T6	204222	77	0	0
T15	213648	52	0	0
T16	152738	55	0	0
T44	199003	28	0	0
T45	217490	28	0	0
T60	0	8	0	0
T92	69384	14	0	0
T93	90956	12	0	0
T94	89313	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2908	2908	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	607275639	51511	0	0
DepthKnown_A	607275639	607156573	0	0
RvalidKnown_A	607275639	607156573	0	0
WreadyKnown_A	607275639	607156573	0	0
gen_passthru_fifo.paramCheckPass	2908	2908	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	51511	0	0
T4	278828	95	0	0
T5	862854	0	0	0
T6	204222	77	0	0
T15	213648	52	0	0
T16	152738	55	0	0
T44	199003	28	0	0
T45	217490	28	0	0
T60	0	8	0	0
T92	69384	14	0	0
T93	90956	12	0	0
T94	89313	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2908	2908	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	607275639	46164	0	0
DepthKnown_A	607275639	607156573	0	0
RvalidKnown_A	607275639	607156573	0	0
WreadyKnown_A	607275639	607156573	0	0
gen_passthru_fifo.paramCheckPass	2908	2908	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	46164	0	0
T4	278828	56	0	0
T5	862854	27	0	0
T6	204222	1	0	0
T15	213648	1	0	0
T16	152738	1	0	0
T44	199003	2	0	0
T45	217490	2	0	0
T92	69384	1	0	0
T93	90956	1	0	0
T94	89313	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2908	2908	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	607275639	49077	0	0
DepthKnown_A	607275639	607156573	0	0
RvalidKnown_A	607275639	607156573	0	0
WreadyKnown_A	607275639	607156573	0	0
gen_passthru_fifo.paramCheckPass	2908	2908	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	49077	0	0
T4	278828	56	0	0
T5	862854	27	0	0
T6	204222	1	0	0
T15	213648	1	0	0
T16	152738	1	0	0
T44	199003	2	0	0
T45	217490	2	0	0
T92	69384	1	0	0
T93	90956	1	0	0
T94	89313	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607275639	607156573	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2908	2908	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0