Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_recov_alert_val_8.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_recov_alert_val_8.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T140,T141,T152 |
1 | 0 | Covered | T154,T137,T7 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T140,T141,T152 |
1 | 1 | Covered | T140,T141,T152 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T140,T141,T152 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T154,T137,T7 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_recov_alert_val_9.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_recov_alert_val_9.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T140,T141,T150 |
1 | 0 | Covered | T154,T137,T7 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T140,T141,T150 |
1 | 1 | Covered | T140,T141,T150 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T140,T141,T150 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T154,T137,T7 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_recov_alert_val_10.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_recov_alert_val_10.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T140,T141,T150 |
1 | 0 | Covered | T154,T137,T7 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T140,T141,T150 |
1 | 1 | Covered | T140,T141,T150 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T140,T141,T150 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T154,T137,T7 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
43 |
1 |
1 |
44 |
0 |
1 |
51 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
43 |
1 |
1 |
44 |
0 |
1 |
51 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_2.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
43 |
1 |
1 |
44 |
0 |
1 |
51 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_3.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
43 |
1 |
1 |
44 |
0 |
1 |
51 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_4.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
43 |
1 |
1 |
44 |
0 |
1 |
51 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_5.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 0 | 0.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
43 |
0 |
1 |
44 |
0 |
1 |
51 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_6.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 0 | 0.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
43 |
0 |
1 |
44 |
0 |
1 |
51 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_7.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 0 | 0.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
43 |
0 |
1 |
44 |
0 |
1 |
51 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_8.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 0 | 0.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
43 |
0 |
1 |
44 |
0 |
1 |
51 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_fatal_alert_val_9.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 0 | 0.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
43 |
0 |
1 |
44 |
0 |
1 |
51 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |