Line Coverage for Module :
pinmux_strap_sampling
| Line No. | Total | Covered | Percent |
TOTAL | | 303 | 301 | 99.34 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 230 | 1 | 1 | 100.00 |
CONT_ASSIGN | 232 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 241 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
ALWAYS | 262 | 9 | 9 | 100.00 |
ALWAYS | 283 | 9 | 9 | 100.00 |
CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
ALWAYS | 312 | 17 | 17 | 100.00 |
CONT_ASSIGN | 371 | 1 | 1 | 100.00 |
CONT_ASSIGN | 372 | 1 | 1 | 100.00 |
CONT_ASSIGN | 373 | 1 | 1 | 100.00 |
CONT_ASSIGN | 396 | 1 | 1 | 100.00 |
CONT_ASSIGN | 396 | 1 | 1 | 100.00 |
CONT_ASSIGN | 396 | 1 | 1 | 100.00 |
CONT_ASSIGN | 396 | 1 | 1 | 100.00 |
CONT_ASSIGN | 396 | 1 | 1 | 100.00 |
CONT_ASSIGN | 400 | 1 | 1 | 100.00 |
CONT_ASSIGN | 401 | 1 | 1 | 100.00 |
CONT_ASSIGN | 404 | 1 | 1 | 100.00 |
CONT_ASSIGN | 404 | 1 | 1 | 100.00 |
CONT_ASSIGN | 404 | 1 | 1 | 100.00 |
CONT_ASSIGN | 404 | 1 | 1 | 100.00 |
CONT_ASSIGN | 405 | 1 | 1 | 100.00 |
CONT_ASSIGN | 405 | 1 | 1 | 100.00 |
CONT_ASSIGN | 405 | 1 | 1 | 100.00 |
CONT_ASSIGN | 405 | 1 | 1 | 100.00 |
CONT_ASSIGN | 412 | 1 | 1 | 100.00 |
CONT_ASSIGN | 412 | 1 | 1 | 100.00 |
CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 0 | 0.00 |
CONT_ASSIGN | 419 | 1 | 0 | 0.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
132 |
1 |
1 |
133 |
1 |
1 |
153 |
1 |
1 |
157 |
1 |
1 |
187 |
1 |
1 |
230 |
1 |
1 |
232 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
259 |
1 |
1 |
262 |
1 |
1 |
263 |
1 |
1 |
264 |
1 |
1 |
268 |
1 |
1 |
269 |
1 |
1 |
|
|
|
MISSING_ELSE |
274 |
1 |
1 |
275 |
1 |
1 |
276 |
1 |
1 |
277 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
283 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
286 |
1 |
1 |
287 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
291 |
1 |
1 |
292 |
1 |
1 |
308 |
1 |
1 |
312 |
1 |
1 |
315 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
319 |
1 |
1 |
321 |
1 |
1 |
323 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
328 |
1 |
1 |
329 |
1 |
1 |
330 |
1 |
1 |
331 |
1 |
1 |
|
|
|
MISSING_ELSE |
335 |
1 |
1 |
336 |
1 |
1 |
337 |
1 |
1 |
338 |
1 |
1 |
|
|
|
MISSING_ELSE |
371 |
1 |
1 |
372 |
1 |
1 |
373 |
1 |
1 |
396 |
5 |
5 |
400 |
1 |
1 |
401 |
1 |
1 |
404 |
4 |
4 |
405 |
4 |
4 |
412 |
2 |
2 |
414 |
3 |
3 |
417 |
58 |
58 |
418 |
58 |
58 |
419 |
56 |
58 |
420 |
58 |
58 |
Cond Coverage for Module :
pinmux_strap_sampling
| Total | Covered | Percent |
Conditions | 55 | 55 | 100.00 |
Logical | 55 | 55 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 230
EXPRESSION (lc_strap_sample_en ? in_padring_i[30] : tap_strap_q[0])
---------1--------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 232
EXPRESSION (rv_strap_sample_en ? in_padring_i[27] : tap_strap_q[1])
---------1--------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 236
EXPRESSION (dft_strap_sample_en ? ({in_padring_i[42], in_padring_i[40]}) : dft_strap_q)
---------1---------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 240
EXPRESSION (dft_strap_sample_en | dft_strap_valid_q)
---------1--------- --------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T4,T5,T6 |
LINE 268
EXPRESSION (strap_en_q && tap_sampling_en)
-----1---- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T60,T166,T167 |
1 | 1 | Covered | T4,T5,T6 |
LINE 274
EXPRESSION (strap_en_q || tap_sampling_en)
-----1---- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T44 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T60,T166,T167 |
LINE 396
EXPRESSION (jtag_en ? 1'b0 : in_padring_i[35])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 396
EXPRESSION (jtag_en ? 1'b0 : in_padring_i[36])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 396
EXPRESSION (jtag_en ? 1'b0 : in_padring_i[37])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 396
EXPRESSION (jtag_en ? 1'b0 : in_padring_i[38])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 396
EXPRESSION (jtag_en ? 1'b0 : in_padring_i[39])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 400
EXPRESSION (jtag_en ? jtag_rsp.tdo : out_core_i[36])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 401
EXPRESSION (jtag_en ? jtag_rsp.tdo_oe : oe_core_i[36])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 404
EXPRESSION (jtag_en ? 1'b0 : out_core_i[35])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 404
EXPRESSION (jtag_en ? 1'b0 : out_core_i[37])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 404
EXPRESSION (jtag_en ? 1'b0 : out_core_i[38])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 404
EXPRESSION (jtag_en ? 1'b0 : out_core_i[39])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 405
EXPRESSION (jtag_en ? 1'b0 : oe_core_i[35])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 405
EXPRESSION (jtag_en ? 1'b0 : oe_core_i[37])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 405
EXPRESSION (jtag_en ? 1'b0 : oe_core_i[38])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 405
EXPRESSION (jtag_en ? 1'b0 : oe_core_i[39])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 412
EXPRESSION
Number Term
1 jtag_en ? ('{schmitt_en:1'b1, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0}) : attr_core_i[38])
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 412
EXPRESSION
Number Term
1 jtag_en ? ('{schmitt_en:1'b1, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0}) : attr_core_i[39])
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 414
EXPRESSION (jtag_en ? '0 : attr_core_i[35])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 414
EXPRESSION (jtag_en ? '0 : attr_core_i[36])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
LINE 414
EXPRESSION (jtag_en ? '0 : attr_core_i[37])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T6,T60,T57 |
Branch Coverage for Module :
pinmux_strap_sampling
| Line No. | Total | Covered | Percent |
Branches |
|
59 |
59 |
100.00 |
TERNARY |
230 |
2 |
2 |
100.00 |
TERNARY |
232 |
2 |
2 |
100.00 |
TERNARY |
236 |
2 |
2 |
100.00 |
TERNARY |
396 |
2 |
2 |
100.00 |
TERNARY |
404 |
2 |
2 |
100.00 |
TERNARY |
405 |
2 |
2 |
100.00 |
TERNARY |
414 |
2 |
2 |
100.00 |
TERNARY |
396 |
2 |
2 |
100.00 |
TERNARY |
400 |
2 |
2 |
100.00 |
TERNARY |
401 |
2 |
2 |
100.00 |
TERNARY |
414 |
2 |
2 |
100.00 |
TERNARY |
396 |
2 |
2 |
100.00 |
TERNARY |
404 |
2 |
2 |
100.00 |
TERNARY |
405 |
2 |
2 |
100.00 |
TERNARY |
414 |
2 |
2 |
100.00 |
TERNARY |
396 |
2 |
2 |
100.00 |
TERNARY |
404 |
2 |
2 |
100.00 |
TERNARY |
405 |
2 |
2 |
100.00 |
TERNARY |
412 |
2 |
2 |
100.00 |
TERNARY |
396 |
2 |
2 |
100.00 |
TERNARY |
404 |
2 |
2 |
100.00 |
TERNARY |
405 |
2 |
2 |
100.00 |
TERNARY |
412 |
2 |
2 |
100.00 |
IF |
268 |
2 |
2 |
100.00 |
IF |
274 |
3 |
3 |
100.00 |
IF |
283 |
2 |
2 |
100.00 |
CASE |
321 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 230 (lc_strap_sample_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 232 (rv_strap_sample_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 236 (dft_strap_sample_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 396 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 404 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 405 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 414 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 396 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 400 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 401 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 414 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 396 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 404 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 405 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 414 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 396 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 404 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 405 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 412 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 396 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 404 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 405 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 412 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T60,T57 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 268 if ((strap_en_q && tap_sampling_en))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 274 if ((strap_en_q || tap_sampling_en))
-2-: 276 if (lc_ctrl_pkg::lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnSample]))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T4,T5,T6 |
1 |
0 |
Covered |
T4,T5,T6 |
0 |
- |
Covered |
T4,T5,T44 |
LineNo. Expression
-1-: 283 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 321 case (tap_strap)
-2-: 328 if (lc_ctrl_pkg::lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnTapSel]))
-3-: 335 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_dft_en[DftEnTapSel]))
Branches:
-1- | -2- | -3- | Status | Tests |
LcTapSel |
- |
- |
Covered |
T6,T60,T57 |
RvTapSel |
1 |
- |
Covered |
T58,T74,T75 |
RvTapSel |
0 |
- |
Covered |
T744,T745,T746 |
DftTapSel |
- |
1 |
Covered |
T77,T78,T79 |
DftTapSel |
- |
0 |
Covered |
T80 |
default |
- |
- |
Covered |
T4,T5,T6 |
Assert Coverage for Module :
pinmux_strap_sampling
Assertion Details
DftTapOff0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130367240 |
38594689 |
0 |
276 |
T1 |
0 |
0 |
0 |
2 |
T2 |
0 |
0 |
0 |
2 |
T4 |
68163 |
10059 |
0 |
0 |
T5 |
208018 |
2502 |
0 |
2 |
T6 |
67021 |
2482 |
0 |
0 |
T15 |
52234 |
2481 |
0 |
0 |
T16 |
53735 |
2484 |
0 |
0 |
T18 |
0 |
0 |
0 |
2 |
T44 |
51895 |
7991 |
0 |
0 |
T45 |
53694 |
4966 |
0 |
0 |
T57 |
0 |
0 |
0 |
2 |
T60 |
0 |
0 |
0 |
2 |
T92 |
17736 |
2484 |
0 |
0 |
T93 |
22856 |
2482 |
0 |
0 |
T94 |
22219 |
2483 |
0 |
0 |
T113 |
0 |
0 |
0 |
2 |
T166 |
0 |
0 |
0 |
2 |
T167 |
0 |
0 |
0 |
2 |
T246 |
0 |
0 |
0 |
2 |
LcHwDebugEnClear_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130367240 |
11949321 |
0 |
15 |
T4 |
68163 |
5093 |
0 |
0 |
T5 |
208018 |
0 |
0 |
0 |
T6 |
67021 |
0 |
0 |
0 |
T15 |
52234 |
0 |
0 |
0 |
T16 |
53735 |
0 |
0 |
0 |
T44 |
51895 |
0 |
0 |
0 |
T45 |
53694 |
0 |
0 |
0 |
T57 |
0 |
1772 |
0 |
1 |
T67 |
0 |
0 |
0 |
1 |
T68 |
0 |
12216 |
0 |
0 |
T69 |
0 |
4982 |
0 |
0 |
T92 |
17736 |
0 |
0 |
0 |
T93 |
22856 |
0 |
0 |
0 |
T94 |
22219 |
0 |
0 |
0 |
T108 |
0 |
4984 |
0 |
0 |
T111 |
0 |
4975 |
0 |
0 |
T172 |
0 |
5101 |
0 |
0 |
T177 |
0 |
14586 |
0 |
0 |
T188 |
0 |
0 |
0 |
1 |
T189 |
0 |
0 |
0 |
1 |
T235 |
0 |
5103 |
0 |
0 |
T284 |
0 |
0 |
0 |
1 |
T325 |
0 |
4981 |
0 |
0 |
T747 |
0 |
0 |
0 |
1 |
T748 |
0 |
0 |
0 |
1 |
T749 |
0 |
0 |
0 |
1 |
T750 |
0 |
0 |
0 |
1 |
T751 |
0 |
0 |
0 |
1 |
LcHwDebugEnSetRev0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130367240 |
1465 |
0 |
98 |
T1 |
0 |
0 |
0 |
1 |
T2 |
0 |
0 |
0 |
1 |
T4 |
68163 |
2 |
0 |
0 |
T5 |
208018 |
1 |
0 |
1 |
T6 |
67021 |
1 |
0 |
0 |
T15 |
52234 |
1 |
0 |
0 |
T16 |
53735 |
1 |
0 |
0 |
T18 |
0 |
0 |
0 |
1 |
T44 |
51895 |
2 |
0 |
0 |
T45 |
53694 |
2 |
0 |
0 |
T57 |
0 |
0 |
0 |
1 |
T58 |
0 |
0 |
0 |
1 |
T92 |
17736 |
1 |
0 |
0 |
T93 |
22856 |
1 |
0 |
0 |
T94 |
22219 |
1 |
0 |
0 |
T113 |
0 |
0 |
0 |
1 |
T183 |
0 |
0 |
0 |
1 |
T236 |
0 |
0 |
0 |
1 |
T246 |
0 |
0 |
0 |
1 |
LcHwDebugEnSetRev1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130367240 |
1465 |
0 |
98 |
T1 |
0 |
0 |
0 |
1 |
T2 |
0 |
0 |
0 |
1 |
T4 |
68163 |
2 |
0 |
0 |
T5 |
208018 |
1 |
0 |
1 |
T6 |
67021 |
1 |
0 |
0 |
T15 |
52234 |
1 |
0 |
0 |
T16 |
53735 |
1 |
0 |
0 |
T18 |
0 |
0 |
0 |
1 |
T44 |
51895 |
2 |
0 |
0 |
T45 |
53694 |
2 |
0 |
0 |
T57 |
0 |
0 |
0 |
1 |
T58 |
0 |
0 |
0 |
1 |
T92 |
17736 |
1 |
0 |
0 |
T93 |
22856 |
1 |
0 |
0 |
T94 |
22219 |
1 |
0 |
0 |
T113 |
0 |
0 |
0 |
1 |
T183 |
0 |
0 |
0 |
1 |
T236 |
0 |
0 |
0 |
1 |
T246 |
0 |
0 |
0 |
1 |
LcHwDebugEnSet_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130367240 |
1465 |
0 |
0 |
T4 |
68163 |
2 |
0 |
0 |
T5 |
208018 |
1 |
0 |
0 |
T6 |
67021 |
1 |
0 |
0 |
T15 |
52234 |
1 |
0 |
0 |
T16 |
53735 |
1 |
0 |
0 |
T44 |
51895 |
2 |
0 |
0 |
T45 |
53694 |
2 |
0 |
0 |
T92 |
17736 |
1 |
0 |
0 |
T93 |
22856 |
1 |
0 |
0 |
T94 |
22219 |
1 |
0 |
0 |
RvTapOff0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130367240 |
259 |
0 |
196 |
T1 |
25075 |
1 |
0 |
2 |
T2 |
0 |
1 |
0 |
2 |
T25 |
57198 |
0 |
0 |
0 |
T57 |
14169 |
2 |
0 |
2 |
T58 |
0 |
0 |
0 |
2 |
T59 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
2 |
T108 |
71075 |
0 |
0 |
0 |
T113 |
0 |
2 |
0 |
2 |
T120 |
545249 |
0 |
0 |
0 |
T133 |
113580 |
0 |
0 |
0 |
T178 |
0 |
2 |
0 |
0 |
T183 |
0 |
11 |
0 |
2 |
T191 |
0 |
0 |
0 |
2 |
T232 |
54717 |
0 |
0 |
0 |
T236 |
0 |
3 |
0 |
2 |
T241 |
43924 |
0 |
0 |
0 |
T246 |
63769 |
1 |
0 |
2 |
T336 |
38841 |
0 |
0 |
0 |
RvTapOff1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130367240 |
35820381 |
0 |
0 |
T4 |
68163 |
10435 |
0 |
0 |
T5 |
208018 |
2732 |
0 |
0 |
T6 |
67021 |
2763 |
0 |
0 |
T15 |
52234 |
2798 |
0 |
0 |
T16 |
53735 |
3103 |
0 |
0 |
T44 |
51895 |
5905 |
0 |
0 |
T45 |
53694 |
5823 |
0 |
0 |
T92 |
17736 |
3205 |
0 |
0 |
T93 |
22856 |
2831 |
0 |
0 |
T94 |
22219 |
2827 |
0 |
0 |
TapStrapKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130367240 |
129694826 |
0 |
0 |
T4 |
68163 |
67659 |
0 |
0 |
T5 |
208018 |
207455 |
0 |
0 |
T6 |
67021 |
66592 |
0 |
0 |
T15 |
52234 |
51647 |
0 |
0 |
T16 |
53735 |
52972 |
0 |
0 |
T44 |
51895 |
50528 |
0 |
0 |
T45 |
53694 |
52947 |
0 |
0 |
T92 |
17736 |
17020 |
0 |
0 |
T93 |
22856 |
22198 |
0 |
0 |
T94 |
22219 |
21802 |
0 |
0 |
dft_strap0_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1017 |
1017 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T44 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T92 |
1 |
1 |
0 |
0 |
T93 |
1 |
1 |
0 |
0 |
T94 |
1 |
1 |
0 |
0 |
dft_strap1_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1017 |
1017 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T44 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T92 |
1 |
1 |
0 |
0 |
T93 |
1 |
1 |
0 |
0 |
T94 |
1 |
1 |
0 |
0 |
tap_strap0_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1017 |
1017 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T44 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T92 |
1 |
1 |
0 |
0 |
T93 |
1 |
1 |
0 |
0 |
T94 |
1 |
1 |
0 |
0 |
tap_strap1_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1017 |
1017 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T44 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T92 |
1 |
1 |
0 |
0 |
T93 |
1 |
1 |
0 |
0 |
T94 |
1 |
1 |
0 |
0 |
tck_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1017 |
1017 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T44 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T92 |
1 |
1 |
0 |
0 |
T93 |
1 |
1 |
0 |
0 |
T94 |
1 |
1 |
0 |
0 |
tdi_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1017 |
1017 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T44 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T92 |
1 |
1 |
0 |
0 |
T93 |
1 |
1 |
0 |
0 |
T94 |
1 |
1 |
0 |
0 |
tdo_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1017 |
1017 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T44 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T92 |
1 |
1 |
0 |
0 |
T93 |
1 |
1 |
0 |
0 |
T94 |
1 |
1 |
0 |
0 |
tms_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1017 |
1017 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T44 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T92 |
1 |
1 |
0 |
0 |
T93 |
1 |
1 |
0 |
0 |
T94 |
1 |
1 |
0 |
0 |
trst_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1017 |
1017 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T44 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
T92 |
1 |
1 |
0 |
0 |
T93 |
1 |
1 |
0 |
0 |
T94 |
1 |
1 |
0 |
0 |