Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : uart
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_uart0 100.00 100.00
tb.dut.top_earlgrey.u_uart1 100.00 100.00
tb.dut.top_earlgrey.u_uart2 100.00 100.00
tb.dut.top_earlgrey.u_uart3 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.62 88.53 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.62 88.53 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.62 88.53 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.62 88.53 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : uart
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 308 308 100.00
Total Bits 0->1 154 154 100.00
Total Bits 1->0 154 154 100.00

Ports 40 40 100.00
Port Bits 308 308 100.00
Port Bits 0->1 154 154 100.00
Port Bits 1->0 154 154 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T5,T15,T16 Yes T5,T15,T16 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T5,T15,T16 Yes T5,T15,T16 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T83,*T84,*T85 Yes T83,T84,T85 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T58,*T75,*T76 Yes T58,T75,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T58,T76,T86 Yes T58,T76,T86 INPUT
tl_i.a_valid Yes Yes T5,T15,T16 Yes T5,T15,T16 INPUT
tl_o.a_ready Yes Yes T5,T15,T16 Yes T5,T15,T16 OUTPUT
tl_o.d_error Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T5,T15,T16 Yes T5,T15,T16 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T5,T15,T16 Yes T5,T15,T16 OUTPUT
tl_o.d_data[31:0] Yes Yes T5,T15,T16 Yes T5,T15,T16 OUTPUT
tl_o.d_sink Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
tl_o.d_source[5:0] Yes Yes *T785,*T269,*T788 Yes T785,T269,T788 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T5,*T15,*T16 Yes T5,T15,T16 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T5,T15,T16 Yes T5,T15,T16 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T69,T336,T108 Yes T69,T336,T108 INPUT
alert_rx_i[0].ping_n Yes Yes T226,T88,T89 Yes T226,T88,T89 INPUT
alert_rx_i[0].ping_p Yes Yes T226,T88,T89 Yes T226,T88,T89 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T69,T336,T108 Yes T69,T336,T108 OUTPUT
cio_rx_i Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
cio_tx_o Yes Yes T5,T15,T16 Yes T5,T15,T16 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T15,T16,T161 Yes T15,T16,T161 OUTPUT
intr_tx_empty_o Yes Yes T15,T16,T161 Yes T15,T16,T161 OUTPUT
intr_rx_watermark_o Yes Yes T15,T16,T161 Yes T15,T16,T161 OUTPUT
intr_tx_done_o Yes Yes T15,T16,T161 Yes T15,T16,T161 OUTPUT
intr_rx_overflow_o Yes Yes T15,T16,T161 Yes T15,T16,T161 OUTPUT
intr_rx_frame_err_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT
intr_rx_break_err_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT
intr_rx_timeout_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT
intr_rx_parity_err_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 304 304 100.00
Total Bits 0->1 152 152 100.00
Total Bits 1->0 152 152 100.00

Ports 40 40 100.00
Port Bits 304 304 100.00
Port Bits 0->1 152 152 100.00
Port Bits 1->0 152 152 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T5,T56,T18 Yes T5,T56,T18 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T5,T56,T18 Yes T5,T56,T18 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T83,*T84,*T85 Yes T83,T84,T85 INPUT
tl_i.a_address[29:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T58,*T75,*T76 Yes T58,T75,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T58,T76,T86 Yes T58,T76,T86 INPUT
tl_i.a_valid Yes Yes T5,T56,T18 Yes T5,T56,T18 INPUT
tl_o.a_ready Yes Yes T5,T56,T18 Yes T5,T56,T18 OUTPUT
tl_o.d_error Yes Yes T84,T85,T135 Yes T84,T85,T135 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T5,T56,T18 Yes T5,T56,T18 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T5,T56,T18 Yes T5,T56,T18 OUTPUT
tl_o.d_data[31:0] Yes Yes T5,T56,T18 Yes T5,T56,T18 OUTPUT
tl_o.d_sink Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
tl_o.d_source[5:0] Yes Yes *T785,*T269,*T788 Yes T785,T269,T788 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T84,T85,T135 Yes T83,T84,T85 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T5,*T56,*T18 Yes T5,T56,T18 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T5,T56,T18 Yes T5,T56,T18 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T61,T62,T171 Yes T61,T62,T171 INPUT
alert_rx_i[0].ping_n Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_rx_i[0].ping_p Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T61,T62,T171 Yes T61,T62,T171 OUTPUT
cio_rx_i Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
cio_tx_o Yes Yes T5,T56,T18 Yes T5,T56,T18 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T232,T91,T341 Yes T232,T91,T341 OUTPUT
intr_tx_empty_o Yes Yes T232,T91,T341 Yes T232,T91,T341 OUTPUT
intr_rx_watermark_o Yes Yes T232,T91,T341 Yes T232,T91,T341 OUTPUT
intr_tx_done_o Yes Yes T232,T91,T341 Yes T232,T91,T341 OUTPUT
intr_rx_overflow_o Yes Yes T232,T91,T341 Yes T232,T91,T341 OUTPUT
intr_rx_frame_err_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT
intr_rx_break_err_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT
intr_rx_timeout_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT
intr_rx_parity_err_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 306 306 100.00
Total Bits 0->1 153 153 100.00
Total Bits 1->0 153 153 100.00

Ports 40 40 100.00
Port Bits 306 306 100.00
Port Bits 0->1 153 153 100.00
Port Bits 1->0 153 153 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T15,T16,T112 Yes T15,T16,T112 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T15,T16,T112 Yes T15,T16,T112 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T83,*T84,*T85 Yes T83,T84,T85 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T58,*T75,*T76 Yes T58,T75,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T58,T76,T86 Yes T58,T76,T86 INPUT
tl_i.a_valid Yes Yes T15,T16,T112 Yes T15,T16,T112 INPUT
tl_o.a_ready Yes Yes T15,T16,T112 Yes T15,T16,T112 OUTPUT
tl_o.d_error Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T15,T16,T112 Yes T15,T16,T112 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T15,T16,T112 Yes T15,T16,T112 OUTPUT
tl_o.d_data[31:0] Yes Yes T15,T16,T112 Yes T15,T16,T112 OUTPUT
tl_o.d_sink Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
tl_o.d_source[5:0] Yes Yes *T84,*T85,*T87 Yes T83,T84,T85 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T84,T85,T87 Yes T83,T84,T85 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T15,*T16,*T112 Yes T15,T16,T112 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T15,T16,T112 Yes T15,T16,T112 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T61,T62,T171 Yes T61,T62,T171 INPUT
alert_rx_i[0].ping_n Yes Yes T226,T88,T89 Yes T226,T88,T89 INPUT
alert_rx_i[0].ping_p Yes Yes T226,T88,T89 Yes T226,T88,T89 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T61,T62,T171 Yes T61,T62,T171 OUTPUT
cio_rx_i Yes Yes T15,T16,T112 Yes T15,T16,T112 INPUT
cio_tx_o Yes Yes T15,T16,T112 Yes T15,T16,T112 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T15,T16,T112 Yes T15,T16,T112 OUTPUT
intr_tx_empty_o Yes Yes T15,T16,T112 Yes T15,T16,T112 OUTPUT
intr_rx_watermark_o Yes Yes T15,T16,T112 Yes T15,T16,T112 OUTPUT
intr_tx_done_o Yes Yes T15,T16,T112 Yes T15,T16,T112 OUTPUT
intr_rx_overflow_o Yes Yes T15,T16,T112 Yes T15,T16,T112 OUTPUT
intr_rx_frame_err_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT
intr_rx_break_err_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT
intr_rx_timeout_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT
intr_rx_parity_err_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 306 306 100.00
Total Bits 0->1 153 153 100.00
Total Bits 1->0 153 153 100.00

Ports 40 40 100.00
Port Bits 306 306 100.00
Port Bits 0->1 153 153 100.00
Port Bits 1->0 153 153 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T161,T162,T163 Yes T161,T162,T163 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T161,T162,T163 Yes T161,T162,T163 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T83,*T84,*T85 Yes T83,T84,T85 INPUT
tl_i.a_address[16:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T58,*T75,*T76 Yes T58,T75,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T58,T76,T86 Yes T58,T76,T86 INPUT
tl_i.a_valid Yes Yes T161,T162,T163 Yes T161,T162,T163 INPUT
tl_o.a_ready Yes Yes T161,T162,T163 Yes T161,T162,T163 OUTPUT
tl_o.d_error Yes Yes T84,T85,T135 Yes T84,T85,T135 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T161,T162,T163 Yes T161,T162,T163 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T161,T162,T163 Yes T161,T162,T163 OUTPUT
tl_o.d_data[31:0] Yes Yes T161,T162,T163 Yes T161,T162,T163 OUTPUT
tl_o.d_sink Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
tl_o.d_source[5:0] Yes Yes *T84,*T85,*T135 Yes T83,T84,T85 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T161,*T162,*T163 Yes T161,T162,T163 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T161,T162,T163 Yes T161,T162,T163 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T69,T336,T108 Yes T69,T336,T108 INPUT
alert_rx_i[0].ping_n Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_rx_i[0].ping_p Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T69,T336,T108 Yes T69,T336,T108 OUTPUT
cio_rx_i Yes Yes T161,T162,T163 Yes T161,T162,T163 INPUT
cio_tx_o Yes Yes T161,T162,T163 Yes T161,T162,T163 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T161,T162,T163 Yes T161,T162,T163 OUTPUT
intr_tx_empty_o Yes Yes T161,T162,T163 Yes T161,T162,T163 OUTPUT
intr_rx_watermark_o Yes Yes T161,T162,T163 Yes T161,T162,T163 OUTPUT
intr_tx_done_o Yes Yes T161,T162,T163 Yes T161,T162,T163 OUTPUT
intr_rx_overflow_o Yes Yes T161,T162,T163 Yes T161,T162,T163 OUTPUT
intr_rx_frame_err_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT
intr_rx_break_err_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT
intr_rx_timeout_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT
intr_rx_parity_err_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 308 308 100.00
Total Bits 0->1 154 154 100.00
Total Bits 1->0 154 154 100.00

Ports 40 40 100.00
Port Bits 308 308 100.00
Port Bits 0->1 154 154 100.00
Port Bits 1->0 154 154 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T25,T26,T27 Yes T25,T26,T27 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T25,T26,T27 Yes T25,T26,T27 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T83,*T84,*T85 Yes T83,T84,T85 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T58,*T75,*T76 Yes T58,T75,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T58,T76,T86 Yes T58,T76,T86 INPUT
tl_i.a_valid Yes Yes T25,T26,T27 Yes T25,T26,T27 INPUT
tl_o.a_ready Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
tl_o.d_error Yes Yes T84,T85,T135 Yes T84,T85,T135 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
tl_o.d_data[31:0] Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
tl_o.d_sink Yes Yes T84,T85,T135 Yes T83,T84,T85 OUTPUT
tl_o.d_source[5:0] Yes Yes *T84,*T85,*T135 Yes T84,T85,T135 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T83,T84,T85 Yes T84,T85,T135 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T25,*T26,*T27 Yes T25,T26,T27 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T61,T62,T171 Yes T61,T62,T171 INPUT
alert_rx_i[0].ping_n Yes Yes T226,T88,T89 Yes T226,T88,T89 INPUT
alert_rx_i[0].ping_p Yes Yes T226,T88,T89 Yes T226,T88,T89 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T61,T62,T171 Yes T61,T62,T171 OUTPUT
cio_rx_i Yes Yes T25,T26,T27 Yes T25,T26,T27 INPUT
cio_tx_o Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
intr_tx_empty_o Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
intr_rx_watermark_o Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
intr_tx_done_o Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
intr_rx_overflow_o Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
intr_rx_frame_err_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT
intr_rx_break_err_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT
intr_rx_timeout_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT
intr_rx_parity_err_o Yes Yes T331,T332,T334 Yes T331,T332,T334 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%