Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.62	88.53		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T84,T85,T87	Yes	T83,T84,T85	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T84,T135,T261	Yes	T84,T135,T261	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T177,T108,T113	Yes	T177,T108,T113	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T177,T108,T113	Yes	T177,T108,T113	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T58,T8,T84	Yes	T58,T8,T84	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T58,T8,T83	Yes	T58,T8,T83	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T4,T68,T69	Yes	T4,T68,T69	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T58,T74,T75	Yes	T58,T74,T75	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T58,T74,T75	Yes	T58,T74,T75	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T58,T74,T75	Yes	T58,T74,T75	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T58,T75,T76	Yes	T58,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T58,T74,T75	Yes	T58,T74,T75	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T58,T75,T76	Yes	T58,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T58,T74,T75	Yes	T58,T74,T75	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T8,T9,T83	Yes	T8,T9,T83	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T8,T9,T83	Yes	T8,T9,T83	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T8,T9,T83	Yes	T8,T9,T83	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T8,T9,T83	Yes	T8,T9,T83	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T8,T9,T83	Yes	T8,T9,T83	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T8,*T9,T83	Yes	T8,T9,T83	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T8,T9,T83	Yes	T8,T9,T83	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T8,T9,T84	Yes	T8,T9,T83	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T8,T9,T83	Yes	T8,T9,T83	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T9,T83	Yes	T8,T9,T83	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T8,T9,T83	Yes	T8,T9,T83	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T8,*T9,T84	Yes	T8,T9,T83	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T8,*T9,*T83	Yes	T8,T9,T83	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T8,T9,T83	Yes	T8,T9,T83	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T74,T267,T8	Yes	T74,T267,T8	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T74,T267,T8	Yes	T74,T267,T8	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T74,T267,T8	Yes	T74,T267,T8	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T74,T267,T8	Yes	T74,T267,T8	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T74,T267,T8	Yes	T74,T267,T8	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T74,*T267,*T268	Yes	T74,T267,T268	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T74,T267,T8	Yes	T74,T267,T8	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T44	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T74,T267,T268	Yes	T74,T267,T268	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T74,T267,T8	Yes	T74,T267,T8	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T44	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T74,*T267,*T268	Yes	T74,T267,T268	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T44	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T74,T267,T8	Yes	T74,T267,T8	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T5,T60,T56	Yes	T5,T60,T56	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T83,*T84,*T85	Yes	T83,T84,T85	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T61,T62,T8	Yes	T61,T62,T8	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T246,T61,T62	Yes	T246,T61,T62	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T246,T61,T62	Yes	T246,T61,T62	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T61,T62,T8	Yes	T61,T62,T8	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T246,T61,T62	Yes	T246,T61,T62	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T8,*T9,*T83	Yes	T8,T9,T83	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T246,T61,T62	Yes	T246,T61,T62	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T246,T61,T62	Yes	T246,T61,T62	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T246,T412,T413	Yes	T246,T412,T413	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T9,T84	Yes	T61,T62,T8	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T246,T8,T412	Yes	T246,T61,T62	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T8,*T9,T84	Yes	T8,T9,T83	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T246,*T8,*T9	Yes	T246,T8,T412	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T246,T61,T62	Yes	T246,T61,T62	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T69,T108,T111	Yes	T69,T108,T111	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T22,T402,T168	Yes	T22,T402,T168	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T22,T168,T61	Yes	T22,T168,T61	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T22,T402,T168	Yes	T22,T402,T168	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T22,T402,T168	Yes	T22,T402,T168	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T22,T168,T61	Yes	T22,T168,T61	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T22,T402,T168	Yes	T22,T402,T168	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T214,*T83,*T84	Yes	T214,T83,T84	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T23,T210,T211	Yes	T23,T210,T211	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T22,T402,T168	Yes	T22,T402,T168	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T22,T402,T168	Yes	T22,T402,T168	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T22,T168,T391	Yes	T22,T168,T391	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T22,T402,T168	Yes	T22,T402,T168	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T22,T168,T391	Yes	T22,T168,T391	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T214,*T83,*T84	Yes	T214,T83,T84	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T22,*T402,*T168	Yes	T22,T402,T168	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T22,T402,T168	Yes	T22,T402,T168	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T402,T168,T61	Yes	T402,T168,T61	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T168,T61,T62	Yes	T168,T61,T62	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T402,T168,T61	Yes	T402,T168,T61	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T402,T168,T61	Yes	T402,T168,T61	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T168,T61,T62	Yes	T168,T61,T62	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T402,T168,T61	Yes	T402,T168,T61	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T214,T83,*T84	Yes	T214,T83,T84	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T402,T168,T61	Yes	T402,T168,T61	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T402,T168,T61	Yes	T402,T168,T61	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T168,T391,T214	Yes	T168,T391,T214	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T402,T168,T391	Yes	T402,T168,T61	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T168,T391,T214	Yes	T168,T391,T214	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T214,T83,*T84	Yes	T214,T83,T84	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T402,*T168,*T391	Yes	T402,T168,T391	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T402,T168,T61	Yes	T402,T168,T61	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T87	Yes	T84,T85,T87	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T84,T85,T134	Yes	T84,T85,T134	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
tl_usbdev_i.d_error	Yes	Yes	T84,T85,T134	Yes	T84,T85,T134	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T29,T30,T402	Yes	T29,T30,T402	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T30,T402	Yes	T29,T30,T402	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T84,T85,T87	Yes	T84,T85,T87	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T87	Yes	T84,T85,T87	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T84,T85,T134	Yes	T84,T85,T134	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T28,*T29,*T30	Yes	T28,T29,T30	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T83,*T84,*T85	Yes	T83,T84,T85	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T44	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T44	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T136	Yes	T83,T84,T85	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T84,T85,T87	Yes	T83,T84,T85	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T84,T85,T87	Yes	T83,T84,T85	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T84,T85,T87	Yes	T83,T84,T85	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T83,*T84,*T85	Yes	T83,T84,T85	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T44	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T83,*T84,*T85	Yes	T83,T84,T85	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_hmac_o.d_ready	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T5,T45,T56	Yes	T5,T45,T56	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T5,T45,T56	Yes	T5,T45,T56	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T83,*T84,*T85	Yes	T83,T84,T85	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T772,T773,T774	Yes	T772,T773,T774	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T5,T45,T56	Yes	T5,T45,T56	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T5,T45,T56	Yes	T5,T45,T56	INPUT
tl_hmac_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	INPUT
tl_hmac_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T83,*T84,*T85	Yes	T83,T84,T85	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T5,*T56,*T18	Yes	T5,T56,T18	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	INPUT
tl_kmac_o.d_ready	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T440,T133,T241	Yes	T440,T133,T241	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T45,T123,T166	Yes	T45,T123,T166	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T45,T123,T166	Yes	T45,T123,T166	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T440,T133,T241	Yes	T440,T133,T241	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T45,T123,T166	Yes	T45,T123,T166	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T9,*T83,*T84	Yes	T9,T83,T84	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T440,T110,T114	Yes	T440,T110,T114	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T45,T123,T166	Yes	T45,T123,T166	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T45,T123,T166	Yes	T45,T123,T166	INPUT
tl_kmac_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T45,T123,T166	Yes	T45,T123,T166	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T123,T166	Yes	T45,T123,T166	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T123,T166,T440	Yes	T166,T440,T167	INPUT
tl_kmac_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T9,*T84,*T85	Yes	T9,T83,T84	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T123,*T166,*T440	Yes	T166,T440,T167	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T45,T123,T166	Yes	T45,T123,T166	INPUT
tl_aes_o.d_ready	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T93,T94,T123	Yes	T93,T94,T123	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T93,T94,T123	Yes	T93,T94,T123	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T45,T93,T94	Yes	T45,T93,T94	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T93,T94,T123	Yes	T93,T94,T123	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T45,T93,T94	Yes	T45,T93,T94	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T83,*T84,*T85	Yes	T83,T84,T85	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T45,T93,T94	Yes	T45,T93,T94	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T45,T93,T94	Yes	T45,T93,T94	INPUT
tl_aes_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T45,T93,T94	Yes	T45,T93,T94	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T93,T94,T123	Yes	T93,T94,T123	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T45,T93,T94	Yes	T45,T93,T94	INPUT
tl_aes_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T87	Yes	T83,T84,T85	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T45,*T93,*T94	Yes	T45,T93,T94	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T45,T93,T94	Yes	T45,T93,T94	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T83,*T84,*T85	Yes	T83,T84,T85	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T123,T132,T133	Yes	T123,T132,T133	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T83,*T84,*T85	Yes	T83,T84,T85	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T123,*T132,*T133	Yes	T123,T132,T56	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T736,T123,T132	Yes	T736,T123,T132	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T83,*T84,*T85	Yes	T83,T84,T85	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T84,T85,T136	Yes	T84,T85,T136	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_error	Yes	Yes	T84,T85,T136	Yes	T84,T85,T136	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T736,T123,T132	Yes	T736,T123,T132	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T136	Yes	T83,T84,T85	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T736,*T123,*T132	Yes	T736,T123,T132	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T123,T132,T133	Yes	T123,T132,T133	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T123,T132,T133	Yes	T123,T132,T133	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T83,*T84,*T85	Yes	T83,T84,T85	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_error	Yes	Yes	T84,T85,T87	Yes	T83,T84,T85	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T123,T132,T133	Yes	T123,T132,T133	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T87	Yes	T83,T84,T85	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T84,T85,T87	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T123,*T132,*T133	Yes	T123,T132,T133	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn1_o.d_ready	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T123,T132,T133	Yes	T123,T132,T133	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T123,T132,T133	Yes	T123,T132,T133	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T123,T132,T133	Yes	T123,T132,T133	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T123,T132,T133	Yes	T123,T132,T133	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T123,T132,T133	Yes	T123,T132,T133	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T83,*T84,*T85	Yes	T83,T84,T85	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T123,T132,T133	Yes	T123,T132,T133	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T123,T132,T133	Yes	T123,T132,T133	INPUT
tl_edn1_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T123,T132,T133	Yes	T123,T132,T133	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T123,T132,T133	Yes	T123,T132,T133	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T123,T132,T133	Yes	T123,T132,T133	INPUT
tl_edn1_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T135	Yes	T83,T84,T85	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T123,*T132,*T133	Yes	T123,T132,T133	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T123,T132,T133	Yes	T123,T132,T133	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T214,*T83,*T84	Yes	T214,T83,T84	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T84,T85,T134	Yes	T84,T85,T134	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T84,T85,T134	Yes	T84,T85,T134	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T84,T85,T135	Yes	T84,T85,T135	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T214,*T84,*T85	Yes	T214,T84,T85	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T84,T85,T134	Yes	T84,T85,T134	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T4,*T15,*T16	Yes	T4,T15,T16	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
tl_otbn_o.d_ready	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T5,T123,T132	Yes	T5,T123,T132	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T45,T123	Yes	T5,T45,T123	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T5,T45,T123	Yes	T5,T45,T123	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T5,T123,T132	Yes	T5,T123,T132	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T5,T45,T123	Yes	T5,T45,T123	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T58,*T76,*T86	Yes	T58,T76,T86	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T5,T45,T123	Yes	T5,T45,T123	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T5,T45,T123	Yes	T5,T45,T123	INPUT
tl_otbn_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T5,T123,T132	Yes	T5,T123,T132	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T45,T123	Yes	T5,T45,T123	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T5,T45,T123	Yes	T5,T45,T123	INPUT
tl_otbn_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T58,*T76,*T86	Yes	T58,T76,T86	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T5,*T123,*T132	Yes	T5,T123,T132	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T5,T45,T123	Yes	T5,T45,T123	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T123,T166,T167	Yes	T123,T166,T167	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T123,T166,T167	Yes	T123,T166,T167	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T123,T166,T167	Yes	T123,T166,T167	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T123,T166,T167	Yes	T123,T166,T167	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T123,T166,T167	Yes	T123,T166,T167	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T83,*T84,*T85	Yes	T83,T84,T85	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T123,T166,T167	Yes	T123,T166,T167	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T123,T166,T167	Yes	T123,T166,T167	INPUT
tl_keymgr_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T123,T166,T167	Yes	T123,T166,T167	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T123,T166,T167	Yes	T123,T166,T167	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T123,T166,T167	Yes	T123,T166,T167	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T84,T85,T87	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T87	Yes	T83,T84,T85	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T123,*T166,*T167	Yes	T123,T166,T167	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T123,T166,T167	Yes	T123,T166,T167	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T6,T44	Yes	T4,T6,T44	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T8,*T9,*T269	Yes	T8,T9,T269	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T8,T9,T83	Yes	T8,T9,T83	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T65	Yes	T4,T5,T65	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T4,T5,T65	Yes	T4,T5,T65	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T84,T85,T87	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T8,*T9,*T84	Yes	T8,T9,T269	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T84,T85,T134	Yes	T83,T84,T85	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T74,*T268,*T427	Yes	T74,T268,T427	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T84,T85,T87	Yes	T84,T85,T87	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T84,T85,T87	Yes	T84,T85,T87	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T113,T194,T214	Yes	T113,T194,T214	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T18,T113	Yes	T5,T56,T18	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T5,T18,T113	Yes	T5,T56,T18	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T214,*T83,*T84	Yes	T74,T268,T427	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T113,*T125,*T193	Yes	T113,T125,T193	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T44	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range