Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.62	88.53		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_peri_ni	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_error	Yes	Yes	T69,T108,T111	Yes	T69,T108,T111	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	INPUT
tl_uart0_i.d_error	Yes	Yes	T84,T85,T135	Yes	T84,T85,T135	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	INPUT
tl_uart0_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T785,*T269,*T788	Yes	T785,T269,T788	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T84,T85,T135	Yes	T83,T84,T85	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T5,*T56,*T18	Yes	T5,T56,T18	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T15,T16,T112	Yes	T15,T16,T112	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T15,T16,T112	Yes	T15,T16,T112	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T15,T16,T112	Yes	T15,T16,T112	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T15,T16,T112	Yes	T15,T16,T112	INPUT
tl_uart1_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T15,T16,T112	Yes	T15,T16,T112	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T16,T112	Yes	T15,T16,T112	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T15,T16,T112	Yes	T15,T16,T112	INPUT
tl_uart1_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T87	Yes	T83,T84,T85	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T84,T85,T87	Yes	T83,T84,T85	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T15,*T16,*T112	Yes	T15,T16,T112	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T15,T16,T112	Yes	T15,T16,T112	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T161,T162,T163	Yes	T161,T162,T163	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T161,T162,T163	Yes	T161,T162,T163	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T161,T162,T163	Yes	T161,T162,T163	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T161,T162,T163	Yes	T161,T162,T163	INPUT
tl_uart2_i.d_error	Yes	Yes	T84,T85,T135	Yes	T84,T85,T135	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T161,T162,T163	Yes	T161,T162,T163	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T161,T162,T163	Yes	T161,T162,T163	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T161,T162,T163	Yes	T161,T162,T163	INPUT
tl_uart2_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T135	Yes	T83,T84,T85	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T161,*T162,*T163	Yes	T161,T162,T163	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T161,T162,T163	Yes	T161,T162,T163	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
tl_uart3_i.d_error	Yes	Yes	T84,T85,T135	Yes	T84,T85,T135	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
tl_uart3_i.d_sink	Yes	Yes	T84,T85,T135	Yes	T83,T84,T85	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T135	Yes	T84,T85,T135	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T84,T85,T135	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T25,*T26,*T27	Yes	T25,T26,T27	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T330,T227,T228	Yes	T330,T227,T228	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T330,T227,T228	Yes	T330,T227,T228	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T330,T227,T228	Yes	T330,T227,T228	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T330,T227,T228	Yes	T330,T227,T228	INPUT
tl_i2c0_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T330,T227,T228	Yes	T330,T227,T228	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T330,T227,T228	Yes	T330,T227,T228	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T330,T227,T228	Yes	T330,T227,T228	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T135	Yes	T83,T84,T85	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T330,*T227,*T228	Yes	T330,T227,T228	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T330,T227,T228	Yes	T330,T227,T228	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T330,T230,T342	Yes	T330,T230,T342	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T330,T230,T342	Yes	T330,T230,T342	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T330,T61,T230	Yes	T330,T61,T230	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T330,T61,T230	Yes	T330,T61,T230	INPUT
tl_i2c1_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T330,T230,T342	Yes	T330,T230,T342	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T330,T230,T342	Yes	T330,T61,T230	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T330,T230,T342	Yes	T330,T61,T230	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T135	Yes	T83,T84,T85	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T84,T85,T135	Yes	T84,T85,T135	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T330,*T230,*T342	Yes	T330,T230,T342	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T330,T61,T230	Yes	T330,T61,T230	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T330,T231,T391	Yes	T330,T231,T391	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T330,T231,T391	Yes	T330,T231,T391	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T330,T231,T61	Yes	T330,T231,T61	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T330,T231,T61	Yes	T330,T231,T61	INPUT
tl_i2c2_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T330,T231,T335	Yes	T330,T231,T335	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T330,T231,T391	Yes	T330,T231,T61	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T330,T231,T391	Yes	T330,T231,T61	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T83,*T84,*T85	Yes	T83,T84,T85	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T330,*T231,*T391	Yes	T330,T231,T391	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T330,T231,T61	Yes	T330,T231,T61	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T229,T168,T9	Yes	T229,T168,T9	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T229,T168,T9	Yes	T229,T168,T9	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T229,T168,T61	Yes	T229,T168,T61	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T229,T168,T61	Yes	T229,T168,T61	INPUT
tl_pattgen_i.d_error	Yes	Yes	T83,T84,T85	Yes	T84,T85,T136	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T229,T168,T9	Yes	T229,T168,T9	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T229,T168,T9	Yes	T229,T168,T61	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T229,T168,T9	Yes	T229,T168,T61	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T9,T84,T85	Yes	T9,T83,T84	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T229,*T168,*T9	Yes	T229,T168,T9	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T229,T168,T61	Yes	T229,T168,T61	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T115,T8,T164	Yes	T115,T8,T164	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T115,T8,T164	Yes	T115,T8,T164	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T115,T61,T62	Yes	T115,T61,T62	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T115,T61,T62	Yes	T115,T61,T62	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T84,T85,T135	Yes	T83,T84,T85	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T115,T8,T164	Yes	T115,T8,T164	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T115,T8,T164	Yes	T115,T61,T62	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T115,T8,T164	Yes	T115,T61,T62	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T84,T85,T135	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T8,*T9,*T84	Yes	T8,T9,T83	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T115,*T8,*T164	Yes	T115,T8,T164	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T115,T61,T62	Yes	T115,T61,T62	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_error	Yes	Yes	T83,T84,T85	Yes	T84,T85,T87	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T330,T36,T37	Yes	T330,T36,T37	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T115,T330,T36	Yes	T115,T330,T61	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T115,T330,T36	Yes	T115,T330,T61	INPUT
tl_gpio_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T87	Yes	T83,T84,T85	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T84,T85,T87	Yes	T83,T84,T85	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T44	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T91,T22,T27	Yes	T91,T22,T27	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T91,T22,T27	Yes	T91,T22,T27	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T91,T22,T27	Yes	T91,T22,T27	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T91,T22,T27	Yes	T91,T22,T27	INPUT
tl_spi_device_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T91,T22,T27	Yes	T91,T22,T27	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T91,T22,T27	Yes	T91,T22,T27	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T91,T22,T27	Yes	T91,T22,T27	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T214,*T84,*T85	Yes	T214,T83,T84	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T91,*T22,*T27	Yes	T91,T22,T27	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T91,T22,T27	Yes	T91,T22,T27	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T115,T348,T265	Yes	T115,T348,T265	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T115,T348,T265	Yes	T115,T348,T265	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T115,T348,T265	Yes	T115,T348,T265	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T115,T348,T265	Yes	T115,T348,T265	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T84,T85,T134	Yes	T84,T85,T134	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T348,T265,T168	Yes	T348,T265,T168	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T115,T348,T265	Yes	T115,T348,T265	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T115,T348,T265	Yes	T115,T348,T265	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T214,*T84,*T85	Yes	T214,T83,T84	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T115,*T348,*T265	Yes	T115,T348,T265	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T115,T348,T265	Yes	T115,T348,T265	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T44,T45	Yes	T5,T44,T45	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T5,T44,T45	Yes	T5,T44,T45	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T5,T44,T45	Yes	T5,T44,T45	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T5,T44,T45	Yes	T5,T44,T45	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T44,T45	Yes	T5,T44,T45	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T44,T45	Yes	T5,T44,T45	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T5,T44,T45	Yes	T5,T44,T45	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T8,*T9,*T83	Yes	T8,T9,T83	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T5,*T44,*T45	Yes	T5,T44,T45	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T5,T44,T45	Yes	T5,T44,T45	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T84,T85,T136	Yes	T83,T84,T85	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T8,*T9,*T84	Yes	T8,T9,T83	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T84,T85,T135	Yes	T84,T85,T135	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T6,T45,T15	Yes	T6,T45,T15	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T6,T45,T15	Yes	T6,T45,T15	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T15,T93	Yes	T6,T15,T93	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T87	Yes	T75,T783,T101	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T84,T85,T87	Yes	T84,T85,T87	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T6,*T45,*T15	Yes	T6,T45,T15	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T83,T84,T87	Yes	T83,T84,T87	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T44	Yes	T4,T6,T44	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T8,*T9,*T84	Yes	T8,T9,T83	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T44	Yes	T4,T6,T44	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T75,*T165,*T9	Yes	T75,T165,T9	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T123,*T166,*T167	Yes	T123,T166,T167	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T9,T83,T84	Yes	T9,T83,T84	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T9,T83,T84	Yes	T9,T83,T84	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T9,T83,T84	Yes	T9,T83,T84	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T44	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T9,T83,T84	Yes	T9,T83,T84	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T83,T84	Yes	T9,T83,T84	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T44	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T9,T84,T85	Yes	T9,T83,T84	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T44	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T9,T83,T84	Yes	T9,T83,T84	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T5,T16,T166	Yes	T5,T16,T166	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T5,T16,T166	Yes	T5,T16,T166	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T5,T16,T166	Yes	T5,T16,T166	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T5,T16,T166	Yes	T5,T16,T166	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T5,T166,T167	Yes	T5,T166,T167	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T59,T66,T126	Yes	T59,T66,T126	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T5,T56,T18	Yes	T5,T16,T56	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T267,*T326,*T9	Yes	T267,T326,T9	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T5,*T166,*T167	Yes	T5,T16,T166	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T5,T16,T166	Yes	T5,T16,T166	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T44	Yes	T4,T6,T44	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T6,T44	Yes	T4,T6,T44	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T6,T44	Yes	T4,T6,T44	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T6,T44	Yes	T4,T6,T44	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T18,T178,T154	Yes	T18,T178,T154	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T178,T154	Yes	T18,T178,T154	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T4,T44,T45	Yes	T4,T6,T44	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T214,*T83,*T84	Yes	T214,T83,T84	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T4,*T44,*T45	Yes	T4,T6,T44	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T6,T44	Yes	T4,T6,T44	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T4,T123,T65	Yes	T4,T123,T65	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T4,T123,T65	Yes	T4,T123,T65	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T4,T123,T65	Yes	T4,T123,T65	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T4,T123,T65	Yes	T4,T123,T65	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T4,T123,T65	Yes	T4,T123,T65	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T123,T65	Yes	T4,T123,T65	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T4,T65,T68	Yes	T4,T123,T65	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T135	Yes	T83,T84,T85	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T4,*T123,*T65	Yes	T4,T123,T65	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T4,T123,T65	Yes	T4,T123,T65	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T192,T125,T193	Yes	T192,T125,T193	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T18,T55	Yes	T5,T56,T18	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T5,T18,T55	Yes	T5,T56,T18	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T214,*T83,*T84	Yes	T214,T83,T84	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T192,*T125,*T193	Yes	T192,T125,T193	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T5,T56,T18	Yes	T5,T56,T18	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T44	Yes	T4,T5,T44	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T44	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T44,T92	Yes	T4,T44,T92	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T4,T44,T45	Yes	T4,T44,T45	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T58,*T76,*T86	Yes	T58,T76,T86	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T45	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T45	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T4,T5,T45	Yes	T4,T5,T45	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T4,T5,T45	Yes	T4,T5,T45	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T45,T65	Yes	T4,T45,T65	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T45	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T45	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T83,*T84,*T85	Yes	T268,T427,T785	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T45	Yes	T4,T5,T45	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T4,T5,T45	Yes	T4,T5,T45	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T186,T68,T217	Yes	T186,T68,T217	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T186,T68,T217	Yes	T186,T68,T217	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T186,T68,T217	Yes	T186,T68,T217	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T186,T68,T217	Yes	T186,T68,T217	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T83,T84,T85	Yes	T84,T85,T87	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T186,T68,T217	Yes	T186,T68,T217	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T186,T68,T31	Yes	T186,T68,T31	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T186,T68,T217	Yes	T186,T68,T217	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T84,T85,T87	Yes	T83,T84,T85	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T214,*T84,*T85	Yes	T214,T83,T84	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T84,T85,T87	Yes	T83,T84,T85	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T186,*T68,*T31	Yes	T186,T68,T217	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T186,T68,T217	Yes	T186,T68,T217	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T115,T330,T3	Yes	T115,T330,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T115,T330,T3	Yes	T115,T330,T3	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T115,T330,T3	Yes	T115,T330,T3	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T115,T330,T3	Yes	T115,T330,T3	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T84,T85,T135	Yes	T84,T85,T135	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T330,T3,T7	Yes	T330,T3,T7	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T115,T330,T3	Yes	T115,T330,T3	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T115,T3,T7	Yes	T115,T330,T3	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T84,T85,T135	Yes	T84,T85,T135	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T135	Yes	T83,T84,T85	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T84,T85,T135	Yes	T84,T85,T135	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T115,*T330,*T3	Yes	T115,T330,T3	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T115,T330,T3	Yes	T115,T330,T3	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T58,*T75,*T76	Yes	T58,T75,T76	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T58,T76,T86	Yes	T58,T76,T86	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_ast_i.d_error	Yes	Yes	T84,T85,T134	Yes	T84,T85,T134	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T4,T5,T44	Yes	T4,T5,T6	INPUT
tl_ast_i.d_sink	Yes	Yes	T84,T85,T135	Yes	T83,T84,T85	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T135	Yes	T83,T84,T85	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T84,T85,T134	Yes	T84,T85,T134	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T83,*T84,*T85	Yes	T84,T85,T136	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range