Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	142042	1			T80	101		T81	272		T82	6
values[2]	8144	1			T80	1		T81	17		T88	1
values[3]	2926	1			T81	16		T510	1		T442	1
values[4]	1807	1			T81	18		T510	1		T442	1
values[5]	1240	1			T81	15		T510	1		T442	1
values[6]	989	1			T81	11		T510	1		T442	1
values[7]	677	1			T81	12		T510	1		T442	1
values[8]	549	1			T81	26		T510	1		T442	1
values[9]	491	1			T81	9		T510	1		T442	1
values[10]	450	1			T81	18		T510	1		T442	1
values[11]	338	1			T81	15		T510	1		T442	1
values[12]	331	1			T81	10		T510	1		T442	1
values[13]	318	1			T81	13		T510	1		T442	1
values[14]	291	1			T81	14		T510	1		T442	1
values[15]	318	1			T81	27		T510	1		T442	1
values[16]	288	1			T81	14		T510	1		T442	1
values[17]	272	1			T81	10		T510	1		T442	1
values[18]	265	1			T81	12		T510	1		T442	1
values[19]	309	1			T81	13		T510	1		T442	1
values[20]	338	1			T81	13		T510	1		T442	1
values[21]	296	1			T81	13		T510	1		T442	1
values[22]	273	1			T81	8		T510	1		T442	1
values[23]	234	1			T81	8		T510	1		T442	1
values[24]	256	1			T81	17		T510	1		T442	1
values[25]	248	1			T81	14		T510	1		T442	1
values[26]	281	1			T81	22		T510	1		T442	1
values[27]	331	1			T81	24		T510	1		T442	1
values[28]	312	1			T81	16		T510	1		T442	1
values[29]	268	1			T81	19		T510	1		T442	1
values[30]	283	1			T81	15		T510	1		T442	1
values[31]	281	1			T81	15		T510	1		T442	1
values[32]	279	1			T81	16		T510	1		T442	1
values[33]	353	1			T81	31		T510	1		T442	1
values[34]	241	1			T81	13		T510	1		T442	1
values[35]	264	1			T81	15		T510	1		T442	1
values[36]	276	1			T81	12		T510	1		T442	1
values[37]	224	1			T81	8		T510	1		T442	1
values[38]	264	1			T81	26		T510	1		T442	1
values[39]	231	1			T81	19		T510	1		T442	1
values[40]	265	1			T81	22		T510	1		T442	1
values[41]	273	1			T81	12		T510	1		T442	1
values[42]	315	1			T81	10		T510	1		T442	1
values[43]	270	1			T81	10		T510	1		T442	1
values[44]	298	1			T81	15		T510	1		T442	1
values[45]	272	1			T81	14		T510	2		T442	1
values[46]	221	1			T81	11		T510	1		T442	1
values[47]	239	1			T81	8		T510	1		T442	1
values[48]	210	1			T81	17		T510	1		T442	1
values[49]	236	1			T81	27		T510	1		T442	1
values[50]	230	1			T81	18		T510	1		T442	2
values[51]	224	1			T81	13		T510	1		T442	1
values[52]	209	1			T81	17		T510	1		T442	1
values[53]	205	1			T81	8		T510	1		T442	1
values[54]	190	1			T81	16		T510	1		T442	1
values[55]	199	1			T81	16		T510	1		T442	1
values[56]	207	1			T81	7		T510	1		T442	1
values[57]	221	1			T81	7		T510	1		T442	1
values[58]	198	1			T81	15		T510	1		T442	1
values[59]	187	1			T81	3		T510	1		T442	1
values[60]	164	1			T81	9		T510	1		T442	1
values[61]	117	1			T81	6		T510	1		T442	1
values[62]	153	1			T81	5		T510	2		T442	1
values[63]	140	1			T81	5		T510	1		T442	1
values[64]	172	1			T510	1		T442	1		T676	7
values[65]	140	1			T510	1		T442	1		T676	4
values[66]	100	1			T510	1		T442	1		T820	1
values[67]	109	1			T510	1		T442	1		T820	1
values[68]	64	1			T510	1		T442	1		T820	1
values[69]	68	1			T510	1		T442	1		T820	1
values[70]	102	1			T510	1		T442	1		T820	1
values[71]	71	1			T510	1		T442	1		T820	1
values[72]	43	1			T510	1		T442	1		T820	1
values[73]	44	1			T510	1		T442	1		T820	1
values[74]	46	1			T510	1		T442	1		T820	1
values[75]	56	1			T510	1		T442	1		T820	1
values[76]	52	1			T510	1		T442	1		T820	1
values[77]	52	1			T510	1		T442	1		T820	1
values[78]	53	1			T510	1		T442	2		T820	1
values[79]	34	1			T510	1		T442	1		T820	1
values[80]	46	1			T510	1		T442	1		T820	1
values[81]	51	1			T510	1		T442	1		T820	1
values[82]	42	1			T510	1		T442	1		T820	1
values[83]	50	1			T510	1		T442	1		T820	1
values[84]	66	1			T510	1		T442	1		T820	1
values[85]	48	1			T510	1		T442	1		T820	1
values[86]	53	1			T510	1		T442	1		T820	3
values[87]	89	1			T510	1		T442	1		T820	24
values[88]	56	1			T510	1		T442	1		T820	1
values[89]	66	1			T510	1		T442	1		T820	2
values[90]	59	1			T510	1		T442	1		T820	4
values[91]	60	1			T510	1		T442	1		T820	1
values[92]	70	1			T510	1		T442	1		T820	8
values[93]	59	1			T510	1		T442	1		T820	1
values[94]	59	1			T510	1		T442	1		T820	2
values[95]	72	1			T510	1		T442	1		T820	1
values[96]	58	1			T510	1		T442	1		T820	4
values[97]	48	1			T510	1		T442	1		T820	1
values[98]	66	1			T510	1		T442	1		T820	5
values[99]	62	1			T510	2		T442	1		T820	2
values[100]	46	1			T510	1		T442	1		T820	3
values[101]	47	1			T510	1		T442	1		T820	1
values[102]	60	1			T510	5		T442	1		T820	2
values[103]	66	1			T510	1		T442	1		T820	1
values[104]	65	1			T510	1		T442	1		T820	2
values[105]	43	1			T510	2		T442	1		T820	1
values[106]	67	1			T510	1		T442	1		T820	5
values[107]	54	1			T510	2		T442	1		T820	3
values[108]	52	1			T510	1		T442	1		T820	1
values[109]	45	1			T510	3		T442	1		T820	3
values[110]	64	1			T510	3		T442	1		T820	3
values[111]	59	1			T510	1		T442	1		T820	2
values[112]	60	1			T510	3		T442	1		T820	2
values[113]	41	1			T510	1		T442	1		T820	4
values[114]	54	1			T510	6		T442	2		T820	7
values[115]	61	1			T510	5		T442	4		T820	1
values[116]	47	1			T510	1		T442	2		T820	2
values[117]	56	1			T510	1		T442	3		T820	2
values[118]	51	1			T510	1		T442	1		T820	5
values[119]	59	1			T510	4		T442	2		T820	3
values[120]	54	1			T510	6		T442	5		T820	3
values[121]	62	1			T510	1		T442	3		T820	1
values[122]	61	1			T510	5		T442	1		T820	2
values[123]	51	1			T510	1		T442	1		T820	2
values[124]	47	1			T510	1		T442	3		T820	2
values[125]	48	1			T510	1		T442	1		T820	3
values[126]	76	1			T510	1		T442	1		T820	3
values[127]	775	1			T510	22		T442	31		T820	21
values[128]	6935	1			T510	282		T442	231		T820	264