Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.26	95.58	94.27	95.49		95.12	97.53	99.58

Total tests in report: 2900

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.62	39.62	44.82	44.82	42.89	42.89	32.47	32.47			57.90	57.90	59.27	59.27	0.38	0.38	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1103440611
48.50	8.88	52.09	7.27	51.95	9.05	35.20	2.73			65.96	8.06	85.14	25.87	0.66	0.28	/workspace/coverage/default/2.chip_jtag_csr_rw.3062048370
55.07	6.57	61.10	9.02	55.51	3.56	41.44	6.24			66.22	0.25	85.14	0.00	20.98	20.33	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1004886183
60.14	5.08	71.92	10.82	62.47	6.96	44.45	3.00			75.73	9.52	85.31	0.17	20.98	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.2565958833
64.36	4.22	71.92	0.00	63.00	0.54	44.45	0.00			75.96	0.23	85.31	0.00	45.53	24.54	/workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3557304780
67.55	3.19	77.14	5.22	67.01	4.00	48.16	3.71			77.78	1.83	89.69	4.37	45.53	0.00	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2446042993
70.31	2.76	77.14	0.00	67.28	0.28	48.16	0.01			77.78	0.00	89.69	0.00	61.83	16.30	/workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.4140996485
73.00	2.69	77.15	0.01	67.30	0.02	64.23	16.07			77.80	0.02	89.69	0.00	61.83	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.346567614
75.62	2.62	80.12	2.97	73.73	6.43	64.78	0.55			82.22	4.42	89.69	0.00	63.15	1.33	/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2399100139
77.37	1.75	82.21	2.09	76.35	2.62	68.41	3.63			84.06	1.84	90.03	0.35	63.15	0.00	/workspace/coverage/default/2.rom_e2e_smoke.2567638111
79.06	1.68	82.21	0.00	76.35	0.00	68.41	0.00			84.06	0.00	90.03	0.00	73.26	10.10	/workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.1998306231
80.43	1.37	84.36	2.15	77.44	1.09	71.65	3.24			84.75	0.69	91.08	1.05	73.26	0.00	/workspace/coverage/default/1.chip_sw_power_virus.1821527652
81.69	1.27	84.39	0.03	77.44	0.00	79.06	7.41			84.75	0.00	91.26	0.17	73.26	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.4158483080
82.87	1.17	84.39	0.00	77.44	0.00	79.06	0.00			84.75	0.00	91.26	0.00	80.30	7.04	/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.831802112
83.96	1.09	86.32	1.93	79.43	1.99	79.44	0.38			86.99	2.24	91.26	0.00	80.30	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1669532791
84.97	1.01	87.81	1.49	81.62	2.19	79.66	0.22			89.14	2.15	91.26	0.00	80.30	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.318824349
85.86	0.90	89.02	1.21	82.58	0.95	80.79	1.13			90.31	1.17	92.13	0.87	80.34	0.05	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4067723598
86.65	0.79	89.53	0.51	82.74	0.16	80.80	0.01			90.50	0.19	95.98	3.85	80.34	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2323289016
87.39	0.74	89.56	0.03	82.74	0.01	85.05	4.25			90.50	0.00	96.15	0.17	80.34	0.00	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.296446061
88.08	0.69	89.56	0.00	82.74	0.00	85.05	0.00			90.50	0.00	96.15	0.00	84.47	4.12	/workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.913249733
88.74	0.66	90.09	0.53	83.45	0.70	85.72	0.67			90.98	0.48	96.15	0.00	86.07	1.60	/workspace/coverage/default/2.chip_sw_alert_test.3066486090
89.36	0.62	90.09	0.00	83.45	0.00	85.72	0.00			90.98	0.00	96.15	0.00	89.79	3.72	/workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3471866211
89.98	0.61	91.26	1.17	84.43	0.98	86.13	0.41			92.10	1.12	96.15	0.00	89.79	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.4105132110
90.56	0.58	91.26	0.00	84.97	0.55	86.13	0.00			92.10	0.00	96.15	0.00	92.73	2.94	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.2939035626
91.12	0.56	91.27	0.01	87.90	2.93	86.13	0.00			92.10	0.00	96.15	0.00	93.14	0.41	/workspace/coverage/cover_reg_top/19.chip_tl_errors.673867628
91.66	0.54	92.50	1.22	88.76	0.85	86.56	0.44			92.84	0.74	96.15	0.00	93.14	0.00	/workspace/coverage/default/0.chip_sw_gpio_smoketest.2009506209
92.18	0.52	92.50	0.00	88.76	0.00	86.56	0.00			92.84	0.00	96.15	0.00	96.29	3.15	/workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1889699291
92.55	0.37	92.51	0.01	88.76	0.01	88.78	2.22			92.84	0.00	96.15	0.00	96.29	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.776295744
92.81	0.26	92.73	0.22	88.95	0.19	89.83	1.04			92.94	0.11	96.15	0.00	96.29	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.3785292061
93.03	0.22	92.90	0.18	89.07	0.12	90.75	0.92			93.05	0.11	96.15	0.00	96.29	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3970394523
93.19	0.16	93.21	0.31	89.33	0.26	90.83	0.08			93.36	0.32	96.15	0.00	96.29	0.00	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3427145554
93.35	0.15	93.21	0.00	89.42	0.10	90.83	0.00			93.37	0.01	96.15	0.00	97.10	0.81	/workspace/coverage/cover_reg_top/44.xbar_random_large_delays.408961038
93.50	0.15	93.21	0.00	89.53	0.11	90.83	0.00			93.38	0.01	96.15	0.00	97.87	0.78	/workspace/coverage/cover_reg_top/71.xbar_stress_all.1513379059
93.64	0.15	93.29	0.08	89.64	0.11	91.31	0.48			93.57	0.19	96.15	0.00	97.89	0.01	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.54760074
93.78	0.14	93.42	0.13	90.23	0.59	91.32	0.01			93.66	0.09	96.15	0.00	97.89	0.00	/workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.157421332
93.91	0.13	93.42	0.00	90.59	0.36	91.34	0.02			94.07	0.41	96.15	0.00	97.89	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3345821374
94.04	0.13	93.77	0.35	90.77	0.18	91.43	0.09			94.20	0.13	96.15	0.00	97.90	0.01	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3525493405
94.16	0.12	93.96	0.19	91.03	0.25	91.71	0.28			94.20	0.00	96.15	0.00	97.90	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.512845155
94.27	0.11	93.96	0.00	91.03	0.00	92.37	0.65			94.20	0.00	96.15	0.00	97.90	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2888406650
94.38	0.11	93.99	0.03	91.12	0.09	92.65	0.28			94.26	0.06	96.33	0.17	97.90	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2881519118
94.47	0.10	93.99	0.00	91.12	0.00	93.23	0.58			94.26	0.00	96.33	0.00	97.90	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.4188543942
94.57	0.10	93.99	0.00	91.70	0.58	93.23	0.00			94.26	0.00	96.33	0.00	97.90	0.00	/workspace/coverage/cover_reg_top/11.chip_tl_errors.2854489159
94.66	0.09	93.99	0.00	91.70	0.00	93.76	0.52			94.26	0.00	96.33	0.00	97.90	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3443043979
94.74	0.08	94.00	0.01	91.92	0.22	93.76	0.00			94.52	0.25	96.33	0.00	97.90	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.105834781
94.82	0.08	94.17	0.17	91.98	0.06	93.77	0.01			94.56	0.05	96.50	0.17	97.91	0.01	/workspace/coverage/default/45.chip_sw_all_escalation_resets.2287153256
94.87	0.06	94.28	0.11	92.08	0.10	93.82	0.05			94.66	0.10	96.50	0.00	97.91	0.00	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3719112025
94.93	0.05	94.28	0.00	92.12	0.05	93.82	0.00			94.68	0.02	96.50	0.00	98.17	0.26	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.178117417
94.98	0.05	94.41	0.12	92.19	0.07	93.92	0.11			94.68	0.00	96.50	0.00	98.17	0.00	/workspace/coverage/cover_reg_top/10.xbar_same_source.3936534745
95.03	0.05	94.46	0.05	92.20	0.01	93.97	0.05			94.69	0.01	96.68	0.17	98.17	0.00	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.2169043692
95.07	0.05	94.46	0.00	92.20	0.00	94.25	0.28			94.69	0.00	96.68	0.00	98.17	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2830766896
95.12	0.05	94.50	0.04	92.21	0.01	94.28	0.03			94.69	0.01	96.85	0.17	98.18	0.01	/workspace/coverage/default/94.chip_sw_all_escalation_resets.3770390800
95.16	0.04	94.51	0.01	92.27	0.06	94.29	0.01			94.70	0.01	97.03	0.17	98.18	0.00	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2771583277
95.21	0.04	94.56	0.05	92.28	0.01	94.48	0.19			94.71	0.01	97.03	0.00	98.18	0.00	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1612895260
95.25	0.04	94.56	0.00	92.52	0.24	94.48	0.00			94.71	0.00	97.03	0.00	98.18	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.3573529971
95.29	0.04	94.57	0.01	92.53	0.01	94.48	0.00			94.73	0.02	97.20	0.17	98.19	0.01	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1020981775
95.32	0.04	94.57	0.00	92.65	0.12	94.48	0.00			94.77	0.03	97.20	0.00	98.27	0.08	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2405834387
95.36	0.04	94.58	0.01	92.66	0.01	94.48	0.00			94.77	0.01	97.38	0.17	98.28	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1954206605
95.40	0.04	94.58	0.01	92.68	0.01	94.48	0.01			94.78	0.01	97.55	0.17	98.30	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.96851460
95.43	0.04	94.64	0.06	92.78	0.11	94.48	0.00			94.83	0.05	97.55	0.00	98.30	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1454638160
95.46	0.03	94.67	0.03	92.83	0.04	94.54	0.05			94.88	0.05	97.55	0.00	98.30	0.00	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1331989066
95.49	0.03	94.67	0.00	92.86	0.04	94.54	0.00			94.88	0.00	97.55	0.00	98.43	0.13	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2025375887
95.51	0.03	94.67	0.00	92.99	0.12	94.54	0.00			94.91	0.03	97.55	0.00	98.43	0.00	/workspace/coverage/cover_reg_top/42.xbar_access_same_device.2104406855
95.54	0.03	94.67	0.00	93.14	0.16	94.54	0.00			94.91	0.00	97.55	0.00	98.43	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.279301513
95.56	0.02	94.74	0.07	93.14	0.00	94.61	0.07			94.92	0.01	97.55	0.00	98.43	0.00	/workspace/coverage/default/2.chip_tap_straps_rma.160882122
95.59	0.02	94.78	0.04	93.16	0.01	94.67	0.07			94.94	0.02	97.55	0.00	98.43	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2037989727
95.61	0.02	94.84	0.07	93.21	0.05	94.67	0.00			94.95	0.02	97.55	0.00	98.43	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1795337075
95.63	0.02	94.90	0.06	93.25	0.05	94.67	0.00			94.98	0.02	97.55	0.00	98.43	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3130442868
95.65	0.02	94.90	0.00	93.25	0.00	94.80	0.13			94.98	0.00	97.55	0.00	98.43	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2218223623
95.67	0.02	94.90	0.00	93.25	0.00	94.92	0.12			94.98	0.00	97.55	0.00	98.43	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1977871828
95.69	0.02	94.90	0.00	93.37	0.11	94.92	0.00			94.98	0.00	97.55	0.00	98.43	0.00	/workspace/coverage/cover_reg_top/4.chip_tl_errors.1219035043
95.71	0.02	94.90	0.00	93.37	0.00	94.92	0.00			94.98	0.00	97.55	0.00	98.52	0.09	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.1450843580
95.72	0.02	94.91	0.01	93.41	0.04	94.93	0.01			95.00	0.02	97.55	0.00	98.52	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3846991142
95.74	0.01	94.92	0.01	93.44	0.03	94.96	0.03			95.02	0.02	97.55	0.00	98.52	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1343916525
95.75	0.01	94.93	0.01	93.46	0.02	94.99	0.03			95.03	0.01	97.55	0.00	98.53	0.01	/workspace/coverage/default/76.chip_sw_all_escalation_resets.1523223668
95.76	0.01	94.93	0.00	93.51	0.06	94.99	0.00			95.04	0.02	97.55	0.00	98.53	0.00	/workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3828586023
95.77	0.01	94.94	0.01	93.54	0.02	95.00	0.01			95.07	0.02	97.55	0.00	98.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.47382606
95.78	0.01	94.94	0.00	93.60	0.07	95.00	0.00			95.07	0.00	97.55	0.00	98.53	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.2758261469
95.79	0.01	94.94	0.00	93.62	0.01	95.00	0.00			95.07	0.00	97.55	0.00	98.58	0.05	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.1967375053
95.80	0.01	94.94	0.00	93.62	0.00	95.06	0.06			95.07	0.00	97.55	0.00	98.58	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.571203660
95.81	0.01	94.94	0.00	93.62	0.00	95.06	0.00			95.07	0.00	97.55	0.00	98.64	0.06	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.443064100
95.82	0.01	94.94	0.00	93.67	0.05	95.06	0.00			95.07	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.2849061365
95.83	0.01	94.94	0.00	93.71	0.04	95.06	0.00			95.07	0.00	97.55	0.00	98.65	0.01	/workspace/coverage/cover_reg_top/9.chip_tl_errors.3613210118
95.84	0.01	94.94	0.00	93.76	0.05	95.06	0.00			95.07	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.2280664260
95.85	0.01	94.94	0.00	93.80	0.04	95.06	0.00			95.07	0.00	97.55	0.00	98.66	0.01	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.469910908
95.85	0.01	94.96	0.02	93.80	0.01	95.07	0.01			95.08	0.02	97.55	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.868829426
95.86	0.01	94.98	0.02	93.81	0.01	95.07	0.01			95.10	0.02	97.55	0.00	98.66	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1022357113
95.87	0.01	94.98	0.00	93.86	0.05	95.07	0.00			95.10	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3366341620
95.88	0.01	94.98	0.00	93.86	0.00	95.11	0.05			95.10	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1561232642
95.88	0.01	94.98	0.00	93.86	0.00	95.16	0.04			95.10	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.932787905
95.89	0.01	94.98	0.00	93.86	0.00	95.20	0.04			95.10	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/0.rom_e2e_shutdown_output.3867921502
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96.11	0.01	94.99	0.00	94.13	0.00	95.40	0.00			95.12	0.00	97.55	0.00	99.49	0.01	/workspace/coverage/default/71.chip_sw_all_escalation_resets.2715952626
96.12	0.01	94.99	0.00	94.13	0.00	95.40	0.00			95.12	0.00	97.55	0.00	99.51	0.01	/workspace/coverage/default/73.chip_sw_all_escalation_resets.3877227024
96.12	0.01	94.99	0.00	94.13	0.00	95.40	0.00			95.12	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/75.chip_sw_all_escalation_resets.1228399906
96.12	0.01	94.99	0.00	94.13	0.00	95.40	0.00			95.12	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/78.chip_sw_all_escalation_resets.3140266539
96.12	0.01	94.99	0.00	94.13	0.00	95.40	0.00			95.12	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2860371819
96.12	0.01	94.99	0.00	94.13	0.00	95.40	0.00			95.12	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/79.chip_sw_all_escalation_resets.1400703558
96.13	0.01	94.99	0.00	94.13	0.00	95.40	0.00			95.12	0.00	97.55	0.00	99.57	0.01	/workspace/coverage/default/90.chip_sw_all_escalation_resets.3562752408
96.13	0.01	94.99	0.00	94.13	0.00	95.40	0.00			95.12	0.00	97.55	0.00	99.58	0.01	/workspace/coverage/default/95.chip_sw_all_escalation_resets.2740714426
96.13	0.01	94.99	0.00	94.14	0.01	95.40	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/1.chip_tl_errors.2820611436
96.13	0.01	94.99	0.00	94.15	0.01	95.40	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/18.chip_tl_errors.815222182
96.13	0.01	94.99	0.00	94.16	0.01	95.40	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2189987428
96.13	0.01	94.99	0.00	94.17	0.01	95.40	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.167124308
96.14	0.01	94.99	0.00	94.18	0.01	95.40	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx.970319957
96.14	0.01	94.99	0.00	94.19	0.01	95.40	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2389087273
96.14	0.01	94.99	0.00	94.20	0.01	95.40	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_gpio.2585496211
96.14	0.01	94.99	0.01	94.20	0.00	95.40	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/34.chip_sw_all_escalation_resets.2580651554
96.14	0.01	94.99	0.00	94.20	0.00	95.41	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.987456902
96.14	0.01	94.99	0.00	94.20	0.00	95.42	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3398752593
96.15	0.01	94.99	0.00	94.20	0.00	95.43	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1573571879
96.15	0.01	94.99	0.00	94.20	0.00	95.44	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_kmac_idle.1909866997
96.15	0.01	94.99	0.00	94.21	0.01	95.44	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.3442570432
96.15	0.01	94.99	0.00	94.22	0.01	95.44	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.476509742
96.15	0.01	94.99	0.00	94.23	0.01	95.44	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_gpio.700185334
96.15	0.01	94.99	0.00	94.23	0.01	95.44	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1233481871
96.15	0.01	94.99	0.00	94.23	0.00	95.45	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2464069166
96.15	0.01	94.99	0.00	94.23	0.00	95.46	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3211757773
96.16	0.01	95.00	0.01	94.23	0.00	95.46	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1258061918
96.16	0.01	95.00	0.00	94.23	0.00	95.46	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_aes_enc.2559596932
96.16	0.01	95.00	0.00	94.23	0.00	95.47	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.4138270095
96.16	0.01	95.00	0.00	94.23	0.00	95.47	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1895375088
96.16	0.01	95.00	0.00	94.24	0.01	95.47	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1038834828
96.16	0.01	95.00	0.00	94.24	0.01	95.47	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_rw.76194087
96.16	0.01	95.00	0.00	94.24	0.01	95.47	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.612181643
96.16	0.01	95.00	0.00	94.25	0.01	95.47	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.4037966684
96.16	0.01	95.00	0.00	94.25	0.01	95.47	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.821921012
96.16	0.01	95.00	0.00	94.25	0.01	95.47	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.834027933
96.16	0.01	95.00	0.00	94.26	0.01	95.47	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.1250332163
96.16	0.01	95.00	0.00	94.26	0.01	95.47	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/87.xbar_error_random.3794379953
96.16	0.01	95.00	0.00	94.26	0.01	95.47	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.3205908505
96.16	0.01	95.00	0.00	94.27	0.01	95.47	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3615900740
96.16	0.01	95.00	0.00	94.27	0.01	95.47	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.2032675233
96.16	0.01	95.00	0.00	94.27	0.00	95.48	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_tap_straps_rma.1933360986
96.17	0.01	95.00	0.00	94.27	0.00	95.48	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.344703005
96.17	0.01	95.00	0.01	94.27	0.00	95.48	0.00			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.3073041584
96.17	0.01	95.00	0.00	94.27	0.00	95.48	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.4095317804
96.17	0.01	95.00	0.00	94.27	0.00	95.48	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.734516801
96.17	0.01	95.00	0.00	94.27	0.00	95.49	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2087504505
96.17	0.01	95.00	0.00	94.27	0.00	95.49	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2050460524
96.17	0.01	95.00	0.00	94.27	0.00	95.49	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1690154143
96.17	0.01	95.00	0.00	94.27	0.00	95.49	0.01			95.12	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3887101476

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2557314142
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1021271236
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3305212857
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2647226941
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3225409504
/workspace/coverage/cover_reg_top/0.chip_tl_errors.3045081387
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2106719754
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2815989580
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.703575127
/workspace/coverage/cover_reg_top/0.xbar_error_random.279705980
/workspace/coverage/cover_reg_top/0.xbar_random.3756517362
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.484028859
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.4103074381
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1084924606
/workspace/coverage/cover_reg_top/0.xbar_same_source.2299289923
/workspace/coverage/cover_reg_top/0.xbar_smoke.3912309597
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.156558573
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1793765716
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1991138436
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1590838546
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1911842101
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3444931119
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3457147247
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.808581556
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1664620789
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3425826112
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.3900465649
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3012152847
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1801916746
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3586357438
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3673261897
/workspace/coverage/cover_reg_top/1.xbar_error_random.2362835901
/workspace/coverage/cover_reg_top/1.xbar_random.3477779880
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.4234845318
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3351465613
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3270542924
/workspace/coverage/cover_reg_top/1.xbar_same_source.4205648400
/workspace/coverage/cover_reg_top/1.xbar_smoke.1837260342
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3674177565
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2223088838
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.240634671
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3445509840
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1943870341
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1534957737
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3851574534
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.437413849
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.649411708
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3612260755
/workspace/coverage/cover_reg_top/10.xbar_error_random.2022916242
/workspace/coverage/cover_reg_top/10.xbar_random.1717818378
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.695081673
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2795223232
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.955955090
/workspace/coverage/cover_reg_top/10.xbar_smoke.2929560719
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1001052856
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1407846861
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1141391073
/workspace/coverage/cover_reg_top/10.xbar_stress_all.2894457237
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3510573336
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.645123758
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3774358767
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3040871568
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2737860266
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3370592565
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2782418277
/workspace/coverage/cover_reg_top/11.xbar_error_random.2860971383
/workspace/coverage/cover_reg_top/11.xbar_random.674198890
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3907223881
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3203027502
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3869184574
/workspace/coverage/cover_reg_top/11.xbar_same_source.2940966398
/workspace/coverage/cover_reg_top/11.xbar_smoke.1939730668
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1163460553
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.4086052929
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.4288264341
/workspace/coverage/cover_reg_top/11.xbar_stress_all.74116858
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3309659608
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2733865836
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.485689586
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.785925736
/workspace/coverage/cover_reg_top/12.chip_csr_rw.2706197060
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1369874350
/workspace/coverage/cover_reg_top/12.chip_tl_errors.830626098
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3510023345
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1015361280
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2136771032
/workspace/coverage/cover_reg_top/12.xbar_error_random.1365968343
/workspace/coverage/cover_reg_top/12.xbar_random.3910286099
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1506244480
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.381441077
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1037724278
/workspace/coverage/cover_reg_top/12.xbar_same_source.3216939211
/workspace/coverage/cover_reg_top/12.xbar_smoke.592441172
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1297217483
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1301526768
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2706315763
/workspace/coverage/cover_reg_top/12.xbar_stress_all.2830861012
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.4202899826
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3129584172
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3902602120
/workspace/coverage/cover_reg_top/13.chip_csr_rw.364939281
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3625074959
/workspace/coverage/cover_reg_top/13.chip_tl_errors.3144695898
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3144284183
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.832477663
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.237050831
/workspace/coverage/cover_reg_top/13.xbar_error_random.4025992625
/workspace/coverage/cover_reg_top/13.xbar_random.3228012558
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3099481757
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.4146963977
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.727217834
/workspace/coverage/cover_reg_top/13.xbar_same_source.3970269391
/workspace/coverage/cover_reg_top/13.xbar_smoke.1007802686
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.1692993009
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.289848444
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.103955010
/workspace/coverage/cover_reg_top/13.xbar_stress_all.3341417510
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3152853936
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.302694698
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2321975631
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2163620647
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/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.4022228259
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2274194262
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.159277309
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/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.689957909
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/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.995273579
/workspace/coverage/default/2.chip_sw_spi_device_tpm.3775192004
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2155704465
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/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3472621646
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1651284423
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.275551369
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2959066743
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3236830256
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/workspace/coverage/default/3.chip_sw_all_escalation_resets.1602137766
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.877171511
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/workspace/coverage/default/3.chip_sw_uart_tx_rx.1528031116
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/workspace/coverage/default/3.chip_tap_straps_dev.447344396
/workspace/coverage/default/3.chip_tap_straps_prod.3666161386
/workspace/coverage/default/3.chip_tap_straps_rma.2542215192
/workspace/coverage/default/3.chip_tap_straps_testunlock0.2389461298
/workspace/coverage/default/30.chip_sw_all_escalation_resets.224607360
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.555368939
/workspace/coverage/default/32.chip_sw_all_escalation_resets.3054461025
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1481698963
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.4016695297
/workspace/coverage/default/35.chip_sw_all_escalation_resets.3781414426
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2341192080
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1344169788
/workspace/coverage/default/37.chip_sw_all_escalation_resets.702801571
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.496676261
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.562159472
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2065390975
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2697285360
/workspace/coverage/default/4.chip_sw_all_escalation_resets.1084659853
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1763859169
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3252968004
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.435239748
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3976543701
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3382631406
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2915788273
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1230670613
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2889101840
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/workspace/coverage/default/4.chip_tap_straps_dev.2588416948
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/workspace/coverage/default/4.chip_tap_straps_rma.4049927454
/workspace/coverage/default/4.chip_tap_straps_testunlock0.173910424
/workspace/coverage/default/40.chip_sw_all_escalation_resets.959642455
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3511098697
/workspace/coverage/default/43.chip_sw_all_escalation_resets.4190559308
/workspace/coverage/default/44.chip_sw_all_escalation_resets.3394881124
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1870693195
/workspace/coverage/default/46.chip_sw_all_escalation_resets.2879904683
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3075727571
/workspace/coverage/default/49.chip_sw_all_escalation_resets.3991887099
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2157014780
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3091660822
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.4107701162
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2336057412
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3098280565
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2913176480
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3139591314
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1900487183
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1260726246
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.938189713
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1058655251
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3773261639
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1344684603
/workspace/coverage/default/56.chip_sw_all_escalation_resets.171466137
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2816471875
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3776970348
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1249676098
/workspace/coverage/default/58.chip_sw_all_escalation_resets.1258210077
/workspace/coverage/default/59.chip_sw_all_escalation_resets.4057445415
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3389124867
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2981972957
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3413768850
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.767947360
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1567535900
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2348023716
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.978957043
/workspace/coverage/default/63.chip_sw_all_escalation_resets.163168894
/workspace/coverage/default/64.chip_sw_all_escalation_resets.104702702
/workspace/coverage/default/65.chip_sw_all_escalation_resets.3358404826
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3735378268
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2130901050
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1383766526
/workspace/coverage/default/68.chip_sw_all_escalation_resets.263267262
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3839824454
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.4108148239
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3766161256
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.81411192
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.461244521
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.978612109
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3006635794
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2052563863
/workspace/coverage/default/72.chip_sw_all_escalation_resets.4002938821
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3860621825
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3634166454
/workspace/coverage/default/74.chip_sw_all_escalation_resets.796562187
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1248554342
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1284152304
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4014407002
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2939401023
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.202351278
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1050046218
/workspace/coverage/default/8.chip_sw_all_escalation_resets.787966577
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2550081157
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1443656058
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2407120447
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.776338487
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2775116587
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1194227988
/workspace/coverage/default/81.chip_sw_all_escalation_resets.1119650772
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.571787556
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1167243753
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3246563120
/workspace/coverage/default/83.chip_sw_all_escalation_resets.691065503
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.246212725
/workspace/coverage/default/84.chip_sw_all_escalation_resets.4020964842
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4216735307
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2218497189
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.223408131
/workspace/coverage/default/86.chip_sw_all_escalation_resets.222181266
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.522981711
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1979079952
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.692447333
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1505697534
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1938872859
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1197805132
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1481497597
/workspace/coverage/default/9.chip_sw_all_escalation_resets.754552186
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1140692184
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.76597775
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2946697642
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2041579898
/workspace/coverage/default/92.chip_sw_all_escalation_resets.904454997
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3846169519
/workspace/coverage/default/96.chip_sw_all_escalation_resets.502973619
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3500625905
/workspace/coverage/default/98.chip_sw_all_escalation_resets.924552334
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2961396729
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1500651540
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.911279007
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.230005850
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.66124641
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3784800572
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2214836179
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2868297251
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.4070666629

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Total test records in report: 2900

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3970394523			Jul 09 08:12:34 PM PDT 24	Jul 09 08:34:06 PM PDT 24	23246751880 ps
T5	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.889829738			Jul 09 07:54:52 PM PDT 24	Jul 09 10:58:50 PM PDT 24	59264520280 ps
T6	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1103440611			Jul 09 07:51:53 PM PDT 24	Jul 09 08:16:48 PM PDT 24	15458224914 ps
T95	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.1796179763			Jul 09 07:48:46 PM PDT 24	Jul 09 08:05:28 PM PDT 24	6571661180 ps
T20	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.296446061			Jul 09 07:58:58 PM PDT 24	Jul 09 08:07:53 PM PDT 24	6098681125 ps
T18	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3719112025			Jul 09 08:18:23 PM PDT 24	Jul 09 08:26:27 PM PDT 24	3397135560 ps
T96	/workspace/coverage/default/0.chip_sw_edn_auto_mode.155828693			Jul 09 07:53:04 PM PDT 24	Jul 09 08:10:38 PM PDT 24	4177074990 ps
T61	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1082396175			Jul 09 08:12:42 PM PDT 24	Jul 09 08:14:22 PM PDT 24	1969977318 ps
T19	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3525493405			Jul 09 08:30:47 PM PDT 24	Jul 09 08:38:48 PM PDT 24	4484203598 ps
T97	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.776295744			Jul 09 07:57:59 PM PDT 24	Jul 09 09:15:33 PM PDT 24	21045938656 ps
T21	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3868454531			Jul 09 07:58:55 PM PDT 24	Jul 09 08:09:22 PM PDT 24	9652766330 ps
T174	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2110279460			Jul 09 08:13:20 PM PDT 24	Jul 09 08:23:44 PM PDT 24	4822343196 ps
T30	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3561861875			Jul 09 07:53:41 PM PDT 24	Jul 09 08:02:56 PM PDT 24	5921878214 ps
T65	/workspace/coverage/default/76.chip_sw_all_escalation_resets.1523223668			Jul 09 08:22:51 PM PDT 24	Jul 09 08:34:33 PM PDT 24	5392677162 ps
T301	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2697285360			Jul 09 08:14:45 PM PDT 24	Jul 09 08:22:16 PM PDT 24	3389996954 ps
T302	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.692447333			Jul 09 08:32:28 PM PDT 24	Jul 09 08:38:19 PM PDT 24	3694483478 ps
T661	/workspace/coverage/default/0.chip_sw_aes_masking_off.980821167			Jul 09 07:50:18 PM PDT 24	Jul 09 07:54:05 PM PDT 24	3227473253 ps
T122	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.819813976			Jul 09 08:02:28 PM PDT 24	Jul 09 09:13:26 PM PDT 24	24943905944 ps
T59	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1612895260			Jul 09 08:12:11 PM PDT 24	Jul 09 08:31:12 PM PDT 24	9937348946 ps
T430	/workspace/coverage/default/2.chip_sw_kmac_smoketest.4263579451			Jul 09 08:17:30 PM PDT 24	Jul 09 08:23:55 PM PDT 24	3011173788 ps
T66	/workspace/coverage/default/48.chip_sw_all_escalation_resets.3693219903			Jul 09 08:20:15 PM PDT 24	Jul 09 08:30:06 PM PDT 24	5825999852 ps
T151	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3692852148			Jul 09 08:16:46 PM PDT 24	Jul 09 08:41:13 PM PDT 24	8000963062 ps
T60	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.54760074			Jul 09 07:51:35 PM PDT 24	Jul 09 08:00:52 PM PDT 24	4946375059 ps
T181	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3091660822			Jul 09 08:18:24 PM PDT 24	Jul 09 08:30:57 PM PDT 24	6408442488 ps
T153	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.144876174			Jul 09 08:01:24 PM PDT 24	Jul 09 08:21:41 PM PDT 24	7886629788 ps
T272	/workspace/coverage/default/2.chip_sw_hmac_oneshot.1624700225			Jul 09 08:14:49 PM PDT 24	Jul 09 08:19:48 PM PDT 24	3055040064 ps
T185	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.820731759			Jul 09 08:15:51 PM PDT 24	Jul 09 08:20:20 PM PDT 24	3027838038 ps
T273	/workspace/coverage/default/2.chip_sw_csrng_smoketest.1111008119			Jul 09 08:17:02 PM PDT 24	Jul 09 08:21:41 PM PDT 24	2461236126 ps
T182	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2881519118			Jul 09 08:00:34 PM PDT 24	Jul 09 08:13:39 PM PDT 24	5057419412 ps
T274	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3861741721			Jul 09 08:20:55 PM PDT 24	Jul 09 08:28:22 PM PDT 24	4097258152 ps
T240	/workspace/coverage/default/94.chip_sw_all_escalation_resets.3770390800			Jul 09 08:23:52 PM PDT 24	Jul 09 08:32:51 PM PDT 24	5643312608 ps
T252	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2214420172			Jul 09 08:13:12 PM PDT 24	Jul 09 08:46:22 PM PDT 24	23412576602 ps
T260	/workspace/coverage/default/8.chip_sw_all_escalation_resets.787966577			Jul 09 08:19:44 PM PDT 24	Jul 09 08:29:19 PM PDT 24	4695742276 ps
T261	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2533664847			Jul 09 08:03:28 PM PDT 24	Jul 09 08:07:06 PM PDT 24	2523278558 ps
T54	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.890316995			Jul 09 07:59:57 PM PDT 24	Jul 09 09:06:24 PM PDT 24	13591762166 ps
T159	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1135011245			Jul 09 08:20:24 PM PDT 24	Jul 09 08:29:55 PM PDT 24	4765817686 ps
T173	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.346567614			Jul 09 08:13:42 PM PDT 24	Jul 09 08:35:40 PM PDT 24	8505506436 ps
T57	/workspace/coverage/default/2.rom_e2e_smoke.2567638111			Jul 09 08:23:34 PM PDT 24	Jul 09 09:33:07 PM PDT 24	14670597624 ps
T164	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.588134336			Jul 09 07:56:33 PM PDT 24	Jul 09 07:58:25 PM PDT 24	2641173357 ps
T145	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.740989524			Jul 09 08:03:24 PM PDT 24	Jul 09 08:11:06 PM PDT 24	6022064880 ps
T354	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.462472736			Jul 09 08:14:52 PM PDT 24	Jul 09 08:22:17 PM PDT 24	6171283944 ps
T152	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1467268641			Jul 09 08:19:44 PM PDT 24	Jul 09 08:30:06 PM PDT 24	4837100942 ps
T158	/workspace/coverage/default/39.chip_sw_all_escalation_resets.2065390975			Jul 09 08:20:13 PM PDT 24	Jul 09 08:29:48 PM PDT 24	5300745924 ps
T355	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1590365954			Jul 09 07:57:47 PM PDT 24	Jul 09 08:00:39 PM PDT 24	2506180388 ps
T356	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.978612109			Jul 09 08:21:58 PM PDT 24	Jul 09 08:29:17 PM PDT 24	4332660680 ps
T1	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.255023867			Jul 09 08:03:23 PM PDT 24	Jul 09 08:12:21 PM PDT 24	6934636240 ps
T111	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.191012229			Jul 09 08:06:29 PM PDT 24	Jul 09 08:10:39 PM PDT 24	2447253630 ps
T112	/workspace/coverage/default/2.chip_sw_edn_auto_mode.3022110213			Jul 09 08:14:24 PM PDT 24	Jul 09 08:29:01 PM PDT 24	4350184984 ps
T113	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1481497597			Jul 09 08:15:27 PM PDT 24	Jul 09 08:21:50 PM PDT 24	3687562440 ps
T2	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4067723598			Jul 09 07:51:53 PM PDT 24	Jul 09 08:22:12 PM PDT 24	22114146060 ps
T114	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1331989066			Jul 09 08:18:29 PM PDT 24	Jul 09 08:26:45 PM PDT 24	3814130689 ps
T115	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.187095559			Jul 09 08:03:35 PM PDT 24	Jul 09 08:07:00 PM PDT 24	3124929884 ps
T116	/workspace/coverage/default/0.chip_sw_kmac_app_rom.2066714197			Jul 09 07:51:29 PM PDT 24	Jul 09 07:54:49 PM PDT 24	2601192614 ps
T117	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.271477885			Jul 09 07:54:49 PM PDT 24	Jul 09 08:03:49 PM PDT 24	3819887880 ps
T118	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.246212725			Jul 09 08:25:26 PM PDT 24	Jul 09 08:32:27 PM PDT 24	3335606442 ps
T219	/workspace/coverage/default/3.chip_sw_uart_tx_rx.1528031116			Jul 09 08:17:37 PM PDT 24	Jul 09 08:29:27 PM PDT 24	4145033704 ps
T866	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.337102349			Jul 09 07:53:02 PM PDT 24	Jul 09 08:00:16 PM PDT 24	3777855416 ps
T339	/workspace/coverage/default/68.chip_sw_all_escalation_resets.263267262			Jul 09 08:24:57 PM PDT 24	Jul 09 08:35:05 PM PDT 24	5807572062 ps
T58	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3031149832			Jul 09 07:59:50 PM PDT 24	Jul 09 09:14:09 PM PDT 24	18359280672 ps
T125	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3409630827			Jul 09 08:14:37 PM PDT 24	Jul 09 08:17:59 PM PDT 24	2057504852 ps
T707	/workspace/coverage/default/40.chip_sw_all_escalation_resets.959642455			Jul 09 08:26:42 PM PDT 24	Jul 09 08:37:25 PM PDT 24	5411289160 ps
T70	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1256608895			Jul 09 07:56:47 PM PDT 24	Jul 09 08:09:23 PM PDT 24	11311690431 ps
T160	/workspace/coverage/default/18.chip_sw_all_escalation_resets.1114560032			Jul 09 08:19:53 PM PDT 24	Jul 09 08:30:29 PM PDT 24	5089752106 ps
T55	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2214690978			Jul 09 07:57:22 PM PDT 24	Jul 09 08:59:21 PM PDT 24	13746625218 ps
T388	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1060897894			Jul 09 08:22:57 PM PDT 24	Jul 09 08:28:30 PM PDT 24	4398313210 ps
T62	/workspace/coverage/default/2.chip_sw_alert_test.3066486090			Jul 09 08:14:25 PM PDT 24	Jul 09 08:19:48 PM PDT 24	3021913720 ps
T123	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2931175687			Jul 09 08:15:07 PM PDT 24	Jul 09 09:26:31 PM PDT 24	18380671247 ps
T351	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3887101476			Jul 09 07:58:22 PM PDT 24	Jul 09 10:03:20 PM PDT 24	23373119744 ps
T28	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2889101840			Jul 09 08:16:43 PM PDT 24	Jul 09 08:44:26 PM PDT 24	13966726608 ps
T266	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1682694571			Jul 09 07:58:24 PM PDT 24	Jul 09 08:08:43 PM PDT 24	9759094353 ps
T431	/workspace/coverage/default/2.chip_sw_kmac_idle.1909866997			Jul 09 08:14:24 PM PDT 24	Jul 09 08:19:12 PM PDT 24	2871461686 ps
T867	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1763859169			Jul 09 08:13:36 PM PDT 24	Jul 09 08:22:29 PM PDT 24	6740409176 ps
T868	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1790785558			Jul 09 08:13:05 PM PDT 24	Jul 09 08:21:55 PM PDT 24	5227172410 ps
T214	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2732667976			Jul 09 07:55:20 PM PDT 24	Jul 09 08:06:48 PM PDT 24	4088904456 ps
T213	/workspace/coverage/default/26.chip_sw_all_escalation_resets.1416942882			Jul 09 08:19:17 PM PDT 24	Jul 09 08:30:04 PM PDT 24	4510707104 ps
T253	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2276232731			Jul 09 07:58:05 PM PDT 24	Jul 09 08:08:07 PM PDT 24	5263157368 ps
T155	/workspace/coverage/default/2.chip_plic_all_irqs_10.2565958833			Jul 09 08:16:15 PM PDT 24	Jul 09 08:26:59 PM PDT 24	3486248878 ps
T29	/workspace/coverage/default/0.chip_sw_gpio_smoketest.2009506209			Jul 09 07:57:11 PM PDT 24	Jul 09 08:02:20 PM PDT 24	3513171807 ps
T380	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3934865265			Jul 09 08:00:11 PM PDT 24	Jul 09 08:58:23 PM PDT 24	15285743048 ps
T709	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3511098697			Jul 09 08:27:26 PM PDT 24	Jul 09 08:32:47 PM PDT 24	4434910664 ps
T697	/workspace/coverage/default/2.chip_sw_hmac_multistream.2831058612			Jul 09 08:14:28 PM PDT 24	Jul 09 08:38:07 PM PDT 24	7572925234 ps
T869	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2141491464			Jul 09 08:14:31 PM PDT 24	Jul 09 08:19:32 PM PDT 24	3303045802 ps
T165	/workspace/coverage/default/0.rom_volatile_raw_unlock.1808656469			Jul 09 07:55:20 PM PDT 24	Jul 09 07:57:17 PM PDT 24	2959750632 ps
T89	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2081628618			Jul 09 08:18:43 PM PDT 24	Jul 09 08:27:06 PM PDT 24	3622770912 ps
T31	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2959066743			Jul 09 08:13:08 PM PDT 24	Jul 09 08:19:57 PM PDT 24	4163865050 ps
T103	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.4082181926			Jul 09 07:57:36 PM PDT 24	Jul 09 08:55:50 PM PDT 24	14832015270 ps
T71	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3077656894			Jul 09 07:51:15 PM PDT 24	Jul 09 07:58:56 PM PDT 24	5337359416 ps
T104	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1271975673			Jul 09 07:55:35 PM PDT 24	Jul 09 08:05:29 PM PDT 24	4584283540 ps
T105	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.2169043692			Jul 09 08:17:52 PM PDT 24	Jul 09 08:31:33 PM PDT 24	5732461514 ps
T106	/workspace/coverage/default/0.chip_sw_edn_kat.3468167161			Jul 09 07:52:11 PM PDT 24	Jul 09 08:04:32 PM PDT 24	2913889500 ps
T107	/workspace/coverage/default/0.chip_sw_rv_timer_irq.2071674385			Jul 09 07:49:22 PM PDT 24	Jul 09 07:54:35 PM PDT 24	3484616932 ps
T49	/workspace/coverage/default/0.chip_sw_spi_device_tpm.3468962872			Jul 09 07:53:07 PM PDT 24	Jul 09 07:58:59 PM PDT 24	2996865543 ps
T108	/workspace/coverage/default/97.chip_sw_all_escalation_resets.3500625905			Jul 09 08:24:48 PM PDT 24	Jul 09 08:36:06 PM PDT 24	6051084746 ps
T390	/workspace/coverage/default/66.chip_sw_all_escalation_resets.8949208			Jul 09 08:23:22 PM PDT 24	Jul 09 08:32:43 PM PDT 24	4415080374 ps
T223	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1751029667			Jul 09 07:55:38 PM PDT 24	Jul 09 08:13:51 PM PDT 24	7516203524 ps
T411	/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.1909202925			Jul 09 07:57:18 PM PDT 24	Jul 09 08:01:09 PM PDT 24	3254992715 ps
T870	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1831892553			Jul 09 08:16:00 PM PDT 24	Jul 09 08:23:28 PM PDT 24	3869108770 ps
T353	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.167124308			Jul 09 07:52:52 PM PDT 24	Jul 09 08:00:43 PM PDT 24	5404986932 ps
T239	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2087504505			Jul 09 07:53:22 PM PDT 24	Jul 09 08:19:22 PM PDT 24	6641614730 ps
T871	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.559812295			Jul 09 08:17:33 PM PDT 24	Jul 09 08:21:26 PM PDT 24	3426729544 ps
T299	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.257147462			Jul 09 08:19:51 PM PDT 24	Jul 09 08:26:21 PM PDT 24	3595941050 ps
T124	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3070275007			Jul 09 07:52:29 PM PDT 24	Jul 09 08:17:26 PM PDT 24	7878309096 ps
T872	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.591410641			Jul 09 07:57:54 PM PDT 24	Jul 09 08:06:22 PM PDT 24	6871255260 ps
T72	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3344864699			Jul 09 08:01:56 PM PDT 24	Jul 09 08:08:44 PM PDT 24	6061451208 ps
T695	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.496676261			Jul 09 08:20:32 PM PDT 24	Jul 09 08:28:14 PM PDT 24	4029456644 ps
T873	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.103896301			Jul 09 07:53:06 PM PDT 24	Jul 09 07:56:31 PM PDT 24	2993341094 ps
T874	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1677473568			Jul 09 07:55:01 PM PDT 24	Jul 09 08:26:47 PM PDT 24	16230384357 ps
T875	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3492308468			Jul 09 07:52:03 PM PDT 24	Jul 09 07:55:28 PM PDT 24	2813257638 ps
T876	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.597465161			Jul 09 07:58:40 PM PDT 24	Jul 09 08:41:40 PM PDT 24	29446480954 ps
T319	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3237898309			Jul 09 08:16:34 PM PDT 24	Jul 09 08:42:33 PM PDT 24	10396611009 ps
T129	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2406010966			Jul 09 07:59:54 PM PDT 24	Jul 09 08:12:05 PM PDT 24	5373032416 ps
T128	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1363629947			Jul 09 08:18:49 PM PDT 24	Jul 09 08:27:13 PM PDT 24	6377039039 ps
T877	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1244273483			Jul 09 07:54:43 PM PDT 24	Jul 09 08:03:40 PM PDT 24	4961153619 ps
T131	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.512845155			Jul 09 07:58:39 PM PDT 24	Jul 09 08:05:53 PM PDT 24	5704104342 ps
T664	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.80328284			Jul 09 08:16:18 PM PDT 24	Jul 09 09:52:34 PM PDT 24	26130859500 ps
T3	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.161213007			Jul 09 08:05:12 PM PDT 24	Jul 09 08:10:06 PM PDT 24	3784492994 ps
T392	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3457446402			Jul 09 08:18:21 PM PDT 24	Jul 09 08:24:15 PM PDT 24	3675182518 ps
T331	/workspace/coverage/default/64.chip_sw_all_escalation_resets.104702702			Jul 09 08:23:43 PM PDT 24	Jul 09 08:33:38 PM PDT 24	4775865008 ps
T393	/workspace/coverage/default/1.chip_sw_flash_crash_alert.912036580			Jul 09 08:01:56 PM PDT 24	Jul 09 08:14:17 PM PDT 24	6035717218 ps
T394	/workspace/coverage/default/1.chip_sw_edn_kat.2706952426			Jul 09 07:58:40 PM PDT 24	Jul 09 08:08:37 PM PDT 24	3014621620 ps
T251	/workspace/coverage/default/2.chip_sw_rv_timer_irq.983969231			Jul 09 08:13:01 PM PDT 24	Jul 09 08:16:56 PM PDT 24	2851164296 ps
T332	/workspace/coverage/default/79.chip_sw_all_escalation_resets.1400703558			Jul 09 08:23:08 PM PDT 24	Jul 09 08:32:06 PM PDT 24	6002683300 ps
T130	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1356733083			Jul 09 08:16:37 PM PDT 24	Jul 09 08:27:18 PM PDT 24	5255460980 ps
T316	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2169304914			Jul 09 07:49:05 PM PDT 24	Jul 09 07:59:23 PM PDT 24	3990633280 ps
T395	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2956159624			Jul 09 08:14:53 PM PDT 24	Jul 09 08:25:00 PM PDT 24	7184195140 ps
T175	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1443656058			Jul 09 08:15:52 PM PDT 24	Jul 09 08:30:27 PM PDT 24	10216875200 ps
T126	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2002837042			Jul 09 07:54:37 PM PDT 24	Jul 09 08:19:40 PM PDT 24	9610171390 ps
T321	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.47382606			Jul 09 07:51:14 PM PDT 24	Jul 09 08:41:59 PM PDT 24	26402925920 ps
T878	/workspace/coverage/default/0.chip_sw_example_flash.3209763774			Jul 09 07:52:40 PM PDT 24	Jul 09 07:56:44 PM PDT 24	2334595640 ps
T224	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2050460524			Jul 09 07:54:21 PM PDT 24	Jul 09 09:11:58 PM PDT 24	17670098290 ps
T90	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1348543554			Jul 09 08:13:49 PM PDT 24	Jul 09 08:20:42 PM PDT 24	3160462742 ps
T225	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.914204314			Jul 09 07:58:44 PM PDT 24	Jul 09 08:27:50 PM PDT 24	9166551848 ps
T220	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2407120447			Jul 09 08:15:37 PM PDT 24	Jul 09 09:00:48 PM PDT 24	13757611376 ps
T13	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1143849567			Jul 09 08:15:32 PM PDT 24	Jul 09 08:41:36 PM PDT 24	25772590714 ps
T171	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.4188543942			Jul 09 08:00:19 PM PDT 24	Jul 09 09:22:40 PM PDT 24	42441063888 ps
T167	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.4158483080			Jul 09 07:50:17 PM PDT 24	Jul 09 09:26:55 PM PDT 24	46352247240 ps
T83	/workspace/coverage/default/2.rom_raw_unlock.526577813			Jul 09 08:18:28 PM PDT 24	Jul 09 08:24:07 PM PDT 24	4929980654 ps
T879	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.459330409			Jul 09 08:00:28 PM PDT 24	Jul 09 09:03:30 PM PDT 24	15373920620 ps
T880	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3300918807			Jul 09 07:52:24 PM PDT 24	Jul 09 09:00:10 PM PDT 24	16851704608 ps
T216	/workspace/coverage/default/0.chip_sw_pattgen_ios.1199767758			Jul 09 07:48:14 PM PDT 24	Jul 09 07:52:34 PM PDT 24	2709470512 ps
T94	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3292587863			Jul 09 07:49:30 PM PDT 24	Jul 09 11:36:16 PM PDT 24	79519719882 ps
T698	/workspace/coverage/default/1.chip_sw_hmac_oneshot.2111545516			Jul 09 08:03:09 PM PDT 24	Jul 09 08:10:35 PM PDT 24	3150664024 ps
T268	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1750087075			Jul 09 07:50:16 PM PDT 24	Jul 09 08:02:50 PM PDT 24	5225273472 ps
T305	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.652723376			Jul 09 07:50:03 PM PDT 24	Jul 09 08:02:19 PM PDT 24	4631704334 ps
T221	/workspace/coverage/default/80.chip_sw_all_escalation_resets.2775116587			Jul 09 08:23:34 PM PDT 24	Jul 09 08:34:51 PM PDT 24	4535524860 ps
T742	/workspace/coverage/default/61.chip_sw_all_escalation_resets.2348023716			Jul 09 08:31:01 PM PDT 24	Jul 09 08:41:03 PM PDT 24	6078214232 ps
T217	/workspace/coverage/default/1.chip_sw_pattgen_ios.2032675233			Jul 09 07:53:25 PM PDT 24	Jul 09 07:59:09 PM PDT 24	2773200260 ps
T881	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2836770398			Jul 09 08:17:22 PM PDT 24	Jul 09 08:23:09 PM PDT 24	2530007304 ps
T127	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1279568084			Jul 09 08:16:28 PM PDT 24	Jul 09 08:47:37 PM PDT 24	12128723734 ps
T882	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3647644700			Jul 09 07:50:13 PM PDT 24	Jul 09 07:57:30 PM PDT 24	4456981608 ps
T32	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2233484233			Jul 09 07:57:20 PM PDT 24	Jul 09 09:07:55 PM PDT 24	20849177789 ps
T375	/workspace/coverage/default/2.chip_sw_edn_boot_mode.1910994976			Jul 09 08:15:00 PM PDT 24	Jul 09 08:23:34 PM PDT 24	2917027994 ps
T226	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2672723868			Jul 09 08:00:32 PM PDT 24	Jul 09 08:22:37 PM PDT 24	6947066792 ps
T883	/workspace/coverage/default/1.chip_sw_aes_entropy.1580795277			Jul 09 07:57:43 PM PDT 24	Jul 09 08:02:21 PM PDT 24	2844840114 ps
T884	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.4289039331			Jul 09 08:06:39 PM PDT 24	Jul 09 08:27:09 PM PDT 24	7208291866 ps
T215	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2389087273			Jul 09 07:49:21 PM PDT 24	Jul 09 08:00:30 PM PDT 24	4845808072 ps
T885	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2982930406			Jul 09 08:13:00 PM PDT 24	Jul 09 08:24:10 PM PDT 24	9094914764 ps
T98	/workspace/coverage/default/45.chip_sw_all_escalation_resets.2287153256			Jul 09 08:23:41 PM PDT 24	Jul 09 08:37:04 PM PDT 24	5847284756 ps
T886	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.76597775			Jul 09 08:21:07 PM PDT 24	Jul 09 08:36:58 PM PDT 24	10194964620 ps
T99	/workspace/coverage/default/49.chip_sw_all_escalation_resets.3991887099			Jul 09 08:20:50 PM PDT 24	Jul 09 08:32:36 PM PDT 24	4855373784 ps
T696	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3098280565			Jul 09 08:27:27 PM PDT 24	Jul 09 08:33:55 PM PDT 24	3595801656 ps
T710	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2816471875			Jul 09 08:20:39 PM PDT 24	Jul 09 08:27:49 PM PDT 24	3616967962 ps
T887	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2703344714			Jul 09 07:53:08 PM PDT 24	Jul 09 08:01:44 PM PDT 24	3152104504 ps
T888	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1468582334			Jul 09 08:13:07 PM PDT 24	Jul 09 08:23:21 PM PDT 24	5044045784 ps
T33	/workspace/coverage/default/0.chip_sw_usbdev_stream.3957490863			Jul 09 07:49:29 PM PDT 24	Jul 09 09:01:30 PM PDT 24	18881323312 ps
T738	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4216735307			Jul 09 08:23:06 PM PDT 24	Jul 09 08:30:06 PM PDT 24	4008738060 ps
T889	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1127596320			Jul 09 08:01:16 PM PDT 24	Jul 09 08:42:33 PM PDT 24	11909592664 ps
T758	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3735378268			Jul 09 08:23:11 PM PDT 24	Jul 09 08:29:56 PM PDT 24	3514655570 ps
T222	/workspace/coverage/default/83.chip_sw_all_escalation_resets.691065503			Jul 09 08:23:42 PM PDT 24	Jul 09 08:32:02 PM PDT 24	4864118228 ps
T340	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2978022187			Jul 09 08:05:36 PM PDT 24	Jul 09 08:19:36 PM PDT 24	5345375610 ps
T25	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.2300800889			Jul 09 08:04:06 PM PDT 24	Jul 09 08:16:47 PM PDT 24	6794998252 ps
T432	/workspace/coverage/default/0.chip_sw_kmac_entropy.980008704			Jul 09 07:55:23 PM PDT 24	Jul 09 08:00:56 PM PDT 24	3351302316 ps
T352	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2567289786			Jul 09 07:59:23 PM PDT 24	Jul 09 09:39:47 PM PDT 24	24071342072 ps
T76	/workspace/coverage/default/1.chip_tap_straps_prod.2137661049			Jul 09 08:00:28 PM PDT 24	Jul 09 08:14:25 PM PDT 24	6975599980 ps
T890	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3677860748			Jul 09 08:19:22 PM PDT 24	Jul 09 08:25:08 PM PDT 24	5317040200 ps
T172	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1573571879			Jul 09 07:54:12 PM PDT 24	Jul 09 09:25:19 PM PDT 24	50744211200 ps
T350	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1020981775			Jul 09 08:24:52 PM PDT 24	Jul 09 08:31:52 PM PDT 24	4076465400 ps
T325	/workspace/coverage/default/2.chip_sw_hmac_enc.2956101714			Jul 09 08:14:40 PM PDT 24	Jul 09 08:20:44 PM PDT 24	3356461168 ps
T227	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1266288370			Jul 09 07:53:45 PM PDT 24	Jul 09 08:32:53 PM PDT 24	9160448732 ps
T361	/workspace/coverage/default/56.chip_sw_all_escalation_resets.171466137			Jul 09 08:20:50 PM PDT 24	Jul 09 08:32:05 PM PDT 24	5074688076 ps
T109	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2662280462			Jul 09 08:00:44 PM PDT 24	Jul 09 08:25:37 PM PDT 24	25181362392 ps
T362	/workspace/coverage/default/2.rom_e2e_asm_init_prod.1540251995			Jul 09 08:20:49 PM PDT 24	Jul 09 09:37:48 PM PDT 24	15714526042 ps
T363	/workspace/coverage/default/9.chip_sw_all_escalation_resets.754552186			Jul 09 08:21:20 PM PDT 24	Jul 09 08:32:41 PM PDT 24	5985228408 ps
T168	/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.4024596454			Jul 09 08:00:07 PM PDT 24	Jul 09 08:07:31 PM PDT 24	5455714438 ps
T364	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2883335610			Jul 09 08:21:20 PM PDT 24	Jul 09 08:28:21 PM PDT 24	4201038108 ps
T189	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1067234517			Jul 09 07:51:21 PM PDT 24	Jul 09 07:59:49 PM PDT 24	4183897000 ps
T891	/workspace/coverage/default/2.chip_sw_example_manufacturer.2165124234			Jul 09 08:05:39 PM PDT 24	Jul 09 08:09:58 PM PDT 24	2890303784 ps
T892	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2186305164			Jul 09 08:02:09 PM PDT 24	Jul 09 08:06:23 PM PDT 24	3230491060 ps
T91	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.791361190			Jul 09 07:58:28 PM PDT 24	Jul 09 08:03:04 PM PDT 24	3033798865 ps
T713	/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.1066240538			Jul 09 08:15:32 PM PDT 24	Jul 09 08:37:35 PM PDT 24	7970633850 ps
T326	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.440925763			Jul 09 08:05:35 PM PDT 24	Jul 09 08:18:16 PM PDT 24	4106720044 ps
T84	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3613206282			Jul 09 07:55:32 PM PDT 24	Jul 09 08:03:33 PM PDT 24	3466739224 ps
T119	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2855865909			Jul 09 08:15:42 PM PDT 24	Jul 09 11:36:04 PM PDT 24	74578149253 ps
T322	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3846991142			Jul 09 07:55:47 PM PDT 24	Jul 09 08:08:45 PM PDT 24	5394727291 ps
T300	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2813287550			Jul 09 07:56:28 PM PDT 24	Jul 09 08:29:01 PM PDT 24	8526345596 ps
T893	/workspace/coverage/default/0.chip_sw_csrng_smoketest.3243224814			Jul 09 07:57:20 PM PDT 24	Jul 09 08:01:51 PM PDT 24	2932272538 ps
T894	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.310656807			Jul 09 08:16:37 PM PDT 24	Jul 09 08:23:10 PM PDT 24	4577102716 ps
T241	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2311855270			Jul 09 08:12:12 PM PDT 24	Jul 09 08:21:18 PM PDT 24	5443292600 ps
T895	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2780387737			Jul 09 08:13:59 PM PDT 24	Jul 09 08:45:57 PM PDT 24	12346126012 ps
T896	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1948228906			Jul 09 08:18:24 PM PDT 24	Jul 09 08:28:49 PM PDT 24	3700976408 ps
T897	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3267790638			Jul 09 08:03:22 PM PDT 24	Jul 09 08:12:24 PM PDT 24	3379795738 ps
T36	/workspace/coverage/default/1.chip_sw_gpio_smoketest.4224856378			Jul 09 08:06:21 PM PDT 24	Jul 09 08:10:08 PM PDT 24	2754534703 ps
T898	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1815748708			Jul 09 07:51:28 PM PDT 24	Jul 09 08:11:16 PM PDT 24	7522534732 ps
T899	/workspace/coverage/default/0.chip_sw_aes_entropy.1653125638			Jul 09 07:51:11 PM PDT 24	Jul 09 07:56:34 PM PDT 24	3207488872 ps
T56	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2487000885			Jul 09 08:00:28 PM PDT 24	Jul 09 09:16:01 PM PDT 24	18080419448 ps
T346	/workspace/coverage/default/2.chip_sival_flash_info_access.3606560507			Jul 09 08:04:21 PM PDT 24	Jul 09 08:09:42 PM PDT 24	3144096912 ps
T275	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1204719603			Jul 09 08:12:49 PM PDT 24	Jul 09 08:19:56 PM PDT 24	3541296400 ps
T900	/workspace/coverage/default/1.chip_sw_aes_idle.170627011			Jul 09 08:02:47 PM PDT 24	Jul 09 08:07:26 PM PDT 24	2658904056 ps
T777	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2713955636			Jul 09 08:21:33 PM PDT 24	Jul 09 08:27:32 PM PDT 24	3496779520 ps
T328	/workspace/coverage/default/1.chip_sw_uart_tx_rx.416063589			Jul 09 08:01:27 PM PDT 24	Jul 09 08:13:43 PM PDT 24	4700572528 ps
T733	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2535165693			Jul 09 08:21:39 PM PDT 24	Jul 09 08:28:33 PM PDT 24	4258647736 ps
T317	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1949840158			Jul 09 08:17:46 PM PDT 24	Jul 09 09:14:19 PM PDT 24	24899918450 ps
T92	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3894371822			Jul 09 07:56:49 PM PDT 24	Jul 09 10:59:13 PM PDT 24	255584411560 ps
T341	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1779499841			Jul 09 08:15:05 PM PDT 24	Jul 09 08:23:28 PM PDT 24	4033565384 ps
T901	/workspace/coverage/default/1.chip_sw_example_concurrency.2472807046			Jul 09 07:54:57 PM PDT 24	Jul 09 07:59:47 PM PDT 24	3004742484 ps
T902	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3024771057			Jul 09 08:01:12 PM PDT 24	Jul 09 08:04:49 PM PDT 24	3021345652 ps
T242	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.384183024			Jul 09 07:55:24 PM PDT 24	Jul 09 08:05:32 PM PDT 24	5359575344 ps
T344	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.612306204			Jul 09 08:00:00 PM PDT 24	Jul 09 08:56:21 PM PDT 24	31027124904 ps
T509	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3689990267			Jul 09 08:14:39 PM PDT 24	Jul 09 08:28:10 PM PDT 24	7645490704 ps
T683	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2001018841			Jul 09 08:14:19 PM PDT 24	Jul 09 08:19:03 PM PDT 24	3367522348 ps
T903	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.3120880956			Jul 09 08:01:45 PM PDT 24	Jul 09 08:04:37 PM PDT 24	2707087880 ps
T904	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3622398659			Jul 09 07:52:45 PM PDT 24	Jul 09 08:00:58 PM PDT 24	4366223632 ps
T508	/workspace/coverage/default/77.chip_sw_all_escalation_resets.2939401023			Jul 09 08:24:06 PM PDT 24	Jul 09 08:36:40 PM PDT 24	5677640724 ps
T905	/workspace/coverage/default/0.rom_keymgr_functest.1606518973			Jul 09 07:56:13 PM PDT 24	Jul 09 08:06:54 PM PDT 24	4979017060 ps
T906	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3362247926			Jul 09 07:54:47 PM PDT 24	Jul 09 08:25:13 PM PDT 24	8810479452 ps
T907	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.938069960			Jul 09 08:01:38 PM PDT 24	Jul 09 08:46:32 PM PDT 24	11400577288 ps
T26	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1631545782			Jul 09 07:54:33 PM PDT 24	Jul 09 07:59:30 PM PDT 24	3024858900 ps
T908	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3492060766			Jul 09 07:56:34 PM PDT 24	Jul 09 08:12:32 PM PDT 24	9253698250 ps
T744	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.391611427			Jul 09 08:25:54 PM PDT 24	Jul 09 08:32:50 PM PDT 24	3471465858 ps
T183	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.900183620			Jul 09 07:58:59 PM PDT 24	Jul 09 08:07:25 PM PDT 24	5245406366 ps
T780	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3839824454			Jul 09 08:23:17 PM PDT 24	Jul 09 08:29:03 PM PDT 24	3100050992 ps
T726	/workspace/coverage/default/3.chip_sw_all_escalation_resets.1602137766			Jul 09 08:17:21 PM PDT 24	Jul 09 08:28:11 PM PDT 24	6046150410 ps
T323	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2045574252			Jul 09 07:50:46 PM PDT 24	Jul 09 08:01:44 PM PDT 24	3389770424 ps
T719	/workspace/coverage/default/72.chip_sw_all_escalation_resets.4002938821			Jul 09 08:22:21 PM PDT 24	Jul 09 08:32:14 PM PDT 24	5074052236 ps
T909	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3860621825			Jul 09 08:22:51 PM PDT 24	Jul 09 08:29:27 PM PDT 24	3369732128 ps
T347	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1674708545			Jul 09 08:05:25 PM PDT 24	Jul 09 08:17:09 PM PDT 24	4259775062 ps
T910	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.817775244			Jul 09 08:13:55 PM PDT 24	Jul 09 09:18:18 PM PDT 24	17150127134 ps
T911	/workspace/coverage/default/4.chip_sw_uart_tx_rx.2915788273			Jul 09 08:16:25 PM PDT 24	Jul 09 08:29:41 PM PDT 24	4293688836 ps
T232	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.4014923537			Jul 09 07:59:19 PM PDT 24	Jul 09 09:36:29 PM PDT 24	46807271725 ps
T243	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2682279643			Jul 09 08:15:13 PM PDT 24	Jul 09 08:25:44 PM PDT 24	6151633546 ps
T684	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1740764456			Jul 09 07:49:20 PM PDT 24	Jul 09 07:53:11 PM PDT 24	2772803288 ps
T912	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2690771573			Jul 09 07:57:21 PM PDT 24	Jul 09 08:53:06 PM PDT 24	17607002274 ps
T913	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1719814316			Jul 09 08:19:00 PM PDT 24	Jul 09 08:23:00 PM PDT 24	3391359652 ps
T736	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.716016181			Jul 09 08:21:52 PM PDT 24	Jul 09 08:29:34 PM PDT 24	3875728330 ps
T73	/workspace/coverage/default/4.chip_tap_straps_testunlock0.173910424			Jul 09 08:16:21 PM PDT 24	Jul 09 08:18:55 PM PDT 24	2998106453 ps
T914	/workspace/coverage/default/0.chip_sw_aes_enc.2559596932			Jul 09 07:51:28 PM PDT 24	Jul 09 07:55:17 PM PDT 24	2454782894 ps
T915	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.633135119			Jul 09 08:06:43 PM PDT 24	Jul 09 08:14:02 PM PDT 24	4204946919 ps
T349	/workspace/coverage/default/2.chip_tap_straps_dev.1960880895			Jul 09 08:14:01 PM PDT 24	Jul 09 08:17:07 PM PDT 24	2807889159 ps
T186	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3398752593			Jul 09 07:51:00 PM PDT 24	Jul 09 08:03:41 PM PDT 24	8640085258 ps
T433	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.4066488261			Jul 09 08:15:57 PM PDT 24	Jul 09 08:32:42 PM PDT 24	6149969480 ps