Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	167032	1			T80	103		T81	783		T82	6
values[2]	5857	1			T435	2		T510	1		T248	1
values[3]	2826	1			T510	1		T516	60		T446	1
values[4]	1961	1			T510	1		T516	38		T446	1
values[5]	1422	1			T510	1		T516	10		T446	1
values[6]	1158	1			T510	1		T516	3		T446	1
values[7]	1011	1			T510	1		T516	9		T446	1
values[8]	842	1			T510	1		T516	12		T446	1
values[9]	675	1			T510	1		T516	8		T446	1
values[10]	598	1			T510	1		T516	9		T446	1
values[11]	551	1			T510	1		T516	3		T446	1
values[12]	525	1			T510	1		T446	1		T405	1
values[13]	421	1			T510	1		T446	1		T405	1
values[14]	441	1			T510	1		T446	1		T405	1
values[15]	367	1			T510	1		T446	1		T405	1
values[16]	345	1			T510	1		T446	1		T405	1
values[17]	281	1			T510	1		T446	1		T405	1
values[18]	242	1			T510	1		T446	1		T405	1
values[19]	252	1			T510	1		T446	1		T405	1
values[20]	226	1			T510	1		T446	1		T405	1
values[21]	204	1			T510	1		T446	1		T405	1
values[22]	196	1			T510	1		T446	1		T405	1
values[23]	211	1			T510	1		T446	1		T405	1
values[24]	182	1			T510	1		T446	1		T405	1
values[25]	181	1			T510	1		T446	1		T405	1
values[26]	183	1			T510	1		T446	1		T405	1
values[27]	126	1			T510	1		T446	1		T405	1
values[28]	145	1			T510	1		T446	1		T405	1
values[29]	138	1			T510	1		T446	1		T405	1
values[30]	116	1			T510	1		T446	1		T405	1
values[31]	139	1			T510	1		T446	1		T405	1
values[32]	134	1			T510	1		T446	1		T405	1
values[33]	152	1			T510	1		T446	1		T405	1
values[34]	145	1			T510	1		T446	1		T405	1
values[35]	117	1			T510	1		T446	1		T405	1
values[36]	102	1			T510	1		T446	1		T405	1
values[37]	81	1			T510	1		T446	1		T405	1
values[38]	59	1			T510	1		T446	1		T405	1
values[39]	47	1			T510	1		T446	1		T405	1
values[40]	57	1			T510	1		T446	1		T405	1
values[41]	53	1			T510	1		T446	1		T405	1
values[42]	59	1			T510	1		T446	1		T405	1
values[43]	50	1			T510	1		T446	1		T405	1
values[44]	57	1			T510	1		T446	1		T405	1
values[45]	59	1			T510	1		T446	1		T405	1
values[46]	61	1			T510	1		T446	1		T405	1
values[47]	62	1			T510	1		T446	1		T405	1
values[48]	50	1			T510	1		T446	1		T405	1
values[49]	66	1			T510	1		T446	1		T405	1
values[50]	65	1			T510	1		T446	1		T405	1
values[51]	69	1			T510	1		T446	1		T405	1
values[52]	78	1			T510	1		T446	1		T405	1
values[53]	66	1			T510	1		T446	1		T405	1
values[54]	74	1			T510	1		T446	1		T405	1
values[55]	75	1			T510	1		T446	1		T405	1
values[56]	62	1			T510	1		T446	1		T405	1
values[57]	65	1			T510	1		T446	1		T405	1
values[58]	59	1			T510	1		T446	1		T405	1
values[59]	44	1			T510	1		T446	1		T405	1
values[60]	42	1			T510	1		T446	1		T405	1
values[61]	57	1			T510	1		T446	1		T405	1
values[62]	55	1			T510	1		T446	1		T405	1
values[63]	57	1			T510	1		T446	1		T405	1
values[64]	47	1			T510	1		T446	1		T405	1
values[65]	44	1			T510	1		T446	1		T405	1
values[66]	52	1			T510	1		T446	1		T405	1
values[67]	53	1			T510	1		T446	1		T405	1
values[68]	46	1			T510	1		T446	1		T405	1
values[69]	39	1			T510	1		T446	1		T405	1
values[70]	49	1			T510	1		T446	1		T405	1
values[71]	46	1			T510	1		T446	1		T405	1
values[72]	47	1			T510	1		T446	1		T405	1
values[73]	49	1			T510	1		T446	1		T405	1
values[74]	41	1			T510	1		T446	1		T405	1
values[75]	50	1			T510	1		T446	1		T405	1
values[76]	46	1			T510	1		T446	1		T405	1
values[77]	50	1			T510	1		T446	1		T405	1
values[78]	49	1			T510	1		T446	1		T405	1
values[79]	59	1			T510	1		T446	1		T405	6
values[80]	65	1			T510	1		T446	1		T405	3
values[81]	57	1			T510	1		T446	1		T405	6
values[82]	45	1			T510	1		T446	1		T405	5
values[83]	47	1			T510	1		T446	1		T405	2
values[84]	62	1			T510	1		T446	1		T405	2
values[85]	63	1			T510	1		T446	1		T405	2
values[86]	52	1			T510	1		T446	1		T405	5
values[87]	53	1			T510	1		T446	1		T405	2
values[88]	63	1			T510	1		T446	1		T405	3
values[89]	69	1			T510	1		T446	1		T405	2
values[90]	62	1			T510	1		T446	1		T405	3
values[91]	63	1			T510	1		T446	1		T405	4
values[92]	63	1			T510	1		T446	2		T405	3
values[93]	75	1			T510	1		T446	1		T405	1
values[94]	70	1			T510	1		T446	1		T405	2
values[95]	86	1			T510	1		T446	1		T405	4
values[96]	85	1			T510	1		T446	1		T405	4
values[97]	98	1			T510	1		T446	1		T405	2
values[98]	64	1			T510	1		T446	1		T405	1
values[99]	65	1			T510	2		T446	1		T405	1
values[100]	86	1			T510	1		T446	1		T405	2
values[101]	82	1			T510	1		T446	1		T405	2
values[102]	86	1			T510	1		T446	1		T405	1
values[103]	82	1			T510	1		T446	1		T405	3
values[104]	73	1			T510	1		T446	1		T405	4
values[105]	88	1			T510	1		T446	1		T405	3
values[106]	78	1			T510	1		T446	1		T405	2
values[107]	84	1			T510	1		T446	1		T405	1
values[108]	81	1			T510	1		T446	1		T405	3
values[109]	87	1			T510	1		T446	4		T405	2
values[110]	98	1			T510	1		T446	5		T405	2
values[111]	95	1			T510	1		T446	2		T405	6
values[112]	86	1			T510	1		T446	1		T405	1
values[113]	78	1			T510	1		T446	1		T405	1
values[114]	84	1			T510	1		T446	5		T405	1
values[115]	83	1			T510	1		T446	2		T405	1
values[116]	78	1			T510	1		T446	4		T405	1
values[117]	85	1			T510	1		T446	4		T405	2
values[118]	78	1			T510	1		T446	2		T405	4
values[119]	81	1			T510	1		T446	4		T405	4
values[120]	89	1			T510	1		T446	2		T405	3
values[121]	105	1			T510	1		T446	1		T405	2
values[122]	89	1			T510	1		T446	2		T405	2
values[123]	116	1			T510	1		T446	4		T405	3
values[124]	183	1			T510	1		T446	3		T405	2
values[125]	316	1			T510	1		T446	2		T405	1
values[126]	735	1			T510	17		T446	33		T405	14
values[127]	2825	1			T510	190		T446	138		T405	91
values[128]	4545	1			T510	246		T446	178		T405	166