Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	466	1			T81	1		T396	3		T516	1
all_values[1]	466	1			T409	1		T396	2		T516	1
all_values[2]	452	1			T81	2		T510	1		T409	1
all_values[3]	466	1			T409	1		T396	3		T516	2
all_values[4]	428	1			T409	1		T396	2		T749	1
all_values[5]	449	1			T510	2		T406	1		T396	2
all_values[6]	461	1			T396	1		T446	1		T836	3
all_values[7]	453	1			T409	1		T406	1		T396	1
all_values[8]	454	1			T510	1		T409	2		T446	1
all_values[9]	467	1			T510	1		T836	3		T467	1
all_values[10]	478	1			T81	1		T510	1		T406	1
all_values[11]	424	1			T396	2		T516	1		T836	2
all_values[12]	444	1			T396	4		T446	1		T836	2
all_values[13]	451	1			T396	1		T516	1		T511	1
all_values[14]	429	1			T409	1		T396	2		T516	1
all_values[15]	478	1			T510	1		T409	1		T396	4
all_values[16]	462	1			T396	1		T446	1		T836	5
all_values[17]	418	1			T81	1		T396	2		T749	1
all_values[18]	436	1			T406	1		T396	2		T446	1
all_values[19]	415	1			T510	2		T396	1		T446	1
all_values[20]	465	1			T81	1		T396	6		T516	1
all_values[21]	478	1			T81	1		T510	1		T434	1
all_values[22]	440	1			T396	4		T836	1		T712	1
all_values[23]	436	1			T81	1		T396	2		T749	1
all_values[24]	422	1			T836	1		T442	1		T447	1
all_values[25]	474	1			T81	1		T409	2		T396	3
all_values[26]	459	1			T396	3		T408	1		T446	1
all_values[27]	421	1			T396	3		T672	1		T810	1
all_values[28]	445	1			T434	1		T396	2		T749	3
all_values[29]	442	1			T396	1		T408	2		T749	1
all_values[30]	447	1			T81	1		T409	1		T396	3
all_values[31]	468	1			T510	2		T396	5		T836	2
all_values[32]	471	1			T81	1		T510	1		T406	1
all_values[33]	446	1			T396	5		T446	1		T405	1
all_values[34]	445	1			T81	2		T510	1		T396	1
all_values[35]	445	1			T409	1		T406	1		T396	1
all_values[36]	459	1			T81	1		T396	3		T836	1
all_values[37]	461	1			T406	1		T396	2		T836	4
all_values[38]	449	1			T409	1		T408	1		T446	1
all_values[39]	418	1			T81	1		T510	1		T396	2
all_values[40]	426	1			T409	1		T516	1		T836	2
all_values[41]	440	1			T406	1		T405	1		T836	2
all_values[42]	453	1			T409	1		T442	1		T814	2
all_values[43]	443	1			T396	1		T516	1		T511	1
all_values[44]	463	1			T406	1		T396	2		T749	1
all_values[45]	432	1			T409	1		T396	1		T516	1
all_values[46]	452	1			T510	1		T516	1		T408	1
all_values[47]	460	1			T409	2		T406	1		T396	1
all_values[48]	489	1			T81	1		T396	2		T405	1
all_values[49]	448	1			T81	1		T396	3		T516	1