Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3500	1			T80	3		T81	2		T419	2
all_values[1]	3445	1			T80	4		T419	4		T406	3
all_values[2]	3450	1			T80	4		T81	1		T419	5
all_values[3]	3422	1			T80	7		T81	5		T419	1
all_values[4]	3397	1			T80	3		T81	4		T419	2
all_values[5]	3382	1			T80	1		T81	1		T406	2
all_values[6]	3410	1			T80	2		T81	4		T419	1
all_values[7]	3417	1			T80	1		T81	2		T419	2
all_values[8]	3451	1			T80	3		T81	2		T419	4
all_values[9]	3448	1			T80	3		T81	2		T419	1
all_values[10]	3456	1			T80	2		T81	3		T419	1
all_values[11]	3475	1			T80	1		T81	2		T419	1
all_values[12]	3428	1			T80	5		T81	2		T406	5
all_values[13]	3348	1			T80	7		T81	2		T419	1
all_values[14]	3516	1			T80	2		T81	3		T419	2
all_values[15]	3370	1			T80	5		T81	3		T419	3
all_values[16]	3554	1			T80	1		T81	3		T419	3
all_values[17]	3511	1			T80	1		T81	2		T419	3
all_values[18]	3350	1			T80	1		T81	3		T419	1
all_values[19]	3465	1			T80	2		T81	5		T419	2
all_values[20]	3516	1			T81	1		T419	1		T406	5
all_values[21]	3411	1			T80	2		T81	4		T419	1
all_values[22]	3485	1			T80	1		T81	4		T419	4
all_values[23]	3538	1			T80	4		T81	2		T419	3
all_values[24]	3413	1			T80	2		T81	2		T419	6
all_values[25]	3484	1			T80	4		T81	3		T419	2
all_values[26]	3466	1			T80	1		T81	4		T419	4
all_values[27]	3468	1			T80	4		T81	3		T419	3
all_values[28]	3433	1			T80	4		T81	3		T419	1
all_values[29]	3530	1			T80	3		T81	3		T419	1
all_values[30]	3339	1			T80	3		T419	3		T406	5
all_values[31]	3464	1			T80	4		T81	2		T419	3
all_values[32]	3531	1			T80	4		T81	2		T419	2
all_values[33]	3465	1			T80	3		T81	3		T419	1
all_values[34]	3411	1			T80	3		T81	3		T419	3
all_values[35]	3400	1			T80	3		T81	2		T419	3
all_values[36]	3464	1			T80	1		T81	2		T419	1
all_values[37]	3428	1			T80	3		T81	2		T419	2
all_values[38]	3461	1			T80	4		T81	6		T419	2
all_values[39]	3362	1			T80	3		T81	2		T419	2
all_values[40]	3378	1			T80	2		T81	3		T419	1
all_values[41]	3366	1			T80	2		T81	2		T419	2
all_values[42]	3433	1			T80	2		T81	2		T419	4
all_values[43]	3495	1			T80	5		T81	6		T419	1
all_values[44]	3418	1			T80	3		T81	5		T419	2
all_values[45]	3485	1			T80	3		T81	1		T419	3
all_values[46]	3432	1			T80	3		T81	4		T419	2
all_values[47]	3401	1			T80	3		T81	3		T419	4
all_values[48]	3440	1			T80	3		T81	5		T419	2
all_values[49]	3515	1			T80	4		T81	1		T419	4
all_values[50]	3451	1			T80	4		T81	2		T419	5
all_values[51]	3496	1			T80	2		T81	5		T419	3
all_values[52]	3475	1			T80	3		T81	4		T406	2
all_values[53]	3401	1			T80	5		T81	2		T419	3
all_values[54]	3328	1			T80	3		T81	1		T419	1
all_values[55]	3427	1			T80	5		T81	1		T419	3
all_values[56]	3509	1			T80	2		T81	1		T419	2
all_values[57]	3466	1			T80	10		T81	1		T419	1
all_values[58]	3389	1			T80	6		T81	2		T419	5
all_values[59]	3485	1			T80	3		T81	2		T419	2
all_values[60]	3442	1			T80	1		T81	1		T419	2
all_values[61]	3505	1			T80	2		T81	1		T419	2
all_values[62]	3427	1			T80	3		T81	1		T419	1
all_values[63]	3548	1			T80	3		T81	4		T419	1