Go back

 LINE       17998
 EXPRESSION (addr_hit[198] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T18,T19
1	0	1	Covered	T86,T149,T357
1	1	0	Covered	T527,T535,T533
1	1	1	Covered	T6,T18,T19

 LINE       18001
 EXPRESSION (addr_hit[199] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T18,T19
1	0	1	Covered	T6,T18,T19
1	1	0	Not Covered
1	1	1	Covered	T6,T18,T19

 LINE       18002
 EXPRESSION (addr_hit[199] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T18,T19
1	0	1	Covered	T6,T18,T19
1	1	0	Covered	T527,T647,T686
1	1	1	Covered	T6,T18,T19

 LINE       18005
 EXPRESSION (addr_hit[200] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T18,T19
1	0	1	Covered	T86,T693,T694
1	1	0	Covered	T525,T535,T533
1	1	1	Covered	T249,T250,T86

 LINE       18008
 EXPRESSION (addr_hit[201] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T18,T19
1	0	1	Covered	T86,T149,T357
1	1	0	Covered	T535,T533,T607
1	1	1	Covered	T62,T86,T63