Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	152364	1			T72	63		T77	6		T79	5
values[2]	4297	1			T78	2		T287	2		T230	1
values[3]	2087	1			T422	1		T739	1		T423	78
values[4]	1387	1			T422	1		T739	2		T423	56
values[5]	1091	1			T422	1		T739	3		T423	34
values[6]	975	1			T422	1		T739	3		T423	16
values[7]	882	1			T422	1		T739	1		T423	7
values[8]	671	1			T422	1		T739	1		T423	9
values[9]	502	1			T422	1		T739	3		T423	13
values[10]	473	1			T422	1		T739	7		T423	35
values[11]	424	1			T422	1		T739	3		T423	40
values[12]	422	1			T422	1		T739	3		T423	22
values[13]	380	1			T422	1		T739	2		T423	14
values[14]	380	1			T422	1		T739	2		T423	7
values[15]	322	1			T422	1		T739	2		T423	15
values[16]	254	1			T422	1		T739	1		T423	24
values[17]	246	1			T422	1		T739	2		T423	7
values[18]	306	1			T422	1		T739	1		T423	2
values[19]	271	1			T422	1		T739	3		T810	1
values[20]	225	1			T422	1		T739	1		T810	4
values[21]	177	1			T422	1		T739	1		T810	2
values[22]	186	1			T422	1		T739	2		T810	2
values[23]	174	1			T422	1		T739	1		T810	3
values[24]	222	1			T422	1		T739	4		T810	3
values[25]	187	1			T422	1		T739	3		T810	1
values[26]	157	1			T422	1		T739	3		T810	3
values[27]	136	1			T422	1		T739	3		T810	1
values[28]	134	1			T422	1		T739	1		T810	2
values[29]	144	1			T422	1		T739	1		T810	4
values[30]	155	1			T422	1		T739	5		T810	2
values[31]	165	1			T422	1		T739	3		T810	2
values[32]	128	1			T422	1		T739	2		T810	3
values[33]	117	1			T422	1		T739	5		T810	2
values[34]	87	1			T422	1		T739	2		T810	3
values[35]	83	1			T422	1		T739	1		T810	3
values[36]	79	1			T422	1		T739	2		T810	4
values[37]	84	1			T422	1		T739	1		T810	2
values[38]	95	1			T422	1		T739	2		T810	5
values[39]	83	1			T422	1		T739	2		T810	5
values[40]	58	1			T422	1		T739	2		T810	2
values[41]	61	1			T422	1		T739	2		T810	3
values[42]	64	1			T422	1		T739	2		T810	2
values[43]	65	1			T422	1		T739	2		T810	1
values[44]	54	1			T422	1		T739	1		T810	1
values[45]	64	1			T422	1		T739	2		T810	4
values[46]	54	1			T422	1		T739	4		T810	1
values[47]	87	1			T422	1		T739	3		T810	9
values[48]	79	1			T422	1		T739	2		T810	5
values[49]	84	1			T422	1		T739	1		T810	7
values[50]	55	1			T422	1		T739	2		T810	4
values[51]	53	1			T422	1		T739	3		T810	2
values[52]	65	1			T422	1		T739	1		T810	4
values[53]	83	1			T422	1		T739	1		T810	2
values[54]	78	1			T422	1		T739	3		T810	7
values[55]	58	1			T422	1		T739	2		T810	2
values[56]	47	1			T422	1		T739	2		T810	4
values[57]	48	1			T422	1		T739	2		T810	4
values[58]	52	1			T422	1		T739	3		T810	3
values[59]	45	1			T422	1		T739	1		T810	1
values[60]	44	1			T422	1		T739	2		T810	2
values[61]	55	1			T422	1		T739	1		T810	3
values[62]	51	1			T422	1		T739	1		T810	3
values[63]	48	1			T422	1		T739	1		T810	7
values[64]	51	1			T422	1		T739	4		T810	6
values[65]	43	1			T422	1		T739	1		T810	4
values[66]	45	1			T422	1		T739	1		T810	4
values[67]	48	1			T422	1		T739	1		T810	2
values[68]	47	1			T422	1		T739	4		T810	3
values[69]	40	1			T422	1		T739	1		T810	1
values[70]	45	1			T422	1		T739	4		T810	1
values[71]	47	1			T422	1		T739	2		T810	2
values[72]	50	1			T422	1		T739	2		T810	3
values[73]	37	1			T422	1		T739	1		T810	1
values[74]	46	1			T422	1		T739	1		T810	1
values[75]	45	1			T422	1		T739	3		T810	1
values[76]	57	1			T422	1		T739	4		T810	3
values[77]	55	1			T422	1		T739	2		T810	4
values[78]	56	1			T422	1		T739	2		T810	1
values[79]	64	1			T422	1		T739	1		T810	1
values[80]	48	1			T422	1		T739	3		T810	3
values[81]	65	1			T422	1		T739	2		T810	7
values[82]	59	1			T422	1		T739	3		T810	2
values[83]	66	1			T422	1		T739	4		T810	4
values[84]	56	1			T422	1		T739	2		T810	2
values[85]	68	1			T422	1		T739	3		T810	5
values[86]	74	1			T422	1		T739	2		T810	7
values[87]	73	1			T422	1		T739	2		T810	7
values[88]	60	1			T422	2		T739	2		T810	5
values[89]	77	1			T422	1		T739	2		T810	2
values[90]	63	1			T422	1		T739	4		T810	2
values[91]	51	1			T422	1		T739	1		T810	2
values[92]	52	1			T422	1		T739	2		T810	2
values[93]	52	1			T422	1		T739	2		T810	2
values[94]	70	1			T422	1		T739	1		T810	3
values[95]	69	1			T422	1		T739	3		T810	7
values[96]	47	1			T422	1		T739	1		T810	4
values[97]	66	1			T422	1		T739	2		T810	8
values[98]	59	1			T422	1		T739	7		T810	2
values[99]	63	1			T422	1		T739	4		T810	3
values[100]	87	1			T422	1		T739	3		T810	10
values[101]	65	1			T422	1		T739	3		T810	3
values[102]	68	1			T422	1		T739	2		T810	3
values[103]	74	1			T422	1		T739	1		T810	4
values[104]	72	1			T422	1		T739	2		T810	8
values[105]	79	1			T422	1		T739	5		T810	10
values[106]	89	1			T422	1		T739	5		T810	8
values[107]	80	1			T422	1		T739	4		T810	2
values[108]	75	1			T422	1		T739	1		T810	2
values[109]	70	1			T422	1		T739	6		T810	3
values[110]	76	1			T422	1		T739	4		T810	7
values[111]	77	1			T422	1		T739	2		T810	10
values[112]	82	1			T422	1		T739	3		T810	9
values[113]	88	1			T422	1		T739	2		T810	4
values[114]	90	1			T422	1		T739	1		T810	5
values[115]	82	1			T422	1		T739	3		T810	4
values[116]	72	1			T422	1		T739	3		T810	7
values[117]	88	1			T422	1		T739	7		T810	9
values[118]	94	1			T422	1		T739	2		T810	5
values[119]	93	1			T422	1		T739	2		T810	5
values[120]	91	1			T422	2		T739	5		T810	5
values[121]	110	1			T422	2		T739	7		T810	9
values[122]	91	1			T422	4		T739	3		T810	9
values[123]	105	1			T422	4		T739	5		T810	2
values[124]	176	1			T422	1		T739	16		T810	15
values[125]	388	1			T422	1		T739	75		T810	22
values[126]	734	1			T422	10		T739	91		T810	20
values[127]	2156	1			T422	102		T739	48		T810	11
values[128]	3683	1			T422	222		T739	4		T814	8