Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.14	95.59	94.04	95.50		94.82	97.35	99.53

Total tests in report: 2903

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
41.89	41.89	54.41	54.41	48.72	48.72	23.15	23.15			66.34	66.34	58.57	58.57	0.13	0.13	/workspace/coverage/default/0.chip_sw_plic_sw_irq.851022066
52.83	10.94	64.93	10.51	60.15	11.43	30.36	7.21			75.88	9.54	85.14	26.57	0.53	0.40	/workspace/coverage/default/2.chip_jtag_csr_rw.3306540850
60.62	7.79	73.93	9.00	61.78	1.63	33.32	2.96			76.02	0.15	85.14	0.00	33.51	32.98	/workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.3706132947
64.61	4.00	74.02	0.09	64.72	2.93	33.96	0.64			76.47	0.45	85.14	0.00	53.38	19.87	/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2703791266
68.02	3.40	79.90	5.88	68.98	4.27	37.88	3.92			78.46	1.99	89.51	4.37	53.38	0.00	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1995261609
71.16	3.14	80.21	0.31	69.19	0.20	55.42	17.54			78.68	0.22	90.03	0.52	53.44	0.06	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1167569415
73.78	2.62	80.21	0.00	69.19	0.00	71.10	15.68			78.68	0.00	90.03	0.00	53.48	0.05	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1561120286
76.31	2.52	82.58	2.37	74.87	5.68	72.48	1.38			83.89	5.22	90.03	0.00	53.98	0.49	/workspace/coverage/default/1.chip_jtag_csr_rw.2290299270
78.23	1.92	82.58	0.00	75.02	0.16	72.48	0.00			83.91	0.02	90.03	0.00	65.32	11.34	/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.274658828
79.78	1.56	84.50	1.91	76.54	1.51	77.01	4.53			84.95	1.04	90.38	0.35	65.32	0.00	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2543183596
81.34	1.55	85.31	0.82	76.77	0.23	79.41	2.40			84.99	0.04	90.38	0.00	71.15	5.84	/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.592256017
82.77	1.43	87.67	2.36	78.79	2.02	81.27	1.86			87.33	2.34	90.38	0.00	71.15	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3748765624
84.12	1.36	87.67	0.00	78.80	0.01	81.27	0.00			87.33	0.00	90.38	0.00	79.30	8.14	/workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.949152087
85.26	1.14	89.06	1.39	81.02	2.22	81.54	0.27			89.58	2.26	91.08	0.70	79.30	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.37558959
86.20	0.93	90.37	1.31	82.17	1.15	83.37	1.83			90.90	1.31	91.08	0.00	79.30	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.1043319285
86.93	0.73	90.67	0.29	82.26	0.09	83.38	0.01			91.03	0.13	94.93	3.85	79.30	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3035382782
87.65	0.72	90.67	0.00	82.38	0.12	83.38	0.00			91.04	0.02	94.93	0.00	83.47	4.17	/workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1741073834
88.32	0.68	91.25	0.58	84.49	2.11	83.65	0.27			91.45	0.41	94.93	0.00	84.15	0.68	/workspace/coverage/cover_reg_top/4.chip_csr_rw.3052595141
88.88	0.56	91.25	0.00	84.49	0.00	83.65	0.00			91.45	0.00	94.93	0.00	87.52	3.37	/workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.1754828349
89.39	0.51	91.68	0.44	84.69	0.20	84.73	1.08			91.57	0.12	94.93	0.00	88.73	1.21	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2711650807
89.90	0.51	92.41	0.73	85.66	0.96	85.28	0.55			92.37	0.80	94.93	0.00	88.73	0.00	/workspace/coverage/default/0.chip_sw_gpio.3391785354
90.39	0.49	92.72	0.30	85.93	0.27	86.82	1.55			92.65	0.28	95.28	0.35	88.92	0.19	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1363152580
90.82	0.44	92.73	0.01	88.13	2.21	86.82	0.00			92.65	0.00	95.28	0.00	89.33	0.41	/workspace/coverage/cover_reg_top/4.chip_tl_errors.2130464953
91.21	0.39	92.73	0.00	88.14	0.01	86.82	0.00			92.65	0.00	95.28	0.00	91.65	2.31	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.1741332790
91.58	0.37	93.12	0.40	88.50	0.36	87.32	0.50			93.04	0.39	95.80	0.52	91.67	0.02	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2466271889
91.92	0.34	93.12	0.00	88.50	0.00	87.32	0.00			93.04	0.00	95.80	0.00	93.74	2.07	/workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.3474362349
92.25	0.32	93.13	0.01	88.51	0.01	89.25	1.93			93.04	0.00	95.80	0.00	93.74	0.00	/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2857860287
92.53	0.28	93.67	0.54	89.01	0.50	89.38	0.13			93.55	0.51	95.80	0.00	93.74	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.2636860270
92.80	0.28	93.71	0.03	89.36	0.35	89.38	0.00			93.57	0.02	95.80	0.00	94.99	1.26	/workspace/coverage/cover_reg_top/35.xbar_access_same_device.3710993368
93.03	0.23	93.71	0.00	89.66	0.29	89.38	0.00			93.57	0.00	95.80	0.00	96.08	1.08	/workspace/coverage/cover_reg_top/36.xbar_stress_all.3481524719
93.26	0.23	93.71	0.00	89.66	0.00	90.75	1.37			93.57	0.00	95.80	0.00	96.08	0.00	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1547895459
93.43	0.17	93.71	0.00	89.76	0.10	90.75	0.00			93.57	0.00	95.80	0.00	96.99	0.92	/workspace/coverage/cover_reg_top/89.xbar_random_large_delays.1284409939
93.58	0.15	93.91	0.21	90.08	0.32	91.10	0.35			93.57	0.00	95.80	0.00	96.99	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1954998836
93.72	0.15	94.06	0.15	90.24	0.16	91.36	0.26			93.70	0.12	95.98	0.17	97.00	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.2386220407
93.84	0.12	94.07	0.01	90.57	0.34	91.40	0.04			94.04	0.34	95.98	0.00	97.00	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2859036191
93.96	0.12	94.07	0.00	90.57	0.00	92.10	0.70			94.04	0.00	95.98	0.00	97.00	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1342514453
94.07	0.11	94.07	0.00	90.82	0.25	92.10	0.00			94.05	0.02	95.98	0.00	97.38	0.38	/workspace/coverage/cover_reg_top/79.xbar_stress_all.1433751207
94.16	0.09	94.07	0.00	90.83	0.01	92.65	0.54			94.05	0.00	95.98	0.00	97.38	0.00	/workspace/coverage/default/10.chip_sw_all_escalation_resets.78151644
94.25	0.09	94.18	0.11	91.20	0.37	92.66	0.02			94.08	0.02	95.98	0.00	97.39	0.01	/workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.931932358
94.34	0.09	94.20	0.02	91.33	0.13	92.80	0.14			94.14	0.06	96.15	0.17	97.39	0.00	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3542184174
94.42	0.09	94.20	0.00	91.85	0.52	92.80	0.00			94.14	0.00	96.15	0.00	97.39	0.00	/workspace/coverage/cover_reg_top/5.chip_tl_errors.333317513
94.51	0.08	94.24	0.04	91.88	0.03	92.85	0.05			94.17	0.02	96.50	0.35	97.39	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.638360151
94.58	0.08	94.24	0.00	91.90	0.02	92.89	0.04			94.17	0.00	96.50	0.00	97.79	0.40	/workspace/coverage/default/0.chip_sw_alert_test.1413913050
94.65	0.07	94.41	0.17	92.00	0.10	92.95	0.06			94.23	0.06	96.50	0.00	97.80	0.01	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3514302021
94.71	0.06	94.41	0.00	92.00	0.00	93.30	0.35			94.23	0.00	96.50	0.00	97.80	0.00	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1411181408
94.77	0.06	94.41	0.00	92.03	0.02	93.62	0.32			94.24	0.01	96.50	0.00	97.80	0.00	/workspace/coverage/default/1.chip_sw_flash_init.3877666973
94.82	0.06	94.41	0.00	92.18	0.16	93.62	0.01			94.42	0.18	96.50	0.00	97.80	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.36343321
94.88	0.05	94.45	0.04	92.21	0.02	93.67	0.05			94.43	0.02	96.68	0.17	97.81	0.01	/workspace/coverage/default/99.chip_sw_all_escalation_resets.1582762326
94.92	0.05	94.47	0.02	92.22	0.02	93.73	0.06			94.43	0.00	96.85	0.17	97.81	0.00	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3036226908
94.96	0.04	94.50	0.03	92.35	0.12	93.73	0.00			94.52	0.09	96.85	0.00	97.81	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.1006864932
95.00	0.04	94.51	0.01	92.36	0.01	93.73	0.00			94.55	0.02	97.03	0.17	97.83	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.730586479
95.04	0.04	94.54	0.03	92.36	0.01	93.73	0.01			94.56	0.01	97.20	0.17	97.84	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.3427539042
95.08	0.04	94.54	0.00	92.37	0.01	93.73	0.00			94.56	0.00	97.20	0.00	98.06	0.22	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.4219681155
95.11	0.04	94.58	0.03	92.48	0.11	93.73	0.00			94.56	0.01	97.20	0.00	98.13	0.07	/workspace/coverage/cover_reg_top/8.xbar_stress_all.1326407048
95.15	0.04	94.58	0.01	92.49	0.01	93.74	0.01			94.57	0.01	97.38	0.17	98.14	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.1909042473
95.19	0.04	94.58	0.00	92.71	0.22	93.74	0.00			94.57	0.00	97.38	0.00	98.14	0.00	/workspace/coverage/cover_reg_top/7.chip_tl_errors.1603085812
95.22	0.03	94.58	0.00	92.71	0.00	93.94	0.20			94.57	0.00	97.38	0.00	98.14	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2547929102
95.25	0.03	94.58	0.00	92.71	0.00	94.14	0.20			94.57	0.00	97.38	0.00	98.14	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.739202706
95.28	0.03	94.59	0.01	92.72	0.01	94.29	0.16			94.58	0.01	97.38	0.00	98.14	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3141671831
95.31	0.03	94.59	0.00	92.72	0.00	94.47	0.17			94.58	0.00	97.38	0.00	98.14	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.259007092
95.34	0.03	94.66	0.07	92.75	0.03	94.47	0.01			94.63	0.05	97.38	0.00	98.14	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1913613789
95.36	0.02	94.66	0.00	92.75	0.00	94.62	0.15			94.63	0.00	97.38	0.00	98.14	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1669977425
95.39	0.02	94.73	0.07	92.75	0.00	94.69	0.07			94.64	0.01	97.38	0.00	98.14	0.00	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2927175761
95.41	0.02	94.75	0.02	92.76	0.01	94.81	0.12			94.64	0.00	97.38	0.00	98.14	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2144084218
95.44	0.02	94.75	0.00	92.90	0.14	94.81	0.00			94.64	0.00	97.38	0.00	98.14	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.1503478464
95.46	0.02	94.75	0.00	92.98	0.08	94.81	0.00			94.65	0.02	97.38	0.00	98.19	0.05	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3140838452
95.48	0.02	94.75	0.00	93.01	0.03	94.81	0.00			94.65	0.00	97.38	0.00	98.30	0.11	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.4277410778
95.50	0.02	94.78	0.03	93.01	0.01	94.89	0.08			94.65	0.00	97.38	0.00	98.30	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1267590768
95.52	0.02	94.84	0.06	93.06	0.05	94.89	0.00			94.67	0.02	97.38	0.00	98.30	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2996293033
95.54	0.02	94.84	0.00	93.07	0.02	94.89	0.00			94.67	0.00	97.38	0.00	98.39	0.09	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3418010951
95.56	0.02	94.84	0.00	93.18	0.10	94.89	0.00			94.67	0.00	97.38	0.00	98.39	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.3926960162
95.57	0.01	94.84	0.00	93.26	0.08	94.89	0.00			94.67	0.00	97.38	0.00	98.39	0.00	/workspace/coverage/cover_reg_top/14.chip_tl_errors.992956219
95.59	0.01	94.84	0.00	93.28	0.01	94.89	0.00			94.67	0.00	97.38	0.00	98.46	0.07	/workspace/coverage/cover_reg_top/63.xbar_access_same_device.2141591047
95.60	0.01	94.84	0.00	93.28	0.00	94.98	0.08			94.67	0.00	97.38	0.00	98.46	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3129241914
95.61	0.01	94.85	0.01	93.32	0.05	94.98	0.00			94.69	0.02	97.38	0.00	98.46	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3427917715
95.63	0.01	94.85	0.00	93.37	0.05	94.98	0.00			94.72	0.02	97.38	0.00	98.46	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.4236033118
95.64	0.01	94.85	0.00	93.37	0.00	95.05	0.08			94.72	0.00	97.38	0.00	98.46	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.4019816078
95.65	0.01	94.85	0.00	93.39	0.01	95.05	0.00			94.72	0.00	97.38	0.00	98.52	0.06	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2621887601
95.66	0.01	94.86	0.01	93.42	0.03	95.06	0.01			94.73	0.02	97.38	0.00	98.52	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.571306444
95.67	0.01	94.86	0.00	93.49	0.07	95.06	0.00			94.73	0.00	97.38	0.00	98.52	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1925181867
95.68	0.01	94.86	0.00	93.54	0.05	95.06	0.00			94.75	0.02	97.38	0.00	98.52	0.00	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.2423920049
95.70	0.01	94.90	0.03	93.56	0.02	95.06	0.00			94.76	0.01	97.38	0.00	98.52	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2409056499
95.71	0.01	94.92	0.02	93.56	0.01	95.10	0.04			94.76	0.00	97.38	0.00	98.52	0.00	/workspace/coverage/default/0.chip_sw_power_sleep_load.717077477
95.72	0.01	94.92	0.00	93.56	0.00	95.10	0.00			94.76	0.00	97.38	0.00	98.58	0.06	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.443912371
95.72	0.01	94.94	0.02	93.57	0.01	95.11	0.01			94.77	0.02	97.38	0.00	98.58	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3908486081
95.73	0.01	94.94	0.00	93.61	0.04	95.11	0.00			94.79	0.02	97.38	0.00	98.58	0.00	/workspace/coverage/cover_reg_top/2.xbar_stress_all.367804799
95.74	0.01	94.94	0.00	93.61	0.01	95.11	0.00			94.79	0.00	97.38	0.00	98.63	0.05	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.4275201562
95.75	0.01	94.94	0.00	93.61	0.00	95.15	0.04			94.79	0.00	97.38	0.00	98.64	0.01	/workspace/coverage/default/51.chip_sw_all_escalation_resets.620244040
95.76	0.01	94.96	0.02	93.62	0.01	95.15	0.01			94.81	0.02	97.38	0.00	98.64	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3584745136
95.77	0.01	94.96	0.00	93.66	0.05	95.15	0.00			94.81	0.00	97.38	0.00	98.64	0.00	/workspace/coverage/cover_reg_top/6.chip_tl_errors.3894779517
95.77	0.01	94.97	0.01	93.68	0.02	95.16	0.01			94.81	0.00	97.38	0.00	98.64	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2450463311
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96.00	0.01	94.99	0.00	93.94	0.00	95.39	0.00			94.81	0.00	97.38	0.00	99.47	0.01	/workspace/coverage/default/66.chip_sw_all_escalation_resets.2142581639
96.00	0.01	94.99	0.00	93.94	0.00	95.39	0.00			94.81	0.00	97.38	0.00	99.48	0.01	/workspace/coverage/default/67.chip_sw_all_escalation_resets.91912425
96.00	0.01	94.99	0.00	93.94	0.00	95.39	0.00			94.81	0.00	97.38	0.00	99.49	0.01	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2234661739
96.00	0.01	94.99	0.00	93.94	0.00	95.39	0.00			94.81	0.00	97.38	0.00	99.51	0.01	/workspace/coverage/default/82.chip_sw_all_escalation_resets.2882897928
96.00	0.01	94.99	0.00	93.94	0.00	95.39	0.00			94.81	0.00	97.38	0.00	99.52	0.01	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2682677747
96.01	0.01	94.99	0.00	93.94	0.00	95.39	0.00			94.81	0.00	97.38	0.00	99.53	0.01	/workspace/coverage/default/94.chip_sw_all_escalation_resets.2289745305
96.01	0.01	94.99	0.00	93.94	0.00	95.40	0.01			94.81	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3236215940
96.01	0.01	94.99	0.00	93.94	0.00	95.42	0.01			94.81	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1438356870
96.01	0.01	94.99	0.00	93.95	0.01	95.42	0.00			94.81	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.1804876203
96.01	0.01	94.99	0.00	93.96	0.01	95.42	0.00			94.81	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2597336928
96.02	0.01	94.99	0.00	93.97	0.01	95.42	0.00			94.81	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.113446099
96.02	0.01	94.99	0.00	93.98	0.01	95.42	0.00			94.81	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2007484384
96.02	0.01	95.00	0.01	93.98	0.00	95.42	0.01			94.81	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/20.chip_sw_all_escalation_resets.272435521
96.02	0.01	95.00	0.01	93.98	0.01	95.42	0.00			94.81	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2838879678
96.02	0.01	95.00	0.00	93.98	0.00	95.43	0.01			94.81	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_kmac_entropy.3858990897
96.02	0.01	95.00	0.00	93.98	0.00	95.44	0.01			94.81	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1597975076
96.03	0.01	95.00	0.00	93.98	0.00	95.45	0.01			94.81	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.1643876308
96.03	0.01	95.00	0.00	93.98	0.00	95.45	0.00			94.82	0.01	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.9945956
96.03	0.01	95.00	0.00	93.98	0.00	95.45	0.00			94.82	0.01	97.38	0.00	99.53	0.00	/workspace/coverage/default/3.chip_tap_straps_dev.3711368658
96.03	0.01	95.00	0.00	93.99	0.01	95.45	0.00			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.1783119597
96.03	0.01	95.00	0.00	94.00	0.01	95.45	0.00			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/19.chip_tl_errors.609040406
96.03	0.01	95.00	0.00	94.00	0.01	95.45	0.00			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.4037195572
96.03	0.01	95.00	0.00	94.00	0.00	95.46	0.01			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.161507228
96.03	0.01	95.01	0.01	94.00	0.00	95.46	0.00			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3447329140
96.03	0.01	95.01	0.00	94.00	0.00	95.46	0.01			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3234678051
96.04	0.01	95.01	0.00	94.00	0.00	95.47	0.01			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3514777444
96.04	0.01	95.01	0.00	94.00	0.00	95.47	0.01			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.3318625538
96.04	0.01	95.01	0.00	94.00	0.00	95.48	0.01			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_flash_init.3314260106
96.04	0.01	95.01	0.00	94.00	0.00	95.48	0.01			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2415893787
96.04	0.01	95.01	0.00	94.00	0.00	95.49	0.01			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3756250197
96.04	0.01	95.01	0.00	94.00	0.00	95.49	0.01			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2225967560
96.04	0.01	95.01	0.00	94.01	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.3928889885
96.04	0.01	95.01	0.00	94.01	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/20.xbar_stress_all.3217067930
96.04	0.01	95.01	0.00	94.01	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.2591724582
96.04	0.01	95.01	0.00	94.02	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.3452014808
96.04	0.01	95.01	0.00	94.02	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3976141113
96.04	0.01	95.01	0.00	94.02	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3742799617
96.04	0.01	95.01	0.00	94.03	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1183259996
96.04	0.01	95.01	0.00	94.03	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.809420597
96.04	0.01	95.01	0.00	94.04	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2612355612
96.05	0.01	95.01	0.01	94.04	0.00	95.49	0.00			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.1876584099
96.05	0.01	95.01	0.00	94.04	0.00	95.49	0.01			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2321838643
96.05	0.01	95.01	0.00	94.04	0.00	95.50	0.01			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2668276594
96.05	0.01	95.01	0.00	94.04	0.00	95.50	0.01			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.1840639341
96.05	0.01	95.01	0.00	94.04	0.00	95.50	0.01			94.82	0.00	97.38	0.00	99.53	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1407146922

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1087964158
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1053326757
/workspace/coverage/cover_reg_top/0.chip_csr_rw.826627855
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.737139279
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3205281343
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2893306389
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1769705976
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3092760855
/workspace/coverage/cover_reg_top/0.xbar_error_random.1445333543
/workspace/coverage/cover_reg_top/0.xbar_random.3786159039
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3609385888
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3775410435
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3893773534
/workspace/coverage/cover_reg_top/0.xbar_same_source.2060242401
/workspace/coverage/cover_reg_top/0.xbar_smoke.444022604
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3989373473
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.4076969927
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1929681861
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2890239601
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.751604636
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.226881025
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2907344037
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2769611271
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2899166582
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3942018159
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2257094890
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.806929320
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2454141089
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1640171282
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1986271961
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.3393088463
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1214282848
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1932382881
/workspace/coverage/cover_reg_top/1.xbar_error_random.1007448264
/workspace/coverage/cover_reg_top/1.xbar_random.525946325
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.907838452
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.20404199
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.669632178
/workspace/coverage/cover_reg_top/1.xbar_same_source.1354861644
/workspace/coverage/cover_reg_top/1.xbar_smoke.3631556051
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.795935128
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.744716784
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3855263771
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2004302498
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.612519729
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2274802196
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.465894407
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2456127393
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1381367057
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1626183956
/workspace/coverage/cover_reg_top/10.chip_tl_errors.3055998251
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1631949395
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.4269543025
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2790592334
/workspace/coverage/cover_reg_top/10.xbar_error_random.4038895410
/workspace/coverage/cover_reg_top/10.xbar_random.2250142662
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.654589139
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.806691668
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.954588662
/workspace/coverage/cover_reg_top/10.xbar_same_source.2290899059
/workspace/coverage/cover_reg_top/10.xbar_smoke.2894684107
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.4206053900
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.894912365
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3795148945
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1262055665
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.4211025155
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1651783193
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3835945390
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3967833288
/workspace/coverage/cover_reg_top/11.chip_csr_rw.281327807
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.962332428
/workspace/coverage/cover_reg_top/11.chip_tl_errors.3834494253
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.3050552178
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1891661373
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3168906309
/workspace/coverage/cover_reg_top/11.xbar_error_random.2159799050
/workspace/coverage/cover_reg_top/11.xbar_random.2100486097
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3738139370
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2771902035
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.4189217181
/workspace/coverage/cover_reg_top/11.xbar_same_source.2220486311
/workspace/coverage/cover_reg_top/11.xbar_smoke.3159196334
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.998834160
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1590124787
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1405212478
/workspace/coverage/cover_reg_top/11.xbar_stress_all.2871019244
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1929130048
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1186920530
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.4135339214
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.357279777
/workspace/coverage/cover_reg_top/12.chip_csr_rw.2434633372
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1520709513
/workspace/coverage/cover_reg_top/12.chip_tl_errors.1611770794
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1503580678
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1268739347
/workspace/coverage/cover_reg_top/12.xbar_error_random.3275031412
/workspace/coverage/cover_reg_top/12.xbar_random.3488760227
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3372310672
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3288137873
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1870395442
/workspace/coverage/cover_reg_top/12.xbar_same_source.465265542
/workspace/coverage/cover_reg_top/12.xbar_smoke.1770737116
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2293848219
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.480488753
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1592680558
/workspace/coverage/cover_reg_top/12.xbar_stress_all.99794071
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3262645511
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2827829888
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3614116011
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.4136632707
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3688423499
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1482409105
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.246610516
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3015495103
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2772576052
/workspace/coverage/cover_reg_top/13.xbar_error_random.2700225274
/workspace/coverage/cover_reg_top/13.xbar_random.1460271127
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.4077940540
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3612707191
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.672473302
/workspace/coverage/cover_reg_top/13.xbar_same_source.3033862283
/workspace/coverage/cover_reg_top/13.xbar_smoke.278339826
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3757100589
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2625194777
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2156405411
/workspace/coverage/cover_reg_top/13.xbar_stress_all.1066390172
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2746248584
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3843001322
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1121312573
/workspace/coverage/cover_reg_top/14.chip_csr_rw.2897844333
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2374540718
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.3588172915
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.522012628
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2132845160
/workspace/coverage/cover_reg_top/14.xbar_error_random.2710621793
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/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2099300619
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/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1884312782
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/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2699889936
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2235363304
/workspace/coverage/default/32.chip_sw_all_escalation_resets.2193602148
/workspace/coverage/default/33.chip_sw_all_escalation_resets.2387288714
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2965144189
/workspace/coverage/default/34.chip_sw_all_escalation_resets.3695690269
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1472175824
/workspace/coverage/default/36.chip_sw_all_escalation_resets.2808706888
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1279018803
/workspace/coverage/default/37.chip_sw_all_escalation_resets.1162540652
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/workspace/coverage/default/39.chip_sw_all_escalation_resets.3727614130
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.150731415
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2459571185
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.4138006740
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1717115488
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.849045906
/workspace/coverage/default/4.chip_sw_uart_tx_rx.721981916
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3183043627
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.283461325
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.226604541
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/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2423956313
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/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2387597399
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/workspace/coverage/default/44.chip_sw_all_escalation_resets.2471484515
/workspace/coverage/default/45.chip_sw_all_escalation_resets.2936345008
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1563331944
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/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.661780131
/workspace/coverage/default/47.chip_sw_all_escalation_resets.3778325431
/workspace/coverage/default/48.chip_sw_all_escalation_resets.1635578564
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2925561211
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2033977929
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.4123970317
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.4180075876
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1162763742
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.283718821
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1982549121
/workspace/coverage/default/52.chip_sw_all_escalation_resets.4036286476
/workspace/coverage/default/53.chip_sw_all_escalation_resets.3643421632
/workspace/coverage/default/56.chip_sw_all_escalation_resets.3227978022
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3062976623
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.4195985673
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3645296790
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1552264986
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2293196576
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1515231127
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3376228431
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1675132148
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.605167215
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2316681211
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2608139467
/workspace/coverage/default/63.chip_sw_all_escalation_resets.976452046
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.4011546255
/workspace/coverage/default/64.chip_sw_all_escalation_resets.186475438
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2647403161
/workspace/coverage/default/65.chip_sw_all_escalation_resets.1622039142
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3269979967
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2934077847
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1932927919
/workspace/coverage/default/68.chip_sw_all_escalation_resets.3150130178
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2909077950
/workspace/coverage/default/69.chip_sw_all_escalation_resets.3286865951
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2344000161
/workspace/coverage/default/7.chip_sw_all_escalation_resets.938054682
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2048364702
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1878752013
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3956711040
/workspace/coverage/default/70.chip_sw_all_escalation_resets.1027361955
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2568284215
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2390872292
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3614884379
/workspace/coverage/default/72.chip_sw_all_escalation_resets.112385731
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2573976289
/workspace/coverage/default/73.chip_sw_all_escalation_resets.4055376041
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2259326546
/workspace/coverage/default/74.chip_sw_all_escalation_resets.849950490
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2411935073
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1008883174
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3883207789
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2477933662
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1632522102
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1649705357
/workspace/coverage/default/79.chip_sw_all_escalation_resets.3758182200
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1211716711
/workspace/coverage/default/8.chip_sw_all_escalation_resets.1129283126
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1284928539
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1235770238
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3447684391
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.193930805
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1022481393
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2993067457
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.558452081
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1725795122
/workspace/coverage/default/83.chip_sw_all_escalation_resets.2959690337
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3239115009
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2226838827
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3945365547
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3285365982
/workspace/coverage/default/86.chip_sw_all_escalation_resets.2683551738
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3019076327
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2309588896
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2512190632
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1435850277
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2786911386
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3408289522
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3007062834
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3451923630
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.759094777
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1704373131
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2041827500
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3947061169
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3351035553
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2139028775
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2171722233
/workspace/coverage/default/95.chip_sw_all_escalation_resets.851170738
/workspace/coverage/default/96.chip_sw_all_escalation_resets.3193179972
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1466874415
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3319463055
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.372354336
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.428106827
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.4006692828
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1346498836
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1993502649
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.165764358
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2205608380
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1415867871

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Total test records in report: 2903

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2877049273			Jul 10 08:17:41 PM PDT 24	Jul 10 08:29:06 PM PDT 24	4624471128 ps
T5	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.698845129			Jul 10 08:01:02 PM PDT 24	Jul 10 08:07:35 PM PDT 24	6224850558 ps
T6	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3305652649			Jul 10 07:58:33 PM PDT 24	Jul 10 08:03:16 PM PDT 24	2508132900 ps
T60	/workspace/coverage/default/0.chip_sw_aes_idle.1324894211			Jul 10 07:55:48 PM PDT 24	Jul 10 08:00:51 PM PDT 24	3386796420 ps
T86	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1411181408			Jul 10 08:12:12 PM PDT 24	Jul 10 08:16:55 PM PDT 24	2831562314 ps
T87	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.326037372			Jul 10 08:19:44 PM PDT 24	Jul 10 08:23:38 PM PDT 24	2338046905 ps
T18	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1267590768			Jul 10 08:09:38 PM PDT 24	Jul 10 09:07:13 PM PDT 24	15303437000 ps
T88	/workspace/coverage/default/0.chip_sw_plic_sw_irq.851022066			Jul 10 07:57:21 PM PDT 24	Jul 10 08:01:12 PM PDT 24	2690712014 ps
T16	/workspace/coverage/default/5.chip_sw_all_escalation_resets.1212994122			Jul 10 08:22:28 PM PDT 24	Jul 10 08:36:28 PM PDT 24	5010938820 ps
T42	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1388330602			Jul 10 08:05:14 PM PDT 24	Jul 10 08:11:18 PM PDT 24	4675065131 ps
T191	/workspace/coverage/default/0.chip_sw_uart_smoketest.1331083167			Jul 10 08:02:00 PM PDT 24	Jul 10 08:06:34 PM PDT 24	2603442040 ps
T19	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1547895459			Jul 10 08:24:26 PM PDT 24	Jul 10 08:31:51 PM PDT 24	5499862790 ps
T20	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1167569415			Jul 10 07:57:12 PM PDT 24	Jul 10 09:40:17 PM PDT 24	48432008280 ps
T192	/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.4204835362			Jul 10 08:17:02 PM PDT 24	Jul 10 08:42:32 PM PDT 24	7718651588 ps
T53	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2543183596			Jul 10 08:24:53 PM PDT 24	Jul 10 09:03:38 PM PDT 24	11571239399 ps
T17	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3135903295			Jul 10 07:55:21 PM PDT 24	Jul 10 08:05:29 PM PDT 24	4470221835 ps
T61	/workspace/coverage/default/38.chip_sw_all_escalation_resets.3895199344			Jul 10 08:28:03 PM PDT 24	Jul 10 08:35:28 PM PDT 24	4153552000 ps
T120	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2144084218			Jul 10 07:56:36 PM PDT 24	Jul 10 08:15:51 PM PDT 24	9139494705 ps
T55	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2814763615			Jul 10 07:58:11 PM PDT 24	Jul 10 09:43:17 PM PDT 24	50676099225 ps
T62	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1363152580			Jul 10 08:05:09 PM PDT 24	Jul 10 08:26:34 PM PDT 24	16456551778 ps
T31	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1446961188			Jul 10 07:57:40 PM PDT 24	Jul 10 09:05:19 PM PDT 24	20149837394 ps
T24	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1607176174			Jul 10 08:04:32 PM PDT 24	Jul 10 08:17:20 PM PDT 24	7458218494 ps
T123	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4060715255			Jul 10 08:23:46 PM PDT 24	Jul 10 08:31:17 PM PDT 24	7117084748 ps
T121	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3004196860			Jul 10 08:17:05 PM PDT 24	Jul 10 08:26:52 PM PDT 24	4400416232 ps
T151	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3135329026			Jul 10 07:56:13 PM PDT 24	Jul 10 08:01:00 PM PDT 24	3167671630 ps
T190	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3865295252			Jul 10 08:06:13 PM PDT 24	Jul 10 08:20:28 PM PDT 24	7011543580 ps
T313	/workspace/coverage/default/51.chip_sw_all_escalation_resets.620244040			Jul 10 08:28:52 PM PDT 24	Jul 10 08:39:39 PM PDT 24	5792425396 ps
T324	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3514302021			Jul 10 08:32:32 PM PDT 24	Jul 10 08:37:54 PM PDT 24	3383317858 ps
T227	/workspace/coverage/default/26.chip_sw_all_escalation_resets.2386220407			Jul 10 08:27:46 PM PDT 24	Jul 10 08:37:18 PM PDT 24	4766535720 ps
T262	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3614884379			Jul 10 08:30:29 PM PDT 24	Jul 10 08:35:50 PM PDT 24	3847208192 ps
T234	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2736106928			Jul 10 07:57:44 PM PDT 24	Jul 10 08:19:40 PM PDT 24	10653246320 ps
T263	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.697617302			Jul 10 08:29:30 PM PDT 24	Jul 10 08:35:12 PM PDT 24	3706268848 ps
T169	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.4019816078			Jul 10 07:58:38 PM PDT 24	Jul 10 08:05:39 PM PDT 24	7253337814 ps
T218	/workspace/coverage/default/32.chip_sw_all_escalation_resets.2193602148			Jul 10 08:25:51 PM PDT 24	Jul 10 08:36:21 PM PDT 24	5565596004 ps
T264	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.146162433			Jul 10 08:02:18 PM PDT 24	Jul 10 08:06:18 PM PDT 24	3070968992 ps
T223	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2057409129			Jul 10 08:17:15 PM PDT 24	Jul 10 08:23:16 PM PDT 24	5044641736 ps
T265	/workspace/coverage/default/0.chip_sw_kmac_entropy.3858990897			Jul 10 07:56:17 PM PDT 24	Jul 10 08:01:47 PM PDT 24	2456847740 ps
T224	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.517568128			Jul 10 08:18:08 PM PDT 24	Jul 10 08:26:39 PM PDT 24	4881440810 ps
T442	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3672799656			Jul 10 08:19:17 PM PDT 24	Jul 10 08:25:11 PM PDT 24	2824891859 ps
T704	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2636896707			Jul 10 08:10:04 PM PDT 24	Jul 10 08:18:03 PM PDT 24	3817947912 ps
T519	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2281781705			Jul 10 08:12:26 PM PDT 24	Jul 10 08:18:05 PM PDT 24	3092554444 ps
T705	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.3713501533			Jul 10 08:10:01 PM PDT 24	Jul 10 08:25:11 PM PDT 24	7799232696 ps
T164	/workspace/coverage/default/1.chip_sw_flash_init.3877666973			Jul 10 08:00:39 PM PDT 24	Jul 10 08:22:20 PM PDT 24	17565354262 ps
T214	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1162763742			Jul 10 08:22:36 PM PDT 24	Jul 10 08:30:15 PM PDT 24	4362889344 ps
T54	/workspace/coverage/default/2.rom_e2e_asm_init_rma.1120311847			Jul 10 08:25:43 PM PDT 24	Jul 10 09:34:01 PM PDT 24	14651700987 ps
T413	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2444693841			Jul 10 08:26:02 PM PDT 24	Jul 10 08:33:13 PM PDT 24	3839744840 ps
T51	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.854634659			Jul 10 08:07:55 PM PDT 24	Jul 10 09:29:48 PM PDT 24	17639109110 ps
T876	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.348220318			Jul 10 08:20:22 PM PDT 24	Jul 10 08:25:27 PM PDT 24	3015650824 ps
T358	/workspace/coverage/default/91.chip_sw_all_escalation_resets.3351035553			Jul 10 08:42:15 PM PDT 24	Jul 10 08:54:09 PM PDT 24	5572489808 ps
T170	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1878752013			Jul 10 08:23:18 PM PDT 24	Jul 10 08:35:36 PM PDT 24	5823832058 ps
T115	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1445480543			Jul 10 08:00:04 PM PDT 24	Jul 10 09:04:27 PM PDT 24	24728689536 ps
T660	/workspace/coverage/default/2.chip_sw_aes_masking_off.2859946722			Jul 10 08:16:17 PM PDT 24	Jul 10 08:22:58 PM PDT 24	3307608329 ps
T219	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.4041537475			Jul 10 08:14:35 PM PDT 24	Jul 10 08:23:28 PM PDT 24	3798645562 ps
T189	/workspace/coverage/default/0.chip_tap_straps_prod.1584571864			Jul 10 07:59:33 PM PDT 24	Jul 10 08:02:02 PM PDT 24	2869759451 ps
T254	/workspace/coverage/default/1.chip_sw_uart_smoketest.3048074740			Jul 10 08:17:44 PM PDT 24	Jul 10 08:21:37 PM PDT 24	2671551160 ps
T215	/workspace/coverage/default/0.chip_sw_pattgen_ios.1876584099			Jul 10 07:57:13 PM PDT 24	Jul 10 08:02:22 PM PDT 24	3073231960 ps
T255	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2459571185			Jul 10 08:23:40 PM PDT 24	Jul 10 08:31:30 PM PDT 24	6399208856 ps
T256	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2506750498			Jul 10 08:02:15 PM PDT 24	Jul 10 08:14:25 PM PDT 24	4083552296 ps
T257	/workspace/coverage/default/93.chip_sw_all_escalation_resets.2171722233			Jul 10 08:41:37 PM PDT 24	Jul 10 08:49:19 PM PDT 24	5896696720 ps
T258	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2666387910			Jul 10 08:04:28 PM PDT 24	Jul 10 08:15:41 PM PDT 24	4346721700 ps
T231	/workspace/coverage/default/1.chip_sw_plic_sw_irq.2432968044			Jul 10 08:10:38 PM PDT 24	Jul 10 08:14:31 PM PDT 24	2620448632 ps
T27	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3940402176			Jul 10 08:21:53 PM PDT 24	Jul 10 08:31:42 PM PDT 24	4431389232 ps
T710	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2824107745			Jul 10 08:30:25 PM PDT 24	Jul 10 08:36:04 PM PDT 24	3322804772 ps
T172	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.4063964431			Jul 10 08:17:47 PM PDT 24	Jul 10 09:23:25 PM PDT 24	15919568446 ps
T698	/workspace/coverage/default/2.chip_sw_hmac_oneshot.4130014779			Jul 10 08:16:12 PM PDT 24	Jul 10 08:22:02 PM PDT 24	3212138972 ps
T48	/workspace/coverage/default/0.chip_sw_spi_device_tpm.3059574285			Jul 10 07:57:58 PM PDT 24	Jul 10 08:04:03 PM PDT 24	3257670774 ps
T433	/workspace/coverage/default/99.chip_sw_all_escalation_resets.1582762326			Jul 10 08:41:49 PM PDT 24	Jul 10 08:50:21 PM PDT 24	5816276792 ps
T202	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3609587795			Jul 10 08:00:00 PM PDT 24	Jul 10 08:13:25 PM PDT 24	4954547169 ps
T220	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3036226908			Jul 10 08:23:31 PM PDT 24	Jul 10 08:32:54 PM PDT 24	5463702970 ps
T126	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1784176951			Jul 10 08:06:49 PM PDT 24	Jul 10 09:01:45 PM PDT 24	17600339250 ps
T66	/workspace/coverage/default/1.rom_raw_unlock.1162259753			Jul 10 08:12:29 PM PDT 24	Jul 10 08:16:42 PM PDT 24	5483600772 ps
T127	/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2857860287			Jul 10 08:23:28 PM PDT 24	Jul 10 09:34:31 PM PDT 24	19031366350 ps
T135	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3908486081			Jul 10 08:08:55 PM PDT 24	Jul 10 08:21:45 PM PDT 24	6403554808 ps
T232	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1607464215			Jul 10 08:02:55 PM PDT 24	Jul 10 08:07:16 PM PDT 24	3090646200 ps
T439	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.822557597			Jul 10 08:02:44 PM PDT 24	Jul 10 08:14:29 PM PDT 24	5850712160 ps
T179	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3196564600			Jul 10 07:55:35 PM PDT 24	Jul 10 08:03:10 PM PDT 24	5096707476 ps
T52	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1827554493			Jul 10 08:06:30 PM PDT 24	Jul 10 09:26:19 PM PDT 24	14870254616 ps
T233	/workspace/coverage/default/0.chip_sw_rv_timer_irq.1809518125			Jul 10 07:56:39 PM PDT 24	Jul 10 08:02:02 PM PDT 24	2781297920 ps
T877	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1744509429			Jul 10 08:17:51 PM PDT 24	Jul 10 08:26:47 PM PDT 24	4832482890 ps
T409	/workspace/coverage/default/34.chip_sw_all_escalation_resets.3695690269			Jul 10 08:26:06 PM PDT 24	Jul 10 08:36:28 PM PDT 24	4959670906 ps
T7	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1959557939			Jul 10 08:12:18 PM PDT 24	Jul 10 08:19:52 PM PDT 24	3188543864 ps
T32	/workspace/coverage/default/1.chip_jtag_csr_rw.2290299270			Jul 10 08:02:33 PM PDT 24	Jul 10 08:34:20 PM PDT 24	18407494367 ps
T1	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2409056499			Jul 10 08:13:38 PM PDT 24	Jul 10 08:23:04 PM PDT 24	5261825774 ps
T102	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1476347003			Jul 10 08:09:11 PM PDT 24	Jul 10 08:15:57 PM PDT 24	4986535868 ps
T103	/workspace/coverage/default/1.chip_plic_all_irqs_10.2636860270			Jul 10 08:09:39 PM PDT 24	Jul 10 08:21:13 PM PDT 24	4499574680 ps
T104	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3653294788			Jul 10 08:00:14 PM PDT 24	Jul 10 08:20:46 PM PDT 24	5481384852 ps
T105	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4170698991			Jul 10 08:22:25 PM PDT 24	Jul 10 08:52:53 PM PDT 24	13648504213 ps
T33	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.638360151			Jul 10 07:57:24 PM PDT 24	Jul 10 08:23:59 PM PDT 24	24182946116 ps
T106	/workspace/coverage/default/8.chip_sw_all_escalation_resets.1129283126			Jul 10 08:25:17 PM PDT 24	Jul 10 08:36:46 PM PDT 24	4871099188 ps
T107	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2606852591			Jul 10 08:15:05 PM PDT 24	Jul 10 08:27:58 PM PDT 24	5163400640 ps
T108	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.2425491083			Jul 10 08:08:27 PM PDT 24	Jul 10 08:37:08 PM PDT 24	7371193472 ps
T109	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3564930679			Jul 10 08:12:24 PM PDT 24	Jul 10 08:24:58 PM PDT 24	6094511652 ps
T244	/workspace/coverage/default/0.chip_sival_flash_info_access.1584945190			Jul 10 07:55:19 PM PDT 24	Jul 10 07:59:54 PM PDT 24	3609842104 ps
T67	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2046860500			Jul 10 08:19:44 PM PDT 24	Jul 10 08:30:59 PM PDT 24	4434941444 ps
T245	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2925561211			Jul 10 08:29:39 PM PDT 24	Jul 10 08:35:51 PM PDT 24	3838341240 ps
T246	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2750687319			Jul 10 08:09:43 PM PDT 24	Jul 10 08:16:38 PM PDT 24	2785160350 ps
T8	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3515930036			Jul 10 08:19:07 PM PDT 24	Jul 10 08:26:14 PM PDT 24	3159277096 ps
T116	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.409985480			Jul 10 08:00:33 PM PDT 24	Jul 10 08:43:45 PM PDT 24	12198024071 ps
T247	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.4195985673			Jul 10 08:29:33 PM PDT 24	Jul 10 08:35:19 PM PDT 24	3319702192 ps
T212	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.201571539			Jul 10 07:57:52 PM PDT 24	Jul 10 08:29:53 PM PDT 24	7519934586 ps
T75	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3989440505			Jul 10 07:58:14 PM PDT 24	Jul 10 10:51:30 PM PDT 24	59165490634 ps
T344	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2300791915			Jul 10 08:14:23 PM PDT 24	Jul 10 08:25:59 PM PDT 24	3940492116 ps
T235	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.756888977			Jul 10 08:07:07 PM PDT 24	Jul 10 08:22:10 PM PDT 24	8058121882 ps
T878	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2975388268			Jul 10 08:02:23 PM PDT 24	Jul 10 08:06:28 PM PDT 24	3141970568 ps
T392	/workspace/coverage/default/50.chip_sw_all_escalation_resets.1982549121			Jul 10 08:29:50 PM PDT 24	Jul 10 08:40:01 PM PDT 24	4273490770 ps
T2	/workspace/coverage/default/2.chip_jtag_csr_rw.3306540850			Jul 10 08:11:20 PM PDT 24	Jul 10 08:51:12 PM PDT 24	21801322463 ps
T340	/workspace/coverage/default/2.chip_sw_aon_timer_irq.546060696			Jul 10 08:15:32 PM PDT 24	Jul 10 08:22:37 PM PDT 24	4280571320 ps
T156	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3165299635			Jul 10 08:15:53 PM PDT 24	Jul 10 08:18:25 PM PDT 24	3070802533 ps
T150	/workspace/coverage/default/2.chip_sw_power_idle_load.1038964272			Jul 10 08:20:25 PM PDT 24	Jul 10 08:35:52 PM PDT 24	4829202520 ps
T418	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3242528277			Jul 10 08:06:04 PM PDT 24	Jul 10 08:14:42 PM PDT 24	7937404236 ps
T419	/workspace/coverage/default/9.chip_sw_all_escalation_resets.3451923630			Jul 10 08:25:45 PM PDT 24	Jul 10 08:35:32 PM PDT 24	5467068942 ps
T117	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.829408056			Jul 10 08:20:06 PM PDT 24	Jul 10 09:19:06 PM PDT 24	24812546460 ps
T288	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1561120286			Jul 10 08:18:08 PM PDT 24	Jul 10 09:34:13 PM PDT 24	16350099160 ps
T345	/workspace/coverage/default/1.chip_sw_hmac_enc.2775741388			Jul 10 08:09:25 PM PDT 24	Jul 10 08:16:09 PM PDT 24	3134893608 ps
T217	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1345992169			Jul 10 08:10:18 PM PDT 24	Jul 10 08:44:21 PM PDT 24	22947657865 ps
T148	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.4282932352			Jul 10 08:05:07 PM PDT 24	Jul 10 08:14:36 PM PDT 24	4647684944 ps
T359	/workspace/coverage/default/82.chip_sw_all_escalation_resets.2882897928			Jul 10 08:43:05 PM PDT 24	Jul 10 08:53:43 PM PDT 24	5936364844 ps
T289	/workspace/coverage/default/1.chip_sw_all_escalation_resets.4284256792			Jul 10 08:02:23 PM PDT 24	Jul 10 08:13:52 PM PDT 24	5900683740 ps
T110	/workspace/coverage/default/0.chip_sw_power_sleep_load.717077477			Jul 10 08:04:19 PM PDT 24	Jul 10 08:09:24 PM PDT 24	4330854664 ps
T665	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.150731415			Jul 10 08:23:04 PM PDT 24	Jul 10 08:28:56 PM PDT 24	4251858722 ps
T216	/workspace/coverage/default/1.chip_sw_uart_tx_rx.1468790876			Jul 10 08:01:27 PM PDT 24	Jul 10 08:11:13 PM PDT 24	3755126150 ps
T879	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1624408926			Jul 10 08:11:20 PM PDT 24	Jul 10 08:15:27 PM PDT 24	2788926920 ps
T76	/workspace/coverage/default/2.chip_jtag_mem_access.2345680098			Jul 10 08:11:19 PM PDT 24	Jul 10 08:39:53 PM PDT 24	14124070168 ps
T356	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.572507239			Jul 10 08:24:22 PM PDT 24	Jul 10 08:37:15 PM PDT 24	4012983768 ps
T699	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3007062834			Jul 10 08:26:00 PM PDT 24	Jul 10 08:31:42 PM PDT 24	3793772910 ps
T291	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1193987582			Jul 10 07:55:43 PM PDT 24	Jul 10 08:14:57 PM PDT 24	8597983100 ps
T80	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2711650807			Jul 10 08:06:15 PM PDT 24	Jul 10 08:26:46 PM PDT 24	11517566064 ps
T687	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.765959846			Jul 10 08:05:39 PM PDT 24	Jul 10 08:09:39 PM PDT 24	2455968586 ps
T155	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2235363304			Jul 10 08:29:28 PM PDT 24	Jul 10 08:36:26 PM PDT 24	4456743120 ps
T880	/workspace/coverage/default/2.chip_sw_aes_idle.3141055825			Jul 10 08:16:28 PM PDT 24	Jul 10 08:20:31 PM PDT 24	2891888812 ps
T166	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3022379646			Jul 10 08:02:56 PM PDT 24	Jul 10 08:44:39 PM PDT 24	33660963560 ps
T881	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1388628268			Jul 10 08:06:51 PM PDT 24	Jul 10 08:11:59 PM PDT 24	2966039048 ps
T882	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3510200281			Jul 10 08:03:43 PM PDT 24	Jul 10 08:13:37 PM PDT 24	4539518638 ps
T389	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.902846981			Jul 10 08:07:55 PM PDT 24	Jul 10 09:50:01 PM PDT 24	23916214700 ps
T390	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2872331157			Jul 10 08:07:36 PM PDT 24	Jul 10 09:37:48 PM PDT 24	17545102920 ps
T221	/workspace/coverage/default/94.chip_sw_all_escalation_resets.2289745305			Jul 10 08:41:48 PM PDT 24	Jul 10 08:51:04 PM PDT 24	4635418258 ps
T225	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.4293295403			Jul 10 08:11:18 PM PDT 24	Jul 10 08:19:40 PM PDT 24	5520522051 ps
T180	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2951982465			Jul 10 08:25:59 PM PDT 24	Jul 10 08:32:56 PM PDT 24	3515983518 ps
T387	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3883207789			Jul 10 08:30:15 PM PDT 24	Jul 10 08:37:01 PM PDT 24	3520049200 ps
T883	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2144746158			Jul 10 08:15:53 PM PDT 24	Jul 10 09:16:42 PM PDT 24	12201872587 ps
T443	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3996374997			Jul 10 07:57:05 PM PDT 24	Jul 10 08:00:16 PM PDT 24	2759253544 ps
T884	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.854911938			Jul 10 08:17:26 PM PDT 24	Jul 10 08:26:09 PM PDT 24	5353348580 ps
T885	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3330624216			Jul 10 08:12:47 PM PDT 24	Jul 10 08:16:49 PM PDT 24	3623111972 ps
T886	/workspace/coverage/default/1.rom_e2e_static_critical.144232343			Jul 10 08:18:35 PM PDT 24	Jul 10 09:24:35 PM PDT 24	16939177968 ps
T128	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2232630008			Jul 10 08:19:08 PM PDT 24	Jul 10 08:28:54 PM PDT 24	6340822482 ps
T887	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3229150654			Jul 10 08:17:08 PM PDT 24	Jul 10 08:23:04 PM PDT 24	2454404070 ps
T697	/workspace/coverage/default/4.chip_sw_all_escalation_resets.2654216683			Jul 10 08:23:57 PM PDT 24	Jul 10 08:32:51 PM PDT 24	5436369210 ps
T213	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1764473941			Jul 10 08:07:08 PM PDT 24	Jul 10 08:39:28 PM PDT 24	7773441048 ps
T888	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.311436971			Jul 10 08:15:42 PM PDT 24	Jul 10 08:19:37 PM PDT 24	2842939876 ps
T203	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3225860068			Jul 10 08:16:13 PM PDT 24	Jul 10 08:26:58 PM PDT 24	5295584308 ps
T434	/workspace/coverage/default/80.chip_sw_all_escalation_resets.1022481393			Jul 10 08:30:07 PM PDT 24	Jul 10 08:38:52 PM PDT 24	5846751032 ps
T889	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3490955462			Jul 10 08:14:28 PM PDT 24	Jul 10 08:32:04 PM PDT 24	7062524256 ps
T711	/workspace/coverage/default/16.chip_sw_all_escalation_resets.768107815			Jul 10 08:27:12 PM PDT 24	Jul 10 08:38:43 PM PDT 24	6235979504 ps
T890	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.418330819			Jul 10 08:09:37 PM PDT 24	Jul 10 08:25:53 PM PDT 24	8157699594 ps
T891	/workspace/coverage/default/2.chip_sw_plic_sw_irq.2364793551			Jul 10 08:17:33 PM PDT 24	Jul 10 08:22:18 PM PDT 24	2666160336 ps
T892	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2364537310			Jul 10 08:11:23 PM PDT 24	Jul 10 08:17:18 PM PDT 24	3438283396 ps
T893	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1758874912			Jul 10 08:05:34 PM PDT 24	Jul 10 08:19:46 PM PDT 24	5943292797 ps
T149	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.624709682			Jul 10 08:21:24 PM PDT 24	Jul 10 08:32:12 PM PDT 24	4326830820 ps
T130	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.132513893			Jul 10 08:21:24 PM PDT 24	Jul 10 08:29:31 PM PDT 24	7166010316 ps
T744	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1279018803			Jul 10 08:27:05 PM PDT 24	Jul 10 08:32:55 PM PDT 24	3999146828 ps
T775	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2423956313			Jul 10 08:27:51 PM PDT 24	Jul 10 08:34:57 PM PDT 24	4026060536 ps
T314	/workspace/coverage/default/63.chip_sw_all_escalation_resets.976452046			Jul 10 08:30:32 PM PDT 24	Jul 10 08:38:23 PM PDT 24	4815177408 ps
T81	/workspace/coverage/default/12.chip_sw_all_escalation_resets.1909042473			Jul 10 08:24:31 PM PDT 24	Jul 10 08:34:56 PM PDT 24	4730242672 ps
T92	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1690626877			Jul 10 08:26:27 PM PDT 24	Jul 10 08:33:09 PM PDT 24	4037702320 ps
T93	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1898900624			Jul 10 08:20:17 PM PDT 24	Jul 10 08:26:34 PM PDT 24	2967572692 ps
T94	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.508581657			Jul 10 08:08:46 PM PDT 24	Jul 10 08:12:42 PM PDT 24	2993693554 ps
T95	/workspace/coverage/default/0.chip_sw_flash_crash_alert.1831112163			Jul 10 07:59:24 PM PDT 24	Jul 10 08:09:22 PM PDT 24	5569027308 ps
T96	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3376228431			Jul 10 08:23:48 PM PDT 24	Jul 10 08:49:55 PM PDT 24	8200655100 ps
T97	/workspace/coverage/default/33.chip_sw_all_escalation_resets.2387288714			Jul 10 08:27:27 PM PDT 24	Jul 10 08:39:13 PM PDT 24	5858735566 ps
T98	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1928643745			Jul 10 08:28:13 PM PDT 24	Jul 10 08:35:04 PM PDT 24	4270736330 ps
T99	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2838879678			Jul 10 07:57:04 PM PDT 24	Jul 10 08:09:57 PM PDT 24	4672705280 ps
T100	/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.625074466			Jul 10 08:09:38 PM PDT 24	Jul 10 08:19:54 PM PDT 24	5518581552 ps
T393	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1211716711			Jul 10 08:24:05 PM PDT 24	Jul 10 08:30:22 PM PDT 24	3032111392 ps
T124	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2547929102			Jul 10 07:57:22 PM PDT 24	Jul 10 08:09:10 PM PDT 24	6007308893 ps
T712	/workspace/coverage/default/64.chip_sw_all_escalation_resets.186475438			Jul 10 08:29:55 PM PDT 24	Jul 10 08:40:21 PM PDT 24	4992047760 ps
T315	/workspace/coverage/default/1.chip_plic_all_irqs_20.1043319285			Jul 10 08:10:36 PM PDT 24	Jul 10 08:23:24 PM PDT 24	4544696696 ps
T394	/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2347306274			Jul 10 07:59:19 PM PDT 24	Jul 10 08:20:52 PM PDT 24	10402446968 ps
T894	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3151412164			Jul 10 08:17:10 PM PDT 24	Jul 10 08:50:53 PM PDT 24	21649523256 ps
T895	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.745721912			Jul 10 08:18:41 PM PDT 24	Jul 10 09:19:47 PM PDT 24	14968803224 ps
T896	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.432464028			Jul 10 08:18:23 PM PDT 24	Jul 10 08:24:40 PM PDT 24	3339147612 ps
T391	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1407146922			Jul 10 08:06:09 PM PDT 24	Jul 10 09:44:00 PM PDT 24	23891078988 ps
T897	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.527431209			Jul 10 08:18:29 PM PDT 24	Jul 10 08:27:07 PM PDT 24	4791471996 ps
T125	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3247203504			Jul 10 08:16:11 PM PDT 24	Jul 10 08:27:22 PM PDT 24	7302026110 ps
T737	/workspace/coverage/default/92.chip_sw_all_escalation_resets.2139028775			Jul 10 08:42:57 PM PDT 24	Jul 10 08:52:10 PM PDT 24	5066231700 ps
T68	/workspace/coverage/default/2.chip_tap_straps_testunlock0.2118151712			Jul 10 08:18:49 PM PDT 24	Jul 10 08:20:53 PM PDT 24	2725259193 ps
T735	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2037425133			Jul 10 07:56:15 PM PDT 24	Jul 10 08:08:25 PM PDT 24	5023333044 ps
T352	/workspace/coverage/default/44.chip_sw_all_escalation_resets.2471484515			Jul 10 08:28:28 PM PDT 24	Jul 10 08:37:17 PM PDT 24	4101244040 ps
T112	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.214388637			Jul 10 08:11:37 PM PDT 24	Jul 10 09:32:17 PM PDT 24	28928980415 ps
T666	/workspace/coverage/default/35.chip_sw_all_escalation_resets.1472175824			Jul 10 08:26:41 PM PDT 24	Jul 10 08:39:03 PM PDT 24	5467642240 ps
T118	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3930857686			Jul 10 08:14:26 PM PDT 24	Jul 10 08:23:10 PM PDT 24	4499241841 ps
T700	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.764982583			Jul 10 08:27:22 PM PDT 24	Jul 10 08:33:10 PM PDT 24	3768638264 ps
T353	/workspace/coverage/default/67.chip_sw_all_escalation_resets.91912425			Jul 10 08:29:11 PM PDT 24	Jul 10 08:36:34 PM PDT 24	5380000696 ps
T369	/workspace/coverage/default/2.rom_raw_unlock.1183174149			Jul 10 08:21:58 PM PDT 24	Jul 10 08:26:02 PM PDT 24	5402528801 ps
T898	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3808563373			Jul 10 08:24:29 PM PDT 24	Jul 10 09:08:36 PM PDT 24	13347887904 ps
T732	/workspace/coverage/default/31.chip_sw_all_escalation_resets.2053040241			Jul 10 08:27:09 PM PDT 24	Jul 10 08:40:59 PM PDT 24	6300792540 ps
T239	/workspace/coverage/default/2.chip_sw_edn_boot_mode.1154381346			Jul 10 08:16:19 PM PDT 24	Jul 10 08:27:04 PM PDT 24	2762328816 ps
T899	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3042488241			Jul 10 08:05:39 PM PDT 24	Jul 10 08:15:50 PM PDT 24	5671893484 ps
T900	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3503582352			Jul 10 08:05:11 PM PDT 24	Jul 10 09:45:36 PM PDT 24	22542350547 ps
T901	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.4274649676			Jul 10 07:56:59 PM PDT 24	Jul 10 08:06:13 PM PDT 24	5154530163 ps
T173	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3077063024			Jul 10 08:10:13 PM PDT 24	Jul 10 08:21:20 PM PDT 24	8481574500 ps
T199	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3866189134			Jul 10 08:01:06 PM PDT 24	Jul 10 10:53:54 PM PDT 24	58324166207 ps
T56	/workspace/coverage/default/0.chip_sw_alert_test.1413913050			Jul 10 07:59:37 PM PDT 24	Jul 10 08:05:33 PM PDT 24	3025560510 ps
T902	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3287269174			Jul 10 08:16:24 PM PDT 24	Jul 10 08:42:50 PM PDT 24	7853767100 ps
T30	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2192098478			Jul 10 08:04:46 PM PDT 24	Jul 10 08:13:41 PM PDT 24	6239780850 ps
T903	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.3437996183			Jul 10 07:57:52 PM PDT 24	Jul 10 08:03:56 PM PDT 24	2222808288 ps
T294	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1619060364			Jul 10 08:08:15 PM PDT 24	Jul 10 08:51:10 PM PDT 24	9999644750 ps
T904	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.226604541			Jul 10 08:22:32 PM PDT 24	Jul 10 08:32:16 PM PDT 24	3793641352 ps
T290	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2809815876			Jul 10 08:12:01 PM PDT 24	Jul 10 08:48:19 PM PDT 24	12386187280 ps
T346	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2994458903			Jul 10 07:57:41 PM PDT 24	Jul 10 08:02:02 PM PDT 24	3232953804 ps
T905	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2633515888			Jul 10 08:15:56 PM PDT 24	Jul 10 09:19:48 PM PDT 24	19145047486 ps
T906	/workspace/coverage/default/2.chip_sw_flash_crash_alert.325589897			Jul 10 08:20:49 PM PDT 24	Jul 10 08:29:31 PM PDT 24	5118849960 ps
T907	/workspace/coverage/default/1.chip_sw_example_flash.3941720401			Jul 10 08:00:38 PM PDT 24	Jul 10 08:05:31 PM PDT 24	3070095710 ps
T142	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1067603960			Jul 10 08:03:28 PM PDT 24	Jul 10 08:11:36 PM PDT 24	7061408230 ps
T908	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1869304762			Jul 10 08:00:44 PM PDT 24	Jul 10 08:05:14 PM PDT 24	2587763012 ps
T909	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2063644205			Jul 10 08:06:08 PM PDT 24	Jul 10 08:52:27 PM PDT 24	11442297568 ps
T248	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.826828128			Jul 10 07:58:12 PM PDT 24	Jul 10 08:05:54 PM PDT 24	4139094586 ps
T167	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.739202706			Jul 10 07:56:18 PM PDT 24	Jul 10 07:58:51 PM PDT 24	2910707734 ps
T910	/workspace/coverage/default/2.chip_sw_csrng_smoketest.2113524999			Jul 10 08:20:45 PM PDT 24	Jul 10 08:23:57 PM PDT 24	2479728200 ps
T165	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3909920329			Jul 10 08:25:48 PM PDT 24	Jul 10 09:32:55 PM PDT 24	15451121384 ps
T716	/workspace/coverage/default/47.chip_sw_all_escalation_resets.3778325431			Jul 10 08:28:02 PM PDT 24	Jul 10 08:38:39 PM PDT 24	4099451020 ps
T911	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3823406090			Jul 10 08:11:30 PM PDT 24	Jul 10 08:35:01 PM PDT 24	5716681670 ps
T341	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3427917715			Jul 10 08:12:19 PM PDT 24	Jul 10 08:25:41 PM PDT 24	5586135964 ps
T718	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.605167215			Jul 10 08:28:38 PM PDT 24	Jul 10 08:33:52 PM PDT 24	3287585666 ps
T368	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1342514453			Jul 10 08:14:15 PM PDT 24	Jul 10 09:28:34 PM PDT 24	44007212920 ps
T45	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1533033775			Jul 10 07:57:34 PM PDT 24	Jul 10 08:08:20 PM PDT 24	6131688120 ps
T129	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.818245450			Jul 10 08:12:17 PM PDT 24	Jul 10 08:21:56 PM PDT 24	6800552198 ps
T912	/workspace/coverage/default/1.chip_sw_aes_masking_off.275965996			Jul 10 08:08:32 PM PDT 24	Jul 10 08:13:01 PM PDT 24	3127017866 ps
T913	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.1643876308			Jul 10 08:16:41 PM PDT 24	Jul 10 08:21:39 PM PDT 24	3063255728 ps
T914	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.4064323126			Jul 10 08:21:40 PM PDT 24	Jul 10 08:26:00 PM PDT 24	3058012600 ps
T21	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.37558959			Jul 10 07:57:44 PM PDT 24	Jul 10 08:03:22 PM PDT 24	3151318171 ps
T302	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1585486242			Jul 10 08:14:55 PM PDT 24	Jul 10 09:45:03 PM PDT 24	48544433172 ps
T682	/workspace/coverage/default/46.chip_sw_all_escalation_resets.3636550041			Jul 10 08:28:13 PM PDT 24	Jul 10 08:37:22 PM PDT 24	5781062786 ps
T915	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1571258869			Jul 10 08:10:41 PM PDT 24	Jul 10 08:21:32 PM PDT 24	6978272196 ps
T734	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.4161172653			Jul 10 08:26:11 PM PDT 24	Jul 10 08:31:50 PM PDT 24	3600621398 ps
T228	/workspace/coverage/default/77.chip_sw_all_escalation_resets.1632522102			Jul 10 08:30:54 PM PDT 24	Jul 10 08:41:56 PM PDT 24	5550550868 ps
T152	/workspace/coverage/default/0.chip_plic_all_irqs_10.2290309615			Jul 10 08:03:07 PM PDT 24	Jul 10 08:10:36 PM PDT 24	3836946288 ps
T916	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2977809022			Jul 10 08:11:58 PM PDT 24	Jul 10 08:15:38 PM PDT 24	2054942000 ps
T335	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1080220196			Jul 10 08:01:59 PM PDT 24	Jul 10 08:09:26 PM PDT 24	3505568088 ps
T917	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3720448915			Jul 10 08:03:43 PM PDT 24	Jul 10 09:04:44 PM PDT 24	15900366944 ps
T360	/workspace/coverage/default/43.chip_sw_all_escalation_resets.3022803481			Jul 10 08:30:13 PM PDT 24	Jul 10 08:41:29 PM PDT 24	4463969950 ps
T410	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1835972839			Jul 10 08:17:05 PM PDT 24	Jul 10 08:25:18 PM PDT 24	9547127903 ps
T293	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.87463243			Jul 10 07:55:35 PM PDT 24	Jul 10 08:14:35 PM PDT 24	6788824686 ps
T329	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1950338665			Jul 10 08:24:53 PM PDT 24	Jul 10 08:37:17 PM PDT 24	4226296640 ps
T918	/workspace/coverage/default/2.chip_sw_edn_kat.259962609			Jul 10 08:16:00 PM PDT 24	Jul 10 08:28:02 PM PDT 24	3151788604 ps
T754	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1563331944			Jul 10 08:27:56 PM PDT 24	Jul 10 08:33:38 PM PDT 24	3898444920 ps
T204	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3498268879			Jul 10 08:15:03 PM PDT 24	Jul 10 08:21:22 PM PDT 24	3894590807 ps
T292	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1666995699			Jul 10 07:57:24 PM PDT 24	Jul 10 08:44:27 PM PDT 24	11495106014 ps
T28	/workspace/coverage/default/1.chip_sw_gpio.1189189013			Jul 10 08:03:49 PM PDT 24	Jul 10 08:11:35 PM PDT 24	4512824456 ps
T919	/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2969125428			Jul 10 07:59:18 PM PDT 24	Jul 10 08:35:32 PM PDT 24	27831145824 ps
T236	/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.4074240971			Jul 10 07:59:23 PM PDT 24	Jul 10 08:41:28 PM PDT 24	24642235998 ps