Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	496	1			T72	3		T74	1		T448	2
all_values[1]	503	1			T72	2		T448	1		T422	2
all_values[2]	538	1			T72	3		T73	1		T448	2
all_values[3]	510	1			T72	3		T422	1		T739	1
all_values[4]	501	1			T72	5		T448	3		T813	2
all_values[5]	455	1			T72	3		T74	2		T448	2
all_values[6]	495	1			T72	2		T73	1		T448	2
all_values[7]	436	1			T72	2		T448	4		T424	1
all_values[8]	486	1			T72	1		T73	1		T74	1
all_values[9]	492	1			T72	3		T74	1		T448	1
all_values[10]	471	1			T74	1		T448	1		T423	1
all_values[11]	464	1			T72	2		T424	3		T427	1
all_values[12]	531	1			T72	2		T424	2		T428	1
all_values[13]	486	1			T72	3		T73	1		T448	1
all_values[14]	494	1			T72	5		T423	2		T424	1
all_values[15]	529	1			T72	4		T448	1		T423	1
all_values[16]	493	1			T72	3		T424	1		T427	1
all_values[17]	472	1			T72	3		T448	1		T422	1
all_values[18]	500	1			T72	4		T73	1		T448	1
all_values[19]	483	1			T72	4		T424	1		T835	1
all_values[20]	508	1			T72	2		T73	1		T448	1
all_values[21]	451	1			T72	1		T448	3		T422	1
all_values[22]	515	1			T72	3		T73	1		T74	1
all_values[23]	494	1			T448	1		T427	1		T428	1
all_values[24]	515	1			T72	3		T74	1		T740	1
all_values[25]	504	1			T72	3		T73	2		T448	2
all_values[26]	527	1			T72	2		T73	1		T448	1
all_values[27]	484	1			T72	1		T448	3		T423	1
all_values[28]	493	1			T72	2		T448	1		T423	2
all_values[29]	507	1			T72	1		T73	1		T448	2
all_values[30]	478	1			T72	2		T73	1		T74	1
all_values[31]	508	1			T72	2		T73	1		T448	3
all_values[32]	462	1			T72	1		T73	2		T448	3
all_values[33]	465	1			T72	3		T448	5		T422	2
all_values[34]	491	1			T72	3		T424	2		T427	1
all_values[35]	502	1			T72	1		T74	2		T448	1
all_values[36]	531	1			T72	4		T73	1		T74	1
all_values[37]	493	1			T72	2		T74	1		T448	1
all_values[38]	476	1			T72	2		T448	1		T422	1
all_values[39]	508	1			T448	2		T673	5		T492	7
all_values[40]	478	1			T72	2		T739	2		T427	1
all_values[41]	506	1			T72	3		T448	1		T422	1
all_values[42]	515	1			T72	1		T74	1		T738	2
all_values[43]	519	1			T72	1		T424	3		T428	1
all_values[44]	452	1			T72	5		T448	2		T422	1
all_values[45]	506	1			T72	1		T73	1		T74	2
all_values[46]	457	1			T72	1		T73	1		T74	1
all_values[47]	466	1			T72	4		T448	1		T424	2
all_values[48]	514	1			T738	1		T448	2		T739	1
all_values[49]	537	1			T72	1		T448	2		T422	3