Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3467	1			T72	18		T448	29		T424	23
all_values[1]	3521	1			T72	18		T448	24		T525	1
all_values[2]	3589	1			T72	15		T448	25		T424	21
all_values[3]	3616	1			T72	20		T448	28		T525	1
all_values[4]	3526	1			T72	20		T448	33		T525	1
all_values[5]	3608	1			T72	21		T448	23		T424	25
all_values[6]	3592	1			T72	22		T448	25		T424	19
all_values[7]	3520	1			T72	22		T448	20		T525	2
all_values[8]	3640	1			T72	17		T448	26		T525	2
all_values[9]	3600	1			T72	20		T448	27		T525	2
all_values[10]	3659	1			T72	20		T448	26		T525	1
all_values[11]	3563	1			T72	18		T448	19		T424	20
all_values[12]	3452	1			T72	17		T448	23		T525	2
all_values[13]	3708	1			T72	22		T448	21		T525	1
all_values[14]	3635	1			T72	12		T448	29		T424	12
all_values[15]	3638	1			T72	28		T448	24		T424	20
all_values[16]	3668	1			T72	22		T448	22		T525	1
all_values[17]	3581	1			T72	29		T448	27		T525	1
all_values[18]	3629	1			T72	18		T448	18		T525	1
all_values[19]	3640	1			T72	21		T448	23		T525	1
all_values[20]	3577	1			T72	18		T448	19		T424	13
all_values[21]	3556	1			T72	21		T448	25		T525	2
all_values[22]	3522	1			T72	14		T448	16		T424	14
all_values[23]	3559	1			T72	19		T448	30		T525	2
all_values[24]	3555	1			T72	11		T448	27		T525	3
all_values[25]	3640	1			T72	23		T448	32		T424	13
all_values[26]	3700	1			T72	23		T448	30		T525	2
all_values[27]	3564	1			T72	20		T448	32		T525	3
all_values[28]	3634	1			T72	20		T448	17		T424	16
all_values[29]	3513	1			T72	21		T448	27		T525	1
all_values[30]	3678	1			T72	26		T448	28		T525	3
all_values[31]	3573	1			T72	26		T448	28		T525	1
all_values[32]	3553	1			T72	22		T448	24		T525	4
all_values[33]	3644	1			T72	32		T448	29		T525	1
all_values[34]	3725	1			T72	21		T448	27		T525	3
all_values[35]	3590	1			T72	15		T448	31		T525	1
all_values[36]	3630	1			T72	18		T448	15		T424	20
all_values[37]	3498	1			T72	19		T448	21		T525	2
all_values[38]	3591	1			T72	21		T448	26		T525	2
all_values[39]	3472	1			T72	19		T448	20		T424	13
all_values[40]	3633	1			T72	23		T448	31		T525	1
all_values[41]	3648	1			T72	19		T448	24		T424	14
all_values[42]	3653	1			T72	16		T448	31		T525	3
all_values[43]	3594	1			T72	20		T448	16		T525	2
all_values[44]	3704	1			T72	24		T448	20		T525	1
all_values[45]	3542	1			T72	15		T448	20		T525	1
all_values[46]	3508	1			T72	19		T448	29		T525	2
all_values[47]	3657	1			T72	24		T448	26		T525	2
all_values[48]	3605	1			T72	21		T448	23		T525	2
all_values[49]	3694	1			T72	28		T448	18		T525	1
all_values[50]	3709	1			T72	17		T448	23		T525	3
all_values[51]	3598	1			T72	28		T448	21		T424	11
all_values[52]	3526	1			T72	18		T448	20		T525	1
all_values[53]	3575	1			T72	20		T448	29		T525	3
all_values[54]	3583	1			T72	18		T448	30		T525	2
all_values[55]	3599	1			T72	21		T448	15		T525	5
all_values[56]	3637	1			T72	21		T448	24		T424	20
all_values[57]	3639	1			T72	24		T448	31		T525	1
all_values[58]	3608	1			T72	19		T448	31		T525	2
all_values[59]	3709	1			T72	18		T448	25		T525	3
all_values[60]	3542	1			T72	17		T448	27		T424	13
all_values[61]	3534	1			T72	15		T448	20		T525	2
all_values[62]	3576	1			T72	22		T448	27		T525	1
all_values[63]	3500	1			T72	17		T448	24		T525	1