Go
back
LINE 19359
EXPRESSION (mio_pad_attr_44_we & mio_pad_attr_regwen_44_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T505,T485,T506 |
LINE 19528
EXPRESSION (mio_pad_attr_45_we & mio_pad_attr_regwen_45_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T450,T507,T460 |
LINE 19697
EXPRESSION (mio_pad_attr_46_we & mio_pad_attr_regwen_46_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T429,T465,T508 |
LINE 20330
EXPRESSION (dio_pad_attr_0_we & dio_pad_attr_regwen_0_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T6 |
LINE 20499
EXPRESSION (dio_pad_attr_1_we & dio_pad_attr_regwen_1_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T6 |
LINE 20668
EXPRESSION (dio_pad_attr_2_we & dio_pad_attr_regwen_2_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T24,T25,T26 |
LINE 20837
EXPRESSION (dio_pad_attr_3_we & dio_pad_attr_regwen_3_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T24,T25,T26 |
LINE 21006
EXPRESSION (dio_pad_attr_4_we & dio_pad_attr_regwen_4_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T24,T25,T26 |
LINE 21175
EXPRESSION (dio_pad_attr_5_we & dio_pad_attr_regwen_5_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T24,T25,T26 |
LINE 21344
EXPRESSION (dio_pad_attr_6_we & dio_pad_attr_regwen_6_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T428,T421,T507 |
LINE 21513
EXPRESSION (dio_pad_attr_7_we & dio_pad_attr_regwen_7_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T431,T499,T509 |
LINE 21682
EXPRESSION (dio_pad_attr_8_we & dio_pad_attr_regwen_8_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T450,T507,T510 |
LINE 21851
EXPRESSION (dio_pad_attr_9_we & dio_pad_attr_regwen_9_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T492,T468,T481 |
LINE 22020
EXPRESSION (dio_pad_attr_10_we & dio_pad_attr_regwen_10_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T45,T46,T47 |
LINE 22189
EXPRESSION (dio_pad_attr_11_we & dio_pad_attr_regwen_11_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T45,T46,T47 |
LINE 22358
EXPRESSION (dio_pad_attr_12_we & dio_pad_attr_regwen_12_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T511,T455,T485 |
LINE 22527
EXPRESSION (dio_pad_attr_13_we & dio_pad_attr_regwen_13_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T420,T512,T452 |
LINE 22696
EXPRESSION (dio_pad_attr_14_we & dio_pad_attr_regwen_14_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T25,T43,T44 |
LINE 22865
EXPRESSION (dio_pad_attr_15_we & dio_pad_attr_regwen_15_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T25,T43,T44 |
LINE 25669
EXPRESSION (mio_pad_sleep_en_0_we & mio_pad_sleep_regwen_0_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T146,T147 |
1 | 1 | Covered | T2,T21,T9 |
LINE 25701
EXPRESSION (mio_pad_sleep_en_1_we & mio_pad_sleep_regwen_1_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T417,T371,T134 |
1 | 1 | Covered | T2,T21,T9 |
LINE 25733
EXPRESSION (mio_pad_sleep_en_2_we & mio_pad_sleep_regwen_2_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T373 |
1 | 1 | Covered | T2,T21,T9 |
LINE 25765
EXPRESSION (mio_pad_sleep_en_3_we & mio_pad_sleep_regwen_3_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T417 |
1 | 1 | Covered | T2,T21,T9 |
LINE 25797
EXPRESSION (mio_pad_sleep_en_4_we & mio_pad_sleep_regwen_4_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T374 |
1 | 1 | Covered | T2,T21,T9 |
LINE 25829
EXPRESSION (mio_pad_sleep_en_5_we & mio_pad_sleep_regwen_5_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T417 |
1 | 1 | Covered | T2,T21,T9 |
LINE 25861
EXPRESSION (mio_pad_sleep_en_6_we & mio_pad_sleep_regwen_6_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T375,T373 |
1 | 1 | Covered | T2,T21,T9 |
LINE 25893
EXPRESSION (mio_pad_sleep_en_7_we & mio_pad_sleep_regwen_7_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T373,T370 |
1 | 1 | Covered | T2,T21,T9 |
LINE 25925
EXPRESSION (mio_pad_sleep_en_8_we & mio_pad_sleep_regwen_8_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T374,T375 |
1 | 1 | Covered | T2,T21,T22 |
LINE 25957
EXPRESSION (mio_pad_sleep_en_9_we & mio_pad_sleep_regwen_9_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T146,T147 |
1 | 1 | Covered | T2,T21,T22 |
LINE 25989
EXPRESSION (mio_pad_sleep_en_10_we & mio_pad_sleep_regwen_10_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T373,T371,T406 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26021
EXPRESSION (mio_pad_sleep_en_11_we & mio_pad_sleep_regwen_11_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T375,T417,T373 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26053
EXPRESSION (mio_pad_sleep_en_12_we & mio_pad_sleep_regwen_12_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T145,T146 |
1 | 1 | Covered | T21,T22,T23 |
LINE 26085
EXPRESSION (mio_pad_sleep_en_13_we & mio_pad_sleep_regwen_13_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T146,T147 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26117
EXPRESSION (mio_pad_sleep_en_14_we & mio_pad_sleep_regwen_14_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T417,T373 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26149
EXPRESSION (mio_pad_sleep_en_15_we & mio_pad_sleep_regwen_15_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T374,T417 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26181
EXPRESSION (mio_pad_sleep_en_16_we & mio_pad_sleep_regwen_16_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T146,T147 |
1 | 1 | Covered | T21,T22,T23 |
LINE 26213
EXPRESSION (mio_pad_sleep_en_17_we & mio_pad_sleep_regwen_17_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T374,T417 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26245
EXPRESSION (mio_pad_sleep_en_18_we & mio_pad_sleep_regwen_18_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T146,T374 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26277
EXPRESSION (mio_pad_sleep_en_19_we & mio_pad_sleep_regwen_19_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T374,T416 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26309
EXPRESSION (mio_pad_sleep_en_20_we & mio_pad_sleep_regwen_20_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T371,T134 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26341
EXPRESSION (mio_pad_sleep_en_21_we & mio_pad_sleep_regwen_21_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T417 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26373
EXPRESSION (mio_pad_sleep_en_22_we & mio_pad_sleep_regwen_22_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T417 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26405
EXPRESSION (mio_pad_sleep_en_23_we & mio_pad_sleep_regwen_23_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T374,T371 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26437
EXPRESSION (mio_pad_sleep_en_24_we & mio_pad_sleep_regwen_24_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T417,T373,T371 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26469
EXPRESSION (mio_pad_sleep_en_25_we & mio_pad_sleep_regwen_25_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T146,T375 |
1 | 1 | Covered | T21,T22,T23 |
LINE 26501
EXPRESSION (mio_pad_sleep_en_26_we & mio_pad_sleep_regwen_26_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T146,T375 |
1 | 1 | Covered | T21,T22,T23 |
LINE 26533
EXPRESSION (mio_pad_sleep_en_27_we & mio_pad_sleep_regwen_27_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T145,T146 |
1 | 1 | Covered | T21,T22,T23 |
LINE 26565
EXPRESSION (mio_pad_sleep_en_28_we & mio_pad_sleep_regwen_28_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T147,T375 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26597
EXPRESSION (mio_pad_sleep_en_29_we & mio_pad_sleep_regwen_29_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T416,T370,T371 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26629
EXPRESSION (mio_pad_sleep_en_30_we & mio_pad_sleep_regwen_30_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T145,T146 |
1 | 1 | Covered | T21,T22,T23 |
LINE 26661
EXPRESSION (mio_pad_sleep_en_31_we & mio_pad_sleep_regwen_31_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T416 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26693
EXPRESSION (mio_pad_sleep_en_32_we & mio_pad_sleep_regwen_32_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T370,T371 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26725
EXPRESSION (mio_pad_sleep_en_33_we & mio_pad_sleep_regwen_33_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T417,T371 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26757
EXPRESSION (mio_pad_sleep_en_34_we & mio_pad_sleep_regwen_34_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T375,T416 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26789
EXPRESSION (mio_pad_sleep_en_35_we & mio_pad_sleep_regwen_35_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T146,T147 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26821
EXPRESSION (mio_pad_sleep_en_36_we & mio_pad_sleep_regwen_36_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T417,T371 |
1 | 1 | Covered | T21,T22,T23 |
LINE 26853
EXPRESSION (mio_pad_sleep_en_37_we & mio_pad_sleep_regwen_37_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T147,T416 |
1 | 1 | Covered | T21,T22,T23 |
LINE 26885
EXPRESSION (mio_pad_sleep_en_38_we & mio_pad_sleep_regwen_38_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T417 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26917
EXPRESSION (mio_pad_sleep_en_39_we & mio_pad_sleep_regwen_39_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T374,T417 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26949
EXPRESSION (mio_pad_sleep_en_40_we & mio_pad_sleep_regwen_40_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T374,T373 |
1 | 1 | Covered | T2,T21,T22 |
LINE 26981
EXPRESSION (mio_pad_sleep_en_41_we & mio_pad_sleep_regwen_41_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T371,T405 |
1 | 1 | Covered | T2,T21,T22 |
LINE 27013
EXPRESSION (mio_pad_sleep_en_42_we & mio_pad_sleep_regwen_42_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T374,T417 |
1 | 1 | Covered | T2,T21,T22 |
LINE 27045
EXPRESSION (mio_pad_sleep_en_43_we & mio_pad_sleep_regwen_43_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T373,T371 |
1 | 1 | Covered | T21,T22,T23 |
LINE 27077
EXPRESSION (mio_pad_sleep_en_44_we & mio_pad_sleep_regwen_44_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T146,T147 |
1 | 1 | Covered | T21,T22,T23 |
LINE 27109
EXPRESSION (mio_pad_sleep_en_45_we & mio_pad_sleep_regwen_45_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T373,T370 |
1 | 1 | Covered | T2,T21,T22 |
LINE 27141
EXPRESSION (mio_pad_sleep_en_46_we & mio_pad_sleep_regwen_46_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T146,T373 |
1 | 1 | Covered | T2,T21,T22 |
LINE 27173
EXPRESSION (mio_pad_sleep_mode_0_we & mio_pad_sleep_regwen_0_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T417 |
1 | 1 | Covered | T2,T21,T9 |
LINE 27205
EXPRESSION (mio_pad_sleep_mode_1_we & mio_pad_sleep_regwen_1_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T417,T373,T371 |
1 | 1 | Covered | T2,T21,T9 |
LINE 27237
EXPRESSION (mio_pad_sleep_mode_2_we & mio_pad_sleep_regwen_2_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T417 |
1 | 1 | Covered | T2,T21,T9 |
LINE 27269
EXPRESSION (mio_pad_sleep_mode_3_we & mio_pad_sleep_regwen_3_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T417,T370 |
1 | 1 | Covered | T2,T21,T9 |
LINE 27301
EXPRESSION (mio_pad_sleep_mode_4_we & mio_pad_sleep_regwen_4_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T374,T373 |
1 | 1 | Covered | T2,T21,T9 |
LINE 27333
EXPRESSION (mio_pad_sleep_mode_5_we & mio_pad_sleep_regwen_5_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T417 |
1 | 1 | Covered | T2,T21,T9 |
LINE 27365
EXPRESSION (mio_pad_sleep_mode_6_we & mio_pad_sleep_regwen_6_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T375,T373 |
1 | 1 | Covered | T2,T21,T9 |
LINE 27397
EXPRESSION (mio_pad_sleep_mode_7_we & mio_pad_sleep_regwen_7_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T375,T373 |
1 | 1 | Covered | T2,T21,T9 |
LINE 27429
EXPRESSION (mio_pad_sleep_mode_8_we & mio_pad_sleep_regwen_8_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T374,T417 |
1 | 1 | Covered | T2,T21,T22 |
LINE 27461
EXPRESSION (mio_pad_sleep_mode_9_we & mio_pad_sleep_regwen_9_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T146,T147 |
1 | 1 | Covered | T2,T21,T22 |
LINE 27493
EXPRESSION (mio_pad_sleep_mode_10_we & mio_pad_sleep_regwen_10_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T371,T449,T406 |
1 | 1 | Covered | T2,T21,T22 |
LINE 27525
EXPRESSION (mio_pad_sleep_mode_11_we & mio_pad_sleep_regwen_11_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T374,T375 |
1 | 1 | Covered | T2,T21,T22 |
LINE 27557
EXPRESSION (mio_pad_sleep_mode_12_we & mio_pad_sleep_regwen_12_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T145,T146 |
1 | 1 | Covered | T21,T22,T23 |
LINE 27589
EXPRESSION (mio_pad_sleep_mode_13_we & mio_pad_sleep_regwen_13_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T145,T146 |
1 | 1 | Covered | T21,T22,T23 |
LINE 27621
EXPRESSION (mio_pad_sleep_mode_14_we & mio_pad_sleep_regwen_14_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T417,T373 |
1 | 1 | Covered | T2,T21,T22 |
LINE 27653
EXPRESSION (mio_pad_sleep_mode_15_we & mio_pad_sleep_regwen_15_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T417,T370 |
1 | 1 | Covered | T21,T22,T23 |
LINE 27685
EXPRESSION (mio_pad_sleep_mode_16_we & mio_pad_sleep_regwen_16_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T146,T147 |
1 | 1 | Covered | T21,T22,T23 |
LINE 27717
EXPRESSION (mio_pad_sleep_mode_17_we & mio_pad_sleep_regwen_17_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T374,T417 |
1 | 1 | Covered | T2,T21,T22 |
LINE 27749
EXPRESSION (mio_pad_sleep_mode_18_we & mio_pad_sleep_regwen_18_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T146,T373 |
1 | 1 | Covered | T21,T22,T23 |
LINE 27781
EXPRESSION (mio_pad_sleep_mode_19_we & mio_pad_sleep_regwen_19_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T374,T416 |
1 | 1 | Covered | T2,T21,T22 |
LINE 27813
EXPRESSION (mio_pad_sleep_mode_20_we & mio_pad_sleep_regwen_20_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T371,T134 |
1 | 1 | Covered | T2,T21,T22 |
LINE 27845
EXPRESSION (mio_pad_sleep_mode_21_we & mio_pad_sleep_regwen_21_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T417 |
1 | 1 | Covered | T2,T21,T22 |
LINE 27877
EXPRESSION (mio_pad_sleep_mode_22_we & mio_pad_sleep_regwen_22_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T417 |
1 | 1 | Covered | T2,T21,T22 |
LINE 27909
EXPRESSION (mio_pad_sleep_mode_23_we & mio_pad_sleep_regwen_23_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T374,T373 |
1 | 1 | Covered | T2,T21,T22 |
LINE 27941
EXPRESSION (mio_pad_sleep_mode_24_we & mio_pad_sleep_regwen_24_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T373,T134,T406 |
1 | 1 | Covered | T2,T21,T22 |
LINE 27973
EXPRESSION (mio_pad_sleep_mode_25_we & mio_pad_sleep_regwen_25_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T146,T416 |
1 | 1 | Covered | T21,T22,T23 |
LINE 28005
EXPRESSION (mio_pad_sleep_mode_26_we & mio_pad_sleep_regwen_26_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T145,T146 |
1 | 1 | Covered | T21,T22,T23 |
LINE 28037
EXPRESSION (mio_pad_sleep_mode_27_we & mio_pad_sleep_regwen_27_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T145,T146 |
1 | 1 | Covered | T21,T22,T23 |
LINE 28069
EXPRESSION (mio_pad_sleep_mode_28_we & mio_pad_sleep_regwen_28_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T417,T373 |
1 | 1 | Covered | T2,T21,T22 |
LINE 28101
EXPRESSION (mio_pad_sleep_mode_29_we & mio_pad_sleep_regwen_29_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T416,T373,T370 |
1 | 1 | Covered | T2,T21,T22 |
LINE 28133
EXPRESSION (mio_pad_sleep_mode_30_we & mio_pad_sleep_regwen_30_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T146,T374 |
1 | 1 | Covered | T2,T21,T22 |
LINE 28165
EXPRESSION (mio_pad_sleep_mode_31_we & mio_pad_sleep_regwen_31_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T375 |
1 | 1 | Covered | T2,T21,T22 |
LINE 28197
EXPRESSION (mio_pad_sleep_mode_32_we & mio_pad_sleep_regwen_32_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T374,T371 |
1 | 1 | Covered | T2,T21,T22 |
LINE 28229
EXPRESSION (mio_pad_sleep_mode_33_we & mio_pad_sleep_regwen_33_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T375 |
1 | 1 | Covered | T2,T21,T22 |
LINE 28261
EXPRESSION (mio_pad_sleep_mode_34_we & mio_pad_sleep_regwen_34_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T146,T416 |
1 | 1 | Covered | T21,T22,T23 |
LINE 28293
EXPRESSION (mio_pad_sleep_mode_35_we & mio_pad_sleep_regwen_35_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T146,T147 |
1 | 1 | Covered | T2,T21,T22 |
LINE 28325
EXPRESSION (mio_pad_sleep_mode_36_we & mio_pad_sleep_regwen_36_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T374,T416 |
1 | 1 | Covered | T21,T22,T23 |
LINE 28357
EXPRESSION (mio_pad_sleep_mode_37_we & mio_pad_sleep_regwen_37_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T145,T147 |
1 | 1 | Covered | T21,T22,T23 |
LINE 28389
EXPRESSION (mio_pad_sleep_mode_38_we & mio_pad_sleep_regwen_38_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T417 |
1 | 1 | Covered | T2,T21,T22 |
LINE 28421
EXPRESSION (mio_pad_sleep_mode_39_we & mio_pad_sleep_regwen_39_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T374,T371 |
1 | 1 | Covered | T2,T21,T22 |
LINE 28453
EXPRESSION (mio_pad_sleep_mode_40_we & mio_pad_sleep_regwen_40_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T147,T373 |
1 | 1 | Covered | T2,T21,T22 |
LINE 28485
EXPRESSION (mio_pad_sleep_mode_41_we & mio_pad_sleep_regwen_41_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T146,T147 |
1 | 1 | Covered | T21,T22,T23 |
LINE 28517
EXPRESSION (mio_pad_sleep_mode_42_we & mio_pad_sleep_regwen_42_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T374,T417 |
1 | 1 | Covered | T2,T21,T22 |
LINE 28549
EXPRESSION (mio_pad_sleep_mode_43_we & mio_pad_sleep_regwen_43_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T374,T371,T449 |
1 | 1 | Covered | T2,T21,T22 |
LINE 28581
EXPRESSION (mio_pad_sleep_mode_44_we & mio_pad_sleep_regwen_44_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T147,T371 |
1 | 1 | Covered | T21,T22,T23 |
LINE 28613
EXPRESSION (mio_pad_sleep_mode_45_we & mio_pad_sleep_regwen_45_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T374,T373 |
1 | 1 | Covered | T2,T21,T22 |
LINE 28645
EXPRESSION (mio_pad_sleep_mode_46_we & mio_pad_sleep_regwen_46_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T146,T416 |
1 | 1 | Covered | T2,T21,T22 |
LINE 29576
EXPRESSION (dio_pad_sleep_en_0_we & dio_pad_sleep_regwen_0_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T416 |
1 | 1 | Covered | T2,T21,T22 |
LINE 29608
EXPRESSION (dio_pad_sleep_en_1_we & dio_pad_sleep_regwen_1_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T416 |
1 | 1 | Covered | T2,T21,T22 |
LINE 29640
EXPRESSION (dio_pad_sleep_en_2_we & dio_pad_sleep_regwen_2_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T146,T147 |
1 | 1 | Covered | T2,T21,T22 |
LINE 29672
EXPRESSION (dio_pad_sleep_en_3_we & dio_pad_sleep_regwen_3_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T146,T147 |
1 | 1 | Covered | T2,T21,T22 |
LINE 29704
EXPRESSION (dio_pad_sleep_en_4_we & dio_pad_sleep_regwen_4_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T374 |
1 | 1 | Covered | T2,T21,T22 |
LINE 29736
EXPRESSION (dio_pad_sleep_en_5_we & dio_pad_sleep_regwen_5_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T146,T147 |
1 | 1 | Covered | T2,T21,T22 |
LINE 29768
EXPRESSION (dio_pad_sleep_en_6_we & dio_pad_sleep_regwen_6_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T146,T147 |
1 | 1 | Covered | T21,T22,T23 |
LINE 29800
EXPRESSION (dio_pad_sleep_en_7_we & dio_pad_sleep_regwen_7_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T375,T416 |
1 | 1 | Covered | T2,T21,T22 |
LINE 29832
EXPRESSION (dio_pad_sleep_en_8_we & dio_pad_sleep_regwen_8_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T374,T371 |
1 | 1 | Covered | T2,T21,T22 |
LINE 29864
EXPRESSION (dio_pad_sleep_en_9_we & dio_pad_sleep_regwen_9_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T375,T417 |
1 | 1 | Covered | T2,T21,T22 |
LINE 29896
EXPRESSION (dio_pad_sleep_en_10_we & dio_pad_sleep_regwen_10_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T374 |
1 | 1 | Covered | T2,T21,T22 |
LINE 29928
EXPRESSION (dio_pad_sleep_en_11_we & dio_pad_sleep_regwen_11_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T370,T371 |
1 | 1 | Covered | T2,T21,T22 |
LINE 29960
EXPRESSION (dio_pad_sleep_en_12_we & dio_pad_sleep_regwen_12_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T374,T373 |
1 | 1 | Covered | T2,T21,T22 |
LINE 29992
EXPRESSION (dio_pad_sleep_en_13_we & dio_pad_sleep_regwen_13_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T416,T417,T373 |
1 | 1 | Covered | T2,T21,T22 |
LINE 30024
EXPRESSION (dio_pad_sleep_en_14_we & dio_pad_sleep_regwen_14_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T417,T371 |
1 | 1 | Covered | T2,T21,T22 |
LINE 30056
EXPRESSION (dio_pad_sleep_en_15_we & dio_pad_sleep_regwen_15_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T146,T371 |
1 | 1 | Covered | T21,T22,T23 |
LINE 30088
EXPRESSION (dio_pad_sleep_mode_0_we & dio_pad_sleep_regwen_0_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T416 |
1 | 1 | Covered | T2,T21,T22 |
LINE 30120
EXPRESSION (dio_pad_sleep_mode_1_we & dio_pad_sleep_regwen_1_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T146,T416 |
1 | 1 | Covered | T21,T22,T23 |
LINE 30152
EXPRESSION (dio_pad_sleep_mode_2_we & dio_pad_sleep_regwen_2_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T145,T146,T147 |
1 | 1 | Covered | T2,T21,T22 |
LINE 30184
EXPRESSION (dio_pad_sleep_mode_3_we & dio_pad_sleep_regwen_3_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T417 |
1 | 1 | Covered | T2,T21,T22 |
LINE 30216
EXPRESSION (dio_pad_sleep_mode_4_we & dio_pad_sleep_regwen_4_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T146,T147,T374 |
1 | 1 | Covered | T2,T21,T22 |
LINE 30248
EXPRESSION (dio_pad_sleep_mode_5_we & dio_pad_sleep_regwen_5_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T145,T146 |
1 | 1 | Covered | T21,T22,T23 |
LINE 30280
EXPRESSION (dio_pad_sleep_mode_6_we & dio_pad_sleep_regwen_6_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T2,T146,T417 |
1 | 1 | Covered | T21,T22,T23 |
LINE 30312
EXPRESSION (dio_pad_sleep_mode_7_we & dio_pad_sleep_regwen_7_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T147,T374,T375 |
1 | 1 | Covered | T2,T21,T22 |