39211701b5| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 4.880m | 3.070ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.720m | 2.248ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 3.880m | 2.295ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 4.401m | 2.706ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 6.802m | 8.150ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 10.483m | 5.938ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 1.005h | 30.995ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.450h | 64.251ms | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 2.172m | 2.771ms | 0 | 20 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.450h | 64.251ms | 4 | 5 | 80.00 |
| chip_csr_rw | 10.483m | 5.938ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 11.820s | 284.685us | 100 | 100 | 100.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 7.755m | 4.513ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 7.755m | 4.513ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 7.755m | 4.513ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 14.148m | 4.414ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 14.148m | 4.414ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 12.843m | 4.013ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 14.088m | 4.975ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 12.028m | 4.889ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 54.704m | 13.554ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 33.279m | 8.105ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 36.148m | 13.232ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 199 | 220 | 90.45 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.635m | 5.132ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.635m | 5.132ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 5.603m | 3.151ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 9.406m | 5.262ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 6.341m | 3.430ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 26.639m | 16.446ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 26.303m | 14.046ms | 4 | 5 | 80.00 | ||
| chip_tap_straps_rma | 25.428m | 13.916ms | 3 | 5 | 60.00 | ||
| chip_tap_straps_prod | 13.240m | 9.287ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 5.126m | 3.073ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 24.354m | 9.678ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 12.562m | 6.095ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 12.562m | 6.095ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 15.666m | 7.184ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 0 | 3 | 0.00 | ||
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 14.436m | 4.657ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 22.151m | 6.300ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.073h | 18.651ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.113m | 2.966ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 25.313m | 6.976ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.668m | 3.607ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 38.436m | 12.227ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.883m | 2.825ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.874m | 5.532ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 6.039m | 2.223ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 4.118m | 3.166ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 19.517m | 10.007ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.821m | 5.542ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 4.791m | 2.747ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.821m | 5.542ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 3.974m | 2.859ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.578m | 2.376ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 6.279m | 2.968ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 4.331m | 3.058ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.817m | 2.294ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 8.959m | 4.085ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 5.482m | 3.322ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 5.677m | 3.300ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 6.573m | 3.018ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 25.753m | 7.246ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 9.765m | 6.868ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 9.764m | 6.217ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.830m | 2.830ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 5.096m | 2.660ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 5.677m | 2.705ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 4.169m | 2.612ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 4.550m | 2.603ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 5.642m | 3.093ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 10.675m | 3.919ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 4.158h | 78.334ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 1.051h | 14.767ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 4.207m | 5.484ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 15.430m | 4.829ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 11.791m | 10.908ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 3.083h | 59.171ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.405h | 65.018ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 11.260m | 6.021ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 11.260m | 6.021ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.450h | 64.251ms | 4 | 5 | 80.00 |
| chip_same_csr_outstanding | 1.286h | 31.240ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.802m | 8.150ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 10.483m | 5.938ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.450h | 64.251ms | 4 | 5 | 80.00 |
| chip_same_csr_outstanding | 1.286h | 31.240ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.802m | 8.150ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 10.483m | 5.938ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.569m | 2.402ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 7.550s | 55.227us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 2.124m | 10.929ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 1.977m | 6.565ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 57.070s | 619.553us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 22.068m | 113.664ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 22.267m | 71.152ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 56.440s | 1.361ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 56.650s | 1.368ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.470m | 2.226ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 56.650s | 1.368ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.539m | 3.512ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 52.585m | 165.556ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.439m | 2.856ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 11.772m | 17.741ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 11.521m | 19.610ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 16.221m | 8.371ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 14.733m | 16.781ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 1.051h | 14.767ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 56.949m | 27.890ms | 2 | 3 | 66.67 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 1.118h | 15.451ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 50.234m | 10.997ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 57.762m | 15.469ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 1.195h | 15.997ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 1.017h | 15.900ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 59.007m | 14.701ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 46.309m | 11.442ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 57.335m | 15.962ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 1.251h | 15.103ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 1.005h | 15.760ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 1.094h | 14.623ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.503h | 17.545ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 1.630h | 23.891ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 1.769h | 23.978ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 1.701h | 23.916ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 1.587h | 23.210ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 1.364h | 17.639ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 1.715h | 23.633ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 1.657h | 24.034ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 1.725h | 23.963ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 1.673h | 22.542ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 49.434m | 10.897ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 1.166h | 14.324ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 55.223m | 14.926ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 1.330h | 14.870ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 1.012h | 13.874ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 55.691m | 11.262ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 54.188m | 14.608ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 1.019h | 15.648ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 57.568m | 15.303ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 1.242h | 13.745ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 1.013h | 12.202ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 1.094h | 16.046ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 1.190h | 15.368ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 1.094h | 15.920ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 1.138h | 14.652ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 1.119h | 14.683ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 1.289h | 14.216ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 1.099h | 14.740ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 1.100h | 16.939ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 6.406m | 3.018ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 5.113m | 2.966ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 4.909m | 3.114ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 5.036m | 3.387ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 48.715m | 11.893ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.415m | 18.903ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.415m | 18.903ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 7.115m | 4.848ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 9.765m | 6.868ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 7.115m | 4.848ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 18.632m | 8.684ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 18.632m | 8.684ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 8.635m | 7.937ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 10.931m | 5.560ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 15.332m | 6.166ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 5.036m | 3.387ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 4.957m | 3.063ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 4.509m | 2.575ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 8.699m | 5.061ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 8.974m | 5.129ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 12.973m | 5.174ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 11.032m | 5.553ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 29.562m | 10.422ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 12.506m | 4.281ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.164m | 4.451ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 14.332m | 4.620ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.645m | 4.664ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 14.128m | 4.322ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.064m | 4.237ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 15.666m | 7.184ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 20.232m | 10.842ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 14.332m | 4.620ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.645m | 4.664ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 14.436m | 4.657ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 22.151m | 6.300ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.073h | 18.651ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.113m | 2.966ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 25.313m | 6.976ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.668m | 3.607ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 38.436m | 12.227ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.883m | 2.825ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.874m | 5.532ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 6.039m | 2.223ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 5.691m | 2.949ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 13.357m | 5.586ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 19.878m | 7.446ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.073h | 24.729ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.710m | 2.832ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 4.744m | 2.955ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 43.185m | 12.198ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 6.466m | 3.267ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 10.230m | 4.956ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 34.300m | 24.469ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 6.924h | 167.140ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 15.666m | 7.184ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 10.232m | 4.790ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 7.952m | 3.818ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 14.873m | 6.172ms | 97 | 100 | 97.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 32.611m | 8.373ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 28.664m | 7.371ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 9.500m | 4.751ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 11.792m | 6.007ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 5.062m | 3.181ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 20.994m | 7.576ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 30.424m | 23.702ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 6.686m | 3.514ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 6.281m | 3.895ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 13.359m | 4.955ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 30.424m | 23.702ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 30.424m | 23.702ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.127h | 20.150ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.127h | 20.150ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 10.761m | 6.132ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.415m | 18.903ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 2.146h | 27.513ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 5.982m | 3.214ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 24.415m | 6.928ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 5.982m | 3.214ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 28.664m | 7.371ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.774m | 2.450ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 39.863m | 25.890ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 20.350m | 5.145ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 22.151m | 6.300ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 11.774m | 3.436ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 14.436m | 4.657ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.558h | 44.363ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 39.863m | 25.890ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 6.722m | 3.732ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 36.285m | 12.386ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.720m | 4.970ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.558h | 44.363ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.720m | 4.970ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.720m | 4.970ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 9.720m | 4.970ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.720m | 4.970ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 14.873m | 6.172ms | 97 | 100 | 97.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 3.481m | 5.583ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 23.250m | 5.715ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 11.871m | 5.299ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 11.871m | 5.299ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 6.713m | 3.135ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 5.668m | 3.607ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 4.957m | 3.063ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 6.427m | 3.049ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 31.900m | 7.562ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 15.744m | 4.917ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 17.053m | 5.351ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 15.166m | 5.515ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 10.687m | 3.917ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 36.285m | 12.386ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 38.436m | 12.227ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 47.036m | 11.495ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 48.715m | 11.893ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.268h | 16.350ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 4.975m | 2.840ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 5.914m | 2.454ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.883m | 2.825ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 36.285m | 12.386ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 22.972m | 11.785ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 6.078m | 2.252ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 5.494m | 2.457ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 4.509m | 2.575ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 10.689m | 5.233ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 26.639m | 16.446ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 25.428m | 13.916ms | 3 | 5 | 60.00 | ||
| chip_tap_straps_prod | 13.240m | 9.287ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 4.834m | 3.005ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 22.972m | 11.785ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 22.972m | 11.785ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 22.972m | 11.785ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 48.122m | 12.645ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 9.720m | 4.970ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.558h | 44.363ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 12.149m | 4.084ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 26.590m | 8.409ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 26.269m | 7.364ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 22.951m | 6.755ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 22.972m | 11.785ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 36.285m | 12.386ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 10.570m | 8.635ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 11.486m | 8.025ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 3.481m | 5.583ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 20.232m | 10.842ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 12.506m | 4.281ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.164m | 4.451ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 14.332m | 4.620ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.645m | 4.664ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 14.128m | 4.322ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.064m | 4.237ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 26.639m | 16.446ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 25.428m | 13.916ms | 3 | 5 | 60.00 | ||
| chip_tap_straps_prod | 13.240m | 9.287ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 10.613m | 15.551ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 2.709m | 2.920ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.914m | 3.597ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.587m | 3.967ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 5.607m | 3.818ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 49.353m | 27.313ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 10.613m | 15.551ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.624h | 46.421ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.751h | 50.676ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 18.407m | 7.732ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.717h | 48.432ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 49.353m | 27.313ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 1.955m | 2.377ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 1.985m | 2.690ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 2.261m | 2.673ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 22.972m | 11.785ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 39.863m | 25.890ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.865m | 3.799ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 36.285m | 12.386ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 11.129m | 4.575ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.117m | 2.631ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 39.863m | 25.890ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.865m | 3.799ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 36.285m | 12.386ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 11.129m | 4.575ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.117m | 2.631ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 22.972m | 11.785ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 10.526m | 4.606ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 4.834m | 3.005ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 12.149m | 4.084ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 26.590m | 8.409ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 26.269m | 7.364ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 22.951m | 6.755ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 22.972m | 11.785ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 3.481m | 5.583ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 3.481m | 5.583ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.582h | 28.669ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 10.575m | 7.108ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 31.683m | 20.968ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 9.515m | 7.464ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 14.234m | 7.012ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 14.187m | 5.943ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 28.210m | 22.185ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 26.062m | 12.810ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 18.632m | 8.684ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 23.630m | 12.017ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 10.908m | 4.852ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 10.575m | 7.108ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 8.047m | 5.076ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 58.975m | 38.476ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 7.790m | 6.240ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 9.221m | 5.155ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 39.779m | 26.075ms | 2 | 3 | 66.67 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 20.994m | 7.576ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 28.034m | 11.584ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 36.219m | 27.831ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 4.899m | 2.850ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 14.873m | 6.172ms | 97 | 100 | 97.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 10.570m | 8.635ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 10.570m | 8.635ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 28.034m | 11.584ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 39.779m | 26.075ms | 2 | 3 | 66.67 | ||
| chip_sw_pwrmgr_wdog_reset | 10.908m | 4.852ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 9.765m | 6.868ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 8.579m | 5.231ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 15.265m | 6.991ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 8.508m | 3.823ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 33.059m | 11.207ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 4.712m | 3.063ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 14.873m | 6.172ms | 97 | 100 | 97.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 32.322m | 7.773ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 22.604m | 6.150ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 11.558m | 4.500ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 14.054m | 4.882ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 4.740m | 2.666ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 5.383m | 2.781ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 1.051h | 14.767ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 12.792m | 7.458ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 9.810m | 4.963ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 9.580m | 3.533ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 4.796m | 2.759ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 11.129m | 4.575ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.874m | 5.532ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 16.241m | 8.158ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 14.385m | 7.986ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 11.486m | 8.025ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 14.873m | 6.172ms | 97 | 100 | 97.00 |
| chip_sw_data_integrity_escalation | 12.562m | 6.095ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 4.603m | 2.513ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 6.069m | 3.006ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 7.886m | 3.479ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 9.716m | 3.713ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 31.912m | 8.274ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 2.092h | 31.930ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 47.401m | 11.694ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 6.046m | 3.412ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 10.689m | 5.233ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 14.873m | 6.172ms | 97 | 100 | 97.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 7.973m | 3.092ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 33.059m | 11.207ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 10.289m | 4.855ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 9.739m | 4.413ms | 89 | 90 | 98.89 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 29.108m | 13.089ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 32.611m | 8.373ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 32.322m | 7.773ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 26.739m | 7.837ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.636h | 254.108ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 39.852m | 21.801ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 29.170m | 13.589ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 8.579m | 5.231ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 12.042m | 5.476ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 10.995m | 5.388ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 25.428m | 13.916ms | 3 | 5 | 60.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 10.613m | 15.551ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 2632 | 2644 | 99.55 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 6.672m | 3.308ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 4.029h | 72.180ms | 1 | 1 | 100.00 |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 0 | 3 | 0.00 | ||
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 38.734m | 12.249ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 35.130m | 11.285ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 36.178m | 11.826ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 33.100m | 35.696ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 42.060m | 24.642ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 38.156m | 27.805ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 1.407h | 16.082ms | 0 | 3 | 0.00 |
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 6.894m | 2.785ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 11.523m | 3.454ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 19.359m | 4.627ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 47.918m | 11.117ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 12.025m | 3.152ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 23.520m | 5.717ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | //sw/device/tests:i2c_host_override_test | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 4.445m | 3.376ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 13.582m | 6.083ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 8.746m | 5.973ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 6.940m | 5.445ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 28.034m | 11.584ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 14.873m | 6.172ms | 97 | 100 | 97.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_pass_through | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | chip_sw_spi_host_configuration | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_readback | chip_sw_sram_readback | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 14.148m | 4.414ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.446h | 18.856ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 38.734m | 12.249ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 35.130m | 11.285ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 36.178m | 11.826ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 11.231m | 4.435ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 39 | 48 | 81.25 | |||
| Unmapped tests | chip_sival_flash_info_access | 6.720m | 2.560ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 12.131m | 5.023ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 5.198m | 2.384ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 1.063h | 16.832ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 19.479m | 5.253ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 14.754m | 4.781ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 8.690m | 3.853ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 9.750m | 6.341ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 5.814m | 2.513ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 4.806m | 2.973ms | 0 | 3 | 0.00 | ||
| chip_sw_flash_ctrl_write_clear | 7.528m | 2.967ms | 3 | 3 | 100.00 | ||
| TOTAL | 2903 | 2948 | 98.47 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 11 | 11 | 10 | 90.91 |
| V1 | 18 | 18 | 16 | 88.89 |
| V2 | 285 | 270 | 263 | 92.28 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 91 | 22 | 19 | 20.88 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.14 | 95.59 | 94.04 | 95.50 | -- | 94.82 | 97.35 | 99.53 |
UVM_ERROR @ * us: (cip_base_vseq.sv:825) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
0.chip_csr_mem_rw_with_rand_reset.87291162751474495408191745949499112263326985736418137021101635601119666016190
Line 400, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 2642.219617 us: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2642.219617 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_csr_mem_rw_with_rand_reset.90426230400664199976978231163174052833137511538550360080178367016432357980316
Line 363, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 2266.886311 us: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2266.886311 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
0.chip_sw_rv_timer_systick_test.23537866030730341335614798600505545453886452476390004824486040553564500448148
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:5cb72982-9119-4615-9866-a4be3aa1d0e9
1.chip_sw_rv_timer_systick_test.103363340572382467839056414417844695985987520109929109925291847698437988702798
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:931c489f-d786-4741-bb1c-842a08276979
... and 1 more failures.
0.chip_sw_ast_clk_rst_inputs.112292548159591776611670012603190450109489418776609225231738281407418036349171
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
Job ID: smart:5f1e1d43-4379-406b-8d65-f92bc62ed27b
1.chip_sw_ast_clk_rst_inputs.55649492249784758298751796039196132025540918469575505170769423598664483348536
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
Job ID: smart:f49f5251-ece1-4e08-9564-aeb43799878b
... and 1 more failures.
0.chip_sw_power_virus.76761642664384512857556237066223351830116889292085697499181555540431616110433
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
Job ID: smart:e43234df-4f60-4638-a2fa-b4998ae6508f
1.chip_sw_power_virus.103497009527665015520936891493393692941696973375857869849099759084749573140382
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
Job ID: smart:ef336522-5b65-4a64-8993-f26ea7a24417
... and 1 more failures.
UVM_FATAL @ * us: (jtag_driver.sv:124) [driver] wait timeout occurred! has 3 failures:
Test chip_tap_straps_testunlock0 has 1 failures.
0.chip_tap_straps_testunlock0.102766941289195464771842994391548952801224685783880078887210358074795005096352
Line 6007, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_testunlock0/latest/run.log
UVM_FATAL @ 14046.483864 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
UVM_INFO @ 14046.483864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_tap_straps_rma has 2 failures.
1.chip_tap_straps_rma.50638819756913524500122642326764415350765693609438936196776086990566147125774
Line 5964, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_rma/latest/run.log
UVM_FATAL @ 13915.652222 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
UVM_INFO @ 13915.652222 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.chip_tap_straps_rma.94416202656641426114996535176669276849687803147328060717066882698009674763770
Line 5954, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_rma/latest/run.log
UVM_FATAL @ 11831.101458 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
UVM_INFO @ 11831.101458 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 3 failures:
0.chip_sw_rv_core_ibex_lockstep_glitch.60287869804890748078839056125165629838266400657108942759321997186448303044729
Line 785, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2973.449742 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2973.449742 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rv_core_ibex_lockstep_glitch.46663317072516949690866586382072540249458585966192600604796728976272188409001
Line 787, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2132.510816 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2132.510816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending 'initiated' has 3 failures:
0.rom_e2e_self_hash.71314202085553314578836238949182222771338964272976092079892540214313203925598
Line 1018, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log
Offending 'initiated'
UVM_ERROR @ 16082.412968 us: (hmac.sv:932) [ASSERT FAILED] ValidHashProcessAssert
UVM_INFO @ 16082.412968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_self_hash.77218370530547481110127459369957567215626587263286894910468223161385594982339
Line 1016, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log
Offending 'initiated'
UVM_ERROR @ 16182.302500 us: (hmac.sv:932) [ASSERT FAILED] ValidHashProcessAssert
UVM_INFO @ 16182.302500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
18.chip_sw_all_escalation_resets.10981850345798967418675222566537433125145659696124208540028217451544172592671
Line 792, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/18.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3256.920200 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3256.920200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
55.chip_sw_all_escalation_resets.110772205646174163129882215650832351422427466017612785127980969723813385841471
Line 807, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/55.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 2887.517120 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2887.517120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '(pend_req[h2d.a_source].pend == *)' has 2 failures:
Test rom_e2e_shutdown_output has 1 failures.
0.rom_e2e_shutdown_output.72166452051558249669069464426011786647765777135178233524244929014548906557464
Line 975, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
Offending '(pend_req[h2d.a_source].pend == 0)'
UVM_ERROR @ 15908.995860 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 15908.995860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.44205304413077298217006135372595356694075608047439747226893373216976130744748
Line 885, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
Offending '(pend_req[h2d.a_source].pend == 0)'
UVM_ERROR @ 21479.769500 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 21479.769500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
1.chip_csr_aliasing.50217254921221478855851392154466443152444161982909996552084673913371294301495
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
Job ID: smart:d5e98b7a-8ddf-4626-bfeb-c10c21f32350
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
81.chip_sw_alert_handler_lpg_sleep_mode_alerts.39207951792976183788524427188002751939516193982911034008494775221037764409945
Line 789, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 4000.936308 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
UVM_INFO @ 4000.936308 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---