| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 2 | 0 | 2 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| falling | 450599 | 1 | T80 | 2400 | T82 | 212 | T462 | 3727 | ||||
| rising | 450615 | 1 | T80 | 2399 | T82 | 212 | T462 | 3727 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 1719878 | 1 | T80 | 9463 | T82 | 797 | T462 | 14062 | ||||
| auto[1] | 611043 | 1 | T80 | 3241 | T82 | 292 | T462 | 5022 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |