Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	95.40	93.58	95.44		94.39	97.53	99.60

Total tests in report: 2906

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
38.89	38.89	45.69	45.69	44.87	44.87	24.90	24.90			58.75	58.75	58.92	58.92	0.19	0.19	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2007104480
49.96	11.08	58.49	12.81	58.15	13.28	29.88	4.98			68.75	10.00	83.04	24.13	1.47	1.28	/workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.1917637508
55.62	5.65	70.45	11.95	65.85	7.70	33.33	3.45			79.39	10.65	83.22	0.17	1.47	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.2681922485
60.01	4.39	70.45	0.00	65.85	0.00	33.33	0.00			79.39	0.00	83.22	0.00	27.81	26.34	/workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1595094398
64.16	4.15	75.37	4.93	69.41	3.56	36.85	3.52			79.55	0.16	83.22	0.00	40.57	12.76	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.2306621980
67.65	3.49	81.43	6.06	73.80	4.39	40.77	3.92			81.57	2.02	87.76	4.55	40.57	0.00	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3844502388
70.42	2.77	82.61	1.17	74.09	0.29	55.10	14.33			81.75	0.18	87.94	0.17	41.05	0.48	/workspace/coverage/default/2.chip_jtag_csr_rw.2869301943
72.51	2.09	82.61	0.00	74.09	0.00	55.10	0.00			81.75	0.00	87.94	0.00	53.59	12.54	/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2021990840
74.58	2.07	82.62	0.01	74.10	0.01	67.25	12.16			81.76	0.01	88.11	0.17	53.65	0.06	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.602473409
76.49	1.91	82.62	0.00	74.10	0.00	67.25	0.00			81.76	0.00	88.11	0.00	65.10	11.46	/workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2479011415
78.02	1.53	84.40	1.78	77.70	3.60	67.62	0.36			85.19	3.43	88.11	0.00	65.10	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2122425833
79.55	1.53	84.48	0.09	77.71	0.01	76.30	8.68			85.20	0.01	88.46	0.35	65.12	0.01	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2645198370
80.90	1.36	84.48	0.00	77.96	0.25	76.30	0.00			85.27	0.06	88.46	0.00	72.94	7.83	/workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.114902319
82.14	1.24	85.34	0.86	78.40	0.44	78.01	1.71			85.68	0.41	92.48	4.02	72.94	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3937544800
83.18	1.03	87.18	1.84	80.26	1.86	78.31	0.30			87.89	2.22	92.48	0.00	72.94	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.4289367131
84.12	0.94	88.29	1.11	81.13	0.87	79.22	0.91			89.00	1.10	94.06	1.57	72.99	0.05	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3894358600
84.98	0.87	88.29	0.00	81.97	0.84	79.22	0.00			89.17	0.17	94.06	0.00	77.18	4.19	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.2167033336
85.81	0.83	88.29	0.00	81.97	0.00	79.22	0.00			89.17	0.00	94.06	0.00	82.14	4.96	/workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.2722141633
86.62	0.81	88.29	0.00	81.97	0.00	79.22	0.00			89.17	0.00	94.06	0.00	87.02	4.88	/workspace/coverage/cover_reg_top/44.xbar_access_same_device.1382138433
87.31	0.69	89.03	0.74	83.54	1.56	79.25	0.02			89.91	0.75	95.10	1.05	87.02	0.00	/workspace/coverage/cover_reg_top/12.chip_csr_rw.818034017
87.96	0.65	89.03	0.00	83.54	0.00	83.14	3.89			89.91	0.00	95.10	0.00	87.02	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2557293886
88.59	0.64	90.10	1.07	84.10	0.56	84.60	1.46			90.47	0.55	95.28	0.17	87.02	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2898387420
89.19	0.60	90.10	0.00	84.13	0.03	84.60	0.00			90.47	0.00	95.28	0.00	90.59	3.57	/workspace/coverage/cover_reg_top/79.xbar_stress_all.2023818333
89.74	0.55	91.09	0.98	85.13	1.01	85.01	0.40			91.38	0.91	95.28	0.00	90.59	0.00	/workspace/coverage/default/1.chip_sw_gpio.120963694
90.20	0.46	91.96	0.87	85.81	0.68	85.39	0.38			92.18	0.80	95.28	0.00	90.59	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.3930278968
90.64	0.44	91.97	0.01	88.02	2.21	85.39	0.00			92.18	0.00	95.28	0.00	90.99	0.40	/workspace/coverage/cover_reg_top/20.chip_tl_errors.3297654216
91.04	0.40	92.01	0.05	88.08	0.06	86.70	1.31			92.18	0.00	95.28	0.00	91.96	0.98	/workspace/coverage/default/0.chip_sw_alert_test.1700921444
91.40	0.36	92.74	0.73	88.14	0.06	87.26	0.57			92.18	0.00	95.28	0.00	92.79	0.82	/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.1112491280
91.71	0.31	92.85	0.11	88.22	0.08	88.70	1.44			92.25	0.07	95.28	0.00	92.97	0.19	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.403330741
92.01	0.30	92.85	0.00	88.42	0.20	88.70	0.00			92.26	0.01	95.28	0.00	94.57	1.60	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.2260432346
92.26	0.24	92.85	0.00	88.42	0.00	88.70	0.00			92.26	0.00	95.28	0.00	96.02	1.45	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.905181774
92.47	0.22	92.94	0.09	88.59	0.17	88.97	0.27			92.32	0.06	95.98	0.70	96.02	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.925505070
92.68	0.21	92.94	0.00	88.59	0.00	90.23	1.26			92.32	0.00	95.98	0.00	96.02	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1752419132
92.88	0.20	92.94	0.00	88.59	0.00	90.23	0.00			92.32	0.00	95.98	0.00	97.23	1.21	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3356268348
93.07	0.18	92.94	0.00	88.59	0.00	90.97	0.75			92.32	0.00	95.98	0.00	97.58	0.35	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.2896607256
93.23	0.17	93.11	0.17	88.76	0.17	91.48	0.50			92.49	0.17	95.98	0.00	97.58	0.00	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.469225839
93.39	0.16	93.13	0.02	89.18	0.42	91.51	0.03			92.97	0.47	95.98	0.00	97.58	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2064462447
93.54	0.15	93.32	0.19	89.30	0.13	91.61	0.10			93.10	0.13	96.33	0.35	97.58	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.303953538
93.69	0.15	93.52	0.21	89.62	0.32	91.96	0.35			93.10	0.00	96.33	0.00	97.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3452711369
93.81	0.12	93.52	0.00	90.34	0.72	91.96	0.00			93.10	0.00	96.33	0.00	97.58	0.00	/workspace/coverage/cover_reg_top/23.chip_tl_errors.2271282561
93.91	0.11	93.52	0.00	90.46	0.11	91.96	0.00			93.10	0.00	96.33	0.00	98.12	0.54	/workspace/coverage/cover_reg_top/77.xbar_stress_all.1068391333
94.02	0.11	93.54	0.01	90.54	0.08	92.30	0.34			93.12	0.02	96.50	0.17	98.13	0.01	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2308720702
94.13	0.11	93.69	0.15	90.67	0.13	92.52	0.21			93.27	0.15	96.50	0.00	98.13	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.959029847
94.23	0.10	93.69	0.01	90.95	0.28	92.52	0.01			93.59	0.32	96.50	0.00	98.13	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2886709183
94.32	0.09	93.72	0.02	90.96	0.01	93.02	0.50			93.59	0.00	96.50	0.00	98.13	0.00	/workspace/coverage/default/91.chip_sw_all_escalation_resets.4047344308
94.41	0.09	93.89	0.18	91.02	0.06	93.03	0.01			93.66	0.06	96.68	0.17	98.17	0.04	/workspace/coverage/default/2.chip_sw_all_escalation_resets.3631455784
94.48	0.07	94.02	0.13	91.15	0.13	93.06	0.03			93.78	0.12	96.68	0.00	98.17	0.00	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3508397536
94.54	0.07	94.09	0.07	91.29	0.14	93.17	0.11			93.84	0.06	96.68	0.00	98.18	0.01	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3076954084
94.61	0.06	94.09	0.00	91.29	0.00	93.55	0.38			93.84	0.00	96.68	0.00	98.19	0.01	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.696233832
94.67	0.06	94.09	0.00	91.47	0.18	93.55	0.00			93.86	0.02	96.68	0.00	98.36	0.16	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3113268697
94.72	0.05	94.09	0.00	91.47	0.00	93.87	0.33			93.86	0.00	96.68	0.00	98.36	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2076027210
94.77	0.04	94.09	0.00	91.47	0.00	94.14	0.27			93.86	0.00	96.68	0.00	98.36	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.4290155576
94.81	0.04	94.12	0.03	91.49	0.02	94.14	0.01			93.88	0.02	96.85	0.17	98.37	0.01	/workspace/coverage/default/7.chip_sw_all_escalation_resets.3882778555
94.85	0.04	94.12	0.00	91.74	0.25	94.14	0.00			93.88	0.00	96.85	0.00	98.38	0.01	/workspace/coverage/cover_reg_top/1.chip_tl_errors.2232874878
94.90	0.04	94.12	0.00	91.74	0.00	94.40	0.26			93.88	0.00	96.85	0.00	98.38	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2134685554
94.94	0.04	94.18	0.07	91.87	0.12	94.40	0.00			93.95	0.06	96.85	0.00	98.38	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.426181345
94.98	0.04	94.19	0.01	91.88	0.01	94.41	0.01			93.96	0.01	97.03	0.17	98.39	0.01	/workspace/coverage/default/44.chip_sw_all_escalation_resets.4107508851
95.01	0.04	94.19	0.01	91.89	0.01	94.42	0.01			93.96	0.01	97.20	0.17	98.40	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.1598383670
95.05	0.04	94.20	0.01	91.91	0.01	94.42	0.00			93.97	0.01	97.38	0.17	98.41	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.174139
95.08	0.04	94.20	0.00	91.98	0.07	94.42	0.00			93.97	0.00	97.38	0.00	98.55	0.14	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.2614586183
95.12	0.03	94.23	0.03	92.03	0.06	94.51	0.10			94.00	0.02	97.38	0.00	98.55	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3103063523
95.15	0.03	94.23	0.00	92.03	0.00	94.55	0.03			94.00	0.00	97.55	0.17	98.55	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.4080008555
95.18	0.03	94.28	0.05	92.11	0.08	94.55	0.01			94.04	0.05	97.55	0.00	98.55	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2270960614
95.21	0.03	94.35	0.07	92.18	0.07	94.55	0.00			94.09	0.05	97.55	0.00	98.55	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3364934772
95.24	0.03	94.42	0.07	92.18	0.00	94.64	0.09			94.10	0.01	97.55	0.00	98.55	0.00	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2927463309
95.27	0.03	94.42	0.00	92.29	0.11	94.64	0.00			94.15	0.05	97.55	0.00	98.55	0.00	/workspace/coverage/cover_reg_top/6.xbar_stress_all.4292876405
95.29	0.03	94.49	0.07	92.32	0.03	94.65	0.01			94.20	0.05	97.55	0.00	98.55	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2885870246
95.32	0.02	94.56	0.07	92.36	0.05	94.65	0.00			94.23	0.03	97.55	0.00	98.55	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2133613963
95.34	0.02	94.56	0.00	92.50	0.13	94.65	0.00			94.23	0.00	97.55	0.00	98.55	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2270320545
95.36	0.02	94.57	0.01	92.61	0.11	94.65	0.01			94.23	0.00	97.55	0.00	98.55	0.00	/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.2977907935
95.38	0.02	94.58	0.01	92.64	0.03	94.74	0.08			94.24	0.01	97.55	0.00	98.55	0.00	/workspace/coverage/default/0.chip_sw_usbdev_config_host.199095726
95.40	0.02	94.62	0.04	92.67	0.03	94.75	0.01			94.26	0.02	97.55	0.00	98.57	0.01	/workspace/coverage/default/86.chip_sw_all_escalation_resets.3439008379
95.42	0.02	94.62	0.00	92.77	0.10	94.75	0.00			94.26	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.427557838
95.43	0.01	94.62	0.00	92.81	0.04	94.75	0.00			94.26	0.00	97.55	0.00	98.61	0.05	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.1182763354
95.45	0.01	94.62	0.00	92.81	0.00	94.83	0.08			94.26	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2491938819
95.46	0.01	94.62	0.00	92.81	0.01	94.91	0.07			94.26	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3141871
95.47	0.01	94.62	0.00	92.81	0.00	94.98	0.08			94.26	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3895405475
95.48	0.01	94.62	0.00	92.87	0.05	94.98	0.00			94.27	0.02	97.55	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/7.xbar_stress_all.3179412004
95.50	0.01	94.62	0.00	92.93	0.07	94.98	0.00			94.27	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.3528782370
95.51	0.01	94.62	0.00	93.00	0.06	94.98	0.00			94.27	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/28.chip_tl_errors.3578411200
95.52	0.01	94.62	0.01	93.02	0.02	94.99	0.01			94.30	0.02	97.55	0.00	98.61	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1698607715
95.53	0.01	94.64	0.02	93.02	0.00	95.03	0.04			94.30	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.32611589
95.54	0.01	94.64	0.00	93.08	0.06	95.03	0.00			94.30	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.275293191
95.54	0.01	94.64	0.00	93.11	0.03	95.03	0.00			94.30	0.00	97.55	0.00	98.64	0.02	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2983282500
95.55	0.01	94.66	0.02	93.12	0.01	95.04	0.01			94.31	0.02	97.55	0.00	98.64	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2487417349
95.56	0.01	94.69	0.02	93.12	0.01	95.04	0.01			94.33	0.02	97.55	0.00	98.64	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1495596405
95.57	0.01	94.71	0.02	93.13	0.01	95.04	0.01			94.34	0.02	97.55	0.00	98.64	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.164780932
95.58	0.01	94.73	0.02	93.14	0.01	95.04	0.01			94.36	0.02	97.55	0.00	98.64	0.00	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.108335733
95.59	0.01	94.73	0.00	93.14	0.00	95.09	0.05			94.36	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2186400646
95.59	0.01	94.74	0.01	93.16	0.02	95.10	0.01			94.37	0.01	97.55	0.00	98.64	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3831485788
95.60	0.01	94.76	0.02	93.16	0.00	95.11	0.01			94.37	0.00	97.55	0.00	98.66	0.02	/workspace/coverage/default/82.chip_sw_all_escalation_resets.3193195441
95.61	0.01	94.76	0.00	93.20	0.04	95.11	0.00			94.37	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_gpio.1292076621
95.61	0.01	94.76	0.00	93.20	0.00	95.15	0.04			94.37	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1525508200
95.62	0.01	94.78	0.02	93.21	0.01	95.16	0.01			94.37	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.751672754
95.63	0.01	94.78	0.00	93.23	0.02	95.16	0.00			94.37	0.00	97.55	0.00	98.67	0.01	/workspace/coverage/cover_reg_top/13.chip_tl_errors.1505742665
95.63	0.01	94.78	0.00	93.27	0.04	95.16	0.00			94.37	0.00	97.55	0.00	98.67	0.00	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.3300011469
95.64	0.01	94.78	0.00	93.27	0.00	95.16	0.00			94.37	0.00	97.55	0.00	98.71	0.04	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.4123441048
95.64	0.01	94.78	0.00	93.27	0.01	95.18	0.03			94.37	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3815525416
95.65	0.01	94.78	0.00	93.27	0.00	95.22	0.03			94.37	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2113477700
95.65	0.01	94.78	0.00	93.30	0.03	95.22	0.00			94.37	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/cover_reg_top/67.xbar_stress_all.1462007442
95.66	0.01	94.78	0.00	93.34	0.03	95.22	0.00			94.37	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2486381473
95.67	0.01	94.78	0.00	93.34	0.00	95.25	0.03			94.37	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.3884376124
95.67	0.01	94.78	0.00	93.34	0.01	95.25	0.00			94.37	0.00	97.55	0.00	98.73	0.02	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.245633793
95.67	0.01	94.78	0.00	93.34	0.00	95.25	0.00			94.37	0.00	97.55	0.00	98.75	0.02	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.860612222
95.68	0.01	94.78	0.00	93.34	0.00	95.25	0.00			94.37	0.00	97.55	0.00	98.78	0.02	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.2161473071
95.68	0.01	94.78	0.00	93.34	0.00	95.27	0.02			94.37	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.396215928
95.69	0.01	94.78	0.00	93.36	0.02	95.27	0.00			94.37	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.4027882576
95.69	0.01	94.78	0.00	93.38	0.02	95.27	0.00			94.37	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/65.xbar_stress_all.3835352279
95.69	0.01	94.78	0.00	93.38	0.00	95.29	0.02			94.37	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1294636921
95.69	0.01	94.78	0.00	93.38	0.00	95.31	0.02			94.37	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3891900122
95.70	0.01	94.78	0.01	93.40	0.01	95.31	0.00			94.37	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2297435148
95.70	0.01	94.79	0.01	93.40	0.00	95.32	0.01			94.37	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.385772406
95.70	0.01	94.79	0.00	93.40	0.00	95.32	0.01			94.37	0.00	97.55	0.00	98.79	0.01	/workspace/coverage/default/30.chip_sw_all_escalation_resets.2586241685
95.71	0.01	94.79	0.00	93.40	0.00	95.34	0.02			94.37	0.00	97.55	0.00	98.79	0.00	/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.2005465097
95.71	0.01	94.81	0.01	93.40	0.00	95.34	0.01			94.37	0.00	97.55	0.00	98.79	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.654322036
95.71	0.01	94.81	0.00	93.40	0.01	95.34	0.00			94.37	0.00	97.55	0.00	98.80	0.01	/workspace/coverage/cover_reg_top/18.chip_tl_errors.1744117346
95.71	0.01	94.81	0.00	93.40	0.01	95.34	0.00			94.37	0.00	97.55	0.00	98.81	0.01	/workspace/coverage/default/31.chip_sw_all_escalation_resets.651442210
95.72	0.01	94.81	0.00	93.42	0.01	95.34	0.00			94.37	0.00	97.55	0.00	98.81	0.00	/workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.2529262110
95.72	0.01	94.81	0.00	93.43	0.01	95.34	0.00			94.37	0.00	97.55	0.00	98.81	0.00	/workspace/coverage/cover_reg_top/6.chip_tl_errors.1850728627
95.72	0.01	94.81	0.00	93.45	0.01	95.34	0.00			94.37	0.00	97.55	0.00	98.81	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.649823010
95.72	0.01	94.81	0.00	93.46	0.01	95.34	0.00			94.37	0.00	97.55	0.00	98.81	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3861046215
95.73	0.01	94.81	0.00	93.47	0.01	95.34	0.00			94.37	0.00	97.55	0.00	98.81	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.2716469646
95.73	0.01	94.81	0.00	93.47	0.00	95.34	0.01			94.37	0.00	97.55	0.00	98.83	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1263550280
95.73	0.01	94.81	0.00	93.47	0.00	95.34	0.01			94.37	0.00	97.55	0.00	98.84	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.2694736195
95.73	0.01	94.82	0.01	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	98.84	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.3122495713
95.73	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	98.85	0.01	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.4254848218
95.74	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	98.86	0.01	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.699508500
95.74	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	98.87	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.850374265
95.74	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	98.88	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.360492973
95.74	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	98.90	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3001791572
95.74	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	98.91	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.173847110
95.75	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	98.92	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.1477753126
95.75	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	98.93	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.3767221976
95.75	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	98.94	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.974729167
95.75	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	98.95	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.1187334605
95.75	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	98.97	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3897648210
95.76	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	98.98	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.530488726
95.76	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	98.99	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.972668493
95.76	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.00	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.2192606140
95.76	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.01	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1698544431
95.76	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.02	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3672999090
95.77	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.04	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.3050129227
95.77	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.05	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2290591084
95.77	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.06	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.338156439
95.77	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.07	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3632811155
95.77	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.08	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.381828058
95.78	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.10	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1339849047
95.78	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.11	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3549575029
95.78	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.12	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.1598773339
95.78	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.13	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3444720181
95.78	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.14	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.2550312386
95.79	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.15	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.609872559
95.79	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.17	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.3406951925
95.79	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.18	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.4063592151
95.79	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.19	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.845117005
95.79	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.20	0.01	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1994395451
95.80	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.21	0.01	/workspace/coverage/default/3.chip_sw_all_escalation_resets.2596242071
95.80	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.22	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1687170834
95.80	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.24	0.01	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.948195612
95.80	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.25	0.01	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2231510839
95.80	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.26	0.01	/workspace/coverage/default/34.chip_sw_all_escalation_resets.3386451568
95.81	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.27	0.01	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1751126921
95.81	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.28	0.01	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.513763918
95.81	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.30	0.01	/workspace/coverage/default/36.chip_sw_all_escalation_resets.2696954781
95.81	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.31	0.01	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.629788057
95.81	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.32	0.01	/workspace/coverage/default/39.chip_sw_all_escalation_resets.3318420898
95.81	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.33	0.01	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2562017820
95.82	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.34	0.01	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1011592730
95.82	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.35	0.01	/workspace/coverage/default/41.chip_sw_all_escalation_resets.2848634011
95.82	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.37	0.01	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2314388348
95.82	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.38	0.01	/workspace/coverage/default/42.chip_sw_all_escalation_resets.2202711972
95.82	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.39	0.01	/workspace/coverage/default/46.chip_sw_all_escalation_resets.4285695400
95.83	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.40	0.01	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.263686383
95.83	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.41	0.01	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.4077516145
95.83	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.42	0.01	/workspace/coverage/default/50.chip_sw_all_escalation_resets.3262326181
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95.83	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.45	0.01	/workspace/coverage/default/57.chip_sw_all_escalation_resets.2198222699
95.84	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.46	0.01	/workspace/coverage/default/58.chip_sw_all_escalation_resets.315910980
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95.84	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.48	0.01	/workspace/coverage/default/64.chip_sw_all_escalation_resets.3180566747
95.84	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.49	0.01	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.4105706901
95.84	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.51	0.01	/workspace/coverage/default/66.chip_sw_all_escalation_resets.539829002
95.85	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3021272341
95.85	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2935698050
95.85	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.4054751171
95.85	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1363400613
95.85	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.57	0.01	/workspace/coverage/default/77.chip_sw_all_escalation_resets.1798124784
95.86	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.58	0.01	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3197791286
95.86	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.59	0.01	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.240076264
95.86	0.01	94.82	0.00	93.47	0.00	95.34	0.00			94.37	0.00	97.55	0.00	99.60	0.01	/workspace/coverage/default/98.chip_sw_all_escalation_resets.4010239920
95.86	0.01	94.82	0.00	93.48	0.01	95.35	0.01			94.37	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1310366497
95.86	0.01	94.82	0.00	93.48	0.00	95.36	0.01			94.37	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3386050549
95.87	0.01	94.82	0.00	93.49	0.01	95.36	0.00			94.37	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.134585296
95.87	0.01	94.82	0.00	93.50	0.01	95.36	0.00			94.37	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.4240965465
95.87	0.01	94.82	0.01	93.51	0.01	95.36	0.00			94.37	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1287446617
95.87	0.01	94.82	0.00	93.51	0.00	95.37	0.01			94.37	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.2966303096
95.87	0.01	94.82	0.00	93.51	0.00	95.38	0.01			94.37	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.659524117
95.87	0.01	94.82	0.00	93.51	0.00	95.39	0.01			94.37	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1251139412
95.88	0.01	94.82	0.00	93.51	0.00	95.40	0.01			94.37	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.618419615
95.88	0.01	94.82	0.00	93.51	0.00	95.40	0.00			94.38	0.01	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2148833316
95.88	0.01	94.82	0.00	93.51	0.00	95.40	0.00			94.39	0.01	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.428940416
95.88	0.01	94.82	0.00	93.52	0.01	95.40	0.00			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.3396107239
95.88	0.01	94.82	0.00	93.52	0.01	95.40	0.00			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2734485819
95.88	0.01	94.82	0.00	93.53	0.01	95.40	0.00			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1274150848
95.88	0.01	94.82	0.00	93.54	0.01	95.40	0.00			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.620462665
95.88	0.01	94.82	0.00	93.54	0.01	95.40	0.00			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/2.chip_sw_gpio.3216870008
95.88	0.01	94.82	0.00	93.54	0.00	95.40	0.01			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2679562224
95.89	0.01	94.82	0.00	93.54	0.00	95.41	0.01			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2895921794
95.89	0.01	94.82	0.00	93.54	0.00	95.41	0.01			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_flash_init.1372924984
95.89	0.01	94.82	0.00	93.54	0.00	95.42	0.01			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1285436072
95.89	0.01	94.82	0.00	93.54	0.00	95.42	0.01			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2070056941
95.89	0.01	94.82	0.00	93.54	0.00	95.43	0.01			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2199238839
95.89	0.01	94.82	0.00	93.54	0.00	95.43	0.01			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3670491314
95.89	0.01	94.82	0.00	93.55	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1486558218
95.89	0.01	94.82	0.00	93.55	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.1554536337
95.89	0.01	94.82	0.00	93.55	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.1307865792
95.89	0.01	94.82	0.00	93.56	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.1512533858
95.89	0.01	94.82	0.00	93.56	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/18.xbar_error_random.3352623226
95.89	0.01	94.82	0.00	93.57	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/2.chip_tl_errors.2966580206
95.89	0.01	94.82	0.00	93.57	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.2912923407
95.89	0.01	94.82	0.00	93.57	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/52.xbar_error_random.4210045157
95.89	0.01	94.82	0.00	93.58	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2340463438
95.90	0.01	94.82	0.00	93.58	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.964129529
95.90	0.01	94.82	0.00	93.58	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1599855774
95.90	0.01	94.82	0.00	93.58	0.00	95.43	0.01			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/1.chip_tap_straps_testunlock0.3404757694
95.90	0.01	94.83	0.01	93.58	0.00	95.43	0.00			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3194405932
95.90	0.01	94.83	0.00	93.58	0.00	95.44	0.01			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.459286476
95.90	0.01	94.83	0.00	93.58	0.00	95.44	0.01			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.497158332
95.90	0.01	94.83	0.00	93.58	0.00	95.44	0.01			94.39	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.620116087

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1252170426
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2119367176
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3280541770
/workspace/coverage/cover_reg_top/0.chip_csr_rw.651155167
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.76316820
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2091527696
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.197023170
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3188760666
/workspace/coverage/cover_reg_top/0.xbar_error_random.4157418721
/workspace/coverage/cover_reg_top/0.xbar_random.1800519321
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1680718932
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1674101148
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3052778878
/workspace/coverage/cover_reg_top/0.xbar_same_source.2019407235
/workspace/coverage/cover_reg_top/0.xbar_smoke.2799677094
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.75365499
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2885659714
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3014063951
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3272833850
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2919350310
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.83251783
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1708111878
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.440046488
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1868580068
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3744518974
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.3366920998
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.164330211
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1024396251
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2630876639
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.476803671
/workspace/coverage/cover_reg_top/1.xbar_error_random.3446653780
/workspace/coverage/cover_reg_top/1.xbar_random.1765376984
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3261033535
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.347806726
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.160172509
/workspace/coverage/cover_reg_top/1.xbar_same_source.40559989
/workspace/coverage/cover_reg_top/1.xbar_smoke.3680205943
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1066669245
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3762296979
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.832935678
/workspace/coverage/cover_reg_top/1.xbar_stress_all.145820868
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2707109678
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.4078558969
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1542321046
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1147240808
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2548594564
/workspace/coverage/cover_reg_top/10.chip_tl_errors.2633754736
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.3488092454
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.29727201
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2048912402
/workspace/coverage/cover_reg_top/10.xbar_error_random.1148385662
/workspace/coverage/cover_reg_top/10.xbar_random.326667830
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2206423651
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2949704496
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.4068610393
/workspace/coverage/cover_reg_top/10.xbar_same_source.792290925
/workspace/coverage/cover_reg_top/10.xbar_smoke.468555037
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2269304290
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2254413115
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3273638243
/workspace/coverage/cover_reg_top/10.xbar_stress_all.3049725512
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.933910690
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.4290180240
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1689525675
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.55484326
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3375948513
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.499186373
/workspace/coverage/cover_reg_top/11.chip_tl_errors.2855988401
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.1725273778
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2700059315
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2394451768
/workspace/coverage/cover_reg_top/11.xbar_error_random.1438745984
/workspace/coverage/cover_reg_top/11.xbar_random.3122740309
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.476988548
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2156743909
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1360830746
/workspace/coverage/cover_reg_top/11.xbar_same_source.2686710133
/workspace/coverage/cover_reg_top/11.xbar_smoke.2475115377
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2907240133
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2778919126
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.4136089332
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3513943996
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.4112804293
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.973173839
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.313783719
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1945408773
/workspace/coverage/cover_reg_top/12.chip_tl_errors.961190238
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3701893523
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.160992716
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3143571548
/workspace/coverage/cover_reg_top/12.xbar_error_random.400123925
/workspace/coverage/cover_reg_top/12.xbar_random.721618397
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1451893588
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.892196399
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1765067109
/workspace/coverage/cover_reg_top/12.xbar_same_source.2071659821
/workspace/coverage/cover_reg_top/12.xbar_smoke.3539549189
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1659365994
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3318309347
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3484230095
/workspace/coverage/cover_reg_top/12.xbar_stress_all.148902630
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2649659653
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.503882072
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1461731558
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.4119558331
/workspace/coverage/cover_reg_top/13.chip_csr_rw.1205326308
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.557891979
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2710573699
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1540766834
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1232101699
/workspace/coverage/cover_reg_top/13.xbar_error_random.2209648083
/workspace/coverage/cover_reg_top/13.xbar_random.2447941407
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.922371140
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2593194440
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.4092887486
/workspace/coverage/cover_reg_top/13.xbar_same_source.683885578
/workspace/coverage/cover_reg_top/13.xbar_smoke.49877243
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2713765228
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3105627507
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/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.303548958
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.727727026
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/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1607930401
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.4274523891
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.273545342
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1081317644
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.573065119
/workspace/coverage/default/2.chip_sw_spi_device_tpm.2020506939
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/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3941606202
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/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2345841553
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/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2847417110
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/workspace/coverage/default/33.chip_sw_all_escalation_resets.3070546268
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3651512966
/workspace/coverage/default/35.chip_sw_all_escalation_resets.732109315
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.4278274098
/workspace/coverage/default/37.chip_sw_all_escalation_resets.3836827925
/workspace/coverage/default/38.chip_sw_all_escalation_resets.2472750824
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.832475343
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2520642561
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2820700431
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.335322190
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/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1410916157
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1070993982
/workspace/coverage/default/4.chip_sw_uart_tx_rx.518782728
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/workspace/coverage/default/4.chip_tap_straps_dev.3564823028
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/workspace/coverage/default/4.chip_tap_straps_testunlock0.477822360
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.4181960765
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/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3648193317
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/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3603407114
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/workspace/coverage/default/49.chip_sw_all_escalation_resets.657334070
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4007985124
/workspace/coverage/default/5.chip_sw_all_escalation_resets.1623366170
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.172729861
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2817258184
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1256055606
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3940170220
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/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1912091689
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/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.726531967
/workspace/coverage/default/53.chip_sw_all_escalation_resets.3562705442
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.757908807
/workspace/coverage/default/54.chip_sw_all_escalation_resets.3797084430
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2594962287
/workspace/coverage/default/55.chip_sw_all_escalation_resets.2372992371
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.4035691484
/workspace/coverage/default/56.chip_sw_all_escalation_resets.796019630
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1194278982
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1026342469
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.929585321
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1205618952
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3818608389
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3685647868
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1664112783
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1415198514
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1947980883
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2614238489
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3953450112
/workspace/coverage/default/61.chip_sw_all_escalation_resets.4183902367
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3508703111
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3330929817
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1836600895
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1131183071
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3893509581
/workspace/coverage/default/65.chip_sw_all_escalation_resets.107167681
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2786336231
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.35290127
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3676831934
/workspace/coverage/default/68.chip_sw_all_escalation_resets.4246883651
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1320135828
/workspace/coverage/default/69.chip_sw_all_escalation_resets.883025440
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1677917690
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.272208866
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2812450476
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2089181284
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2679290288
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2692053917
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1505713632
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3092345024
/workspace/coverage/default/73.chip_sw_all_escalation_resets.3671849231
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1890847605
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1856233754
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.148916972
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3487233111
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1464708496
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2893256998
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2372393774
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.122122291
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2724854322
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3447112246
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1146388480
/workspace/coverage/default/8.chip_sw_all_escalation_resets.1883846780
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2692104748
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1032001920
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1622741277
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1014632366
/workspace/coverage/default/80.chip_sw_all_escalation_resets.4263771814
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1414658645
/workspace/coverage/default/81.chip_sw_all_escalation_resets.853920215
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3397624345
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2979526091
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1244862522
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4107910173
/workspace/coverage/default/84.chip_sw_all_escalation_resets.1426056299
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3728244988
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1751448369
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2239768645
/workspace/coverage/default/87.chip_sw_all_escalation_resets.842925295
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3548498806
/workspace/coverage/default/88.chip_sw_all_escalation_resets.2161854674
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2621714438
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2998774135
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1743767517
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3055016437
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1824435345
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.638769552
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3089567065
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3011479990
/workspace/coverage/default/92.chip_sw_all_escalation_resets.603336512
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1198416649
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1151907004
/workspace/coverage/default/96.chip_sw_all_escalation_resets.3738594694
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3143337532
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2494111333
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1910211097
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.309569186
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3207194199
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2737477001
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2446905689
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3984836458
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2407321260
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.4076318786

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Total test records in report: 2906

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2898387420			Jul 11 08:12:25 PM PDT 24	Jul 11 09:53:02 PM PDT 24	23695400992 ps
T5	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1752419132			Jul 11 07:59:37 PM PDT 24	Jul 11 09:18:14 PM PDT 24	45224530548 ps
T6	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.4215092417			Jul 11 08:36:03 PM PDT 24	Jul 11 09:33:29 PM PDT 24	15355115656 ps
T43	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.602473409			Jul 11 08:31:30 PM PDT 24	Jul 11 08:46:22 PM PDT 24	6558606321 ps
T44	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2113477700			Jul 11 08:28:30 PM PDT 24	Jul 11 08:41:20 PM PDT 24	4614757300 ps
T16	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3089567065			Jul 11 08:28:59 PM PDT 24	Jul 11 08:38:39 PM PDT 24	4061088670 ps
T17	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2956036921			Jul 11 08:21:58 PM PDT 24	Jul 11 08:26:31 PM PDT 24	3211368247 ps
T88	/workspace/coverage/default/0.chip_sw_kmac_smoketest.3451898550			Jul 11 08:04:20 PM PDT 24	Jul 11 08:09:07 PM PDT 24	2787241908 ps
T18	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2007104480			Jul 11 08:35:56 PM PDT 24	Jul 11 08:42:42 PM PDT 24	3933942784 ps
T89	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3937544800			Jul 11 08:21:07 PM PDT 24	Jul 11 08:26:25 PM PDT 24	2967364940 ps
T196	/workspace/coverage/default/0.chip_sw_aes_idle.843447590			Jul 11 08:03:58 PM PDT 24	Jul 11 08:08:59 PM PDT 24	3508575864 ps
T19	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2182450586			Jul 11 08:30:14 PM PDT 24	Jul 11 08:57:11 PM PDT 24	19982505539 ps
T185	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.202624436			Jul 11 08:04:22 PM PDT 24	Jul 11 08:09:16 PM PDT 24	3009491504 ps
T253	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3444720181			Jul 11 08:32:49 PM PDT 24	Jul 11 08:39:46 PM PDT 24	3433533156 ps
T57	/workspace/coverage/default/2.rom_e2e_asm_init_prod.2198062589			Jul 11 08:28:35 PM PDT 24	Jul 11 09:25:29 PM PDT 24	15182590650 ps
T299	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.412553397			Jul 11 08:09:56 PM PDT 24	Jul 11 08:13:05 PM PDT 24	2794474124 ps
T121	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3631331699			Jul 11 08:21:45 PM PDT 24	Jul 11 08:25:53 PM PDT 24	2573245126 ps
T20	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2134685554			Jul 11 08:04:02 PM PDT 24	Jul 11 08:06:39 PM PDT 24	3078901589 ps
T62	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2616345057			Jul 11 08:25:37 PM PDT 24	Jul 11 08:33:45 PM PDT 24	4645481144 ps
T64	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.403330741			Jul 11 08:04:00 PM PDT 24	Jul 11 08:29:42 PM PDT 24	16834879734 ps
T27	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.469225839			Jul 11 08:25:20 PM PDT 24	Jul 11 09:07:56 PM PDT 24	12826990300 ps
T54	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3141871			Jul 11 08:08:24 PM PDT 24	Jul 11 09:08:53 PM PDT 24	14498099786 ps
T65	/workspace/coverage/default/51.chip_sw_all_escalation_resets.779030664			Jul 11 08:38:34 PM PDT 24	Jul 11 08:46:34 PM PDT 24	5451016900 ps
T922	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3799943493			Jul 11 08:05:41 PM PDT 24	Jul 11 08:13:18 PM PDT 24	4404413944 ps
T126	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1156435986			Jul 11 08:01:09 PM PDT 24	Jul 11 08:07:44 PM PDT 24	6721919416 ps
T159	/workspace/coverage/default/0.chip_plic_all_irqs_10.2681922485			Jul 11 08:03:52 PM PDT 24	Jul 11 08:11:37 PM PDT 24	3903235400 ps
T127	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3324707222			Jul 11 08:20:13 PM PDT 24	Jul 11 09:06:49 PM PDT 24	26452416136 ps
T923	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1629582427			Jul 11 08:04:49 PM PDT 24	Jul 11 08:08:17 PM PDT 24	3024089415 ps
T924	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.1785719801			Jul 11 08:03:32 PM PDT 24	Jul 11 08:07:12 PM PDT 24	2447665162 ps
T66	/workspace/coverage/default/68.chip_sw_all_escalation_resets.4246883651			Jul 11 08:37:28 PM PDT 24	Jul 11 08:44:39 PM PDT 24	4314271480 ps
T369	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1263550280			Jul 11 08:33:38 PM PDT 24	Jul 11 08:41:32 PM PDT 24	3389131656 ps
T752	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3445473521			Jul 11 08:36:43 PM PDT 24	Jul 11 08:42:23 PM PDT 24	3857968424 ps
T694	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1011592730			Jul 11 08:35:28 PM PDT 24	Jul 11 08:41:56 PM PDT 24	4332017240 ps
T925	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2306959454			Jul 11 08:32:57 PM PDT 24	Jul 11 08:39:47 PM PDT 24	5929546408 ps
T58	/workspace/coverage/default/0.chip_jtag_csr_rw.385772406			Jul 11 07:55:00 PM PDT 24	Jul 11 08:32:17 PM PDT 24	18284414216 ps
T151	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1924247198			Jul 11 08:23:48 PM PDT 24	Jul 11 08:35:22 PM PDT 24	4370385030 ps
T926	/workspace/coverage/default/0.chip_sw_example_flash.1513323334			Jul 11 08:04:54 PM PDT 24	Jul 11 08:08:56 PM PDT 24	2599686408 ps
T715	/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2202588827			Jul 11 08:10:32 PM PDT 24	Jul 11 08:37:27 PM PDT 24	7694452550 ps
T176	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3393115095			Jul 11 08:09:09 PM PDT 24	Jul 11 09:02:12 PM PDT 24	12034139805 ps
T322	/workspace/coverage/default/0.chip_sw_hmac_enc.4220839120			Jul 11 08:02:32 PM PDT 24	Jul 11 08:07:39 PM PDT 24	2991518972 ps
T183	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.273545342			Jul 11 08:23:59 PM PDT 24	Jul 11 08:33:36 PM PDT 24	7230838600 ps
T133	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.366969795			Jul 11 08:29:00 PM PDT 24	Jul 11 08:38:05 PM PDT 24	5745352300 ps
T122	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2308720702			Jul 11 08:30:10 PM PDT 24	Jul 11 08:39:51 PM PDT 24	4884115160 ps
T220	/workspace/coverage/default/74.chip_sw_all_escalation_resets.1856233754			Jul 11 08:38:07 PM PDT 24	Jul 11 08:49:21 PM PDT 24	4678000512 ps
T163	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3129781329			Jul 11 08:04:43 PM PDT 24	Jul 11 11:26:54 PM PDT 24	255143951130 ps
T167	/workspace/coverage/default/5.chip_sw_all_escalation_resets.1623366170			Jul 11 08:27:31 PM PDT 24	Jul 11 08:38:29 PM PDT 24	5081222320 ps
T69	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2927463309			Jul 11 08:29:04 PM PDT 24	Jul 11 08:32:49 PM PDT 24	3723674629 ps
T287	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3037008310			Jul 11 08:02:52 PM PDT 24	Jul 11 08:34:01 PM PDT 24	8977323400 ps
T70	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2156610691			Jul 11 08:21:02 PM PDT 24	Jul 11 08:29:33 PM PDT 24	4607439656 ps
T243	/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.93559853			Jul 11 08:20:19 PM PDT 24	Jul 11 08:48:47 PM PDT 24	13275081796 ps
T221	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.696233832			Jul 11 08:24:27 PM PDT 24	Jul 11 08:33:08 PM PDT 24	5399711168 ps
T288	/workspace/coverage/default/2.chip_sw_hmac_smoketest.4151248237			Jul 11 08:32:49 PM PDT 24	Jul 11 08:38:06 PM PDT 24	3071583276 ps
T927	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.212409694			Jul 11 08:26:00 PM PDT 24	Jul 11 08:33:23 PM PDT 24	2989208312 ps
T71	/workspace/coverage/default/2.chip_jtag_csr_rw.2869301943			Jul 11 08:15:08 PM PDT 24	Jul 11 08:36:50 PM PDT 24	10789997168 ps
T63	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3800966740			Jul 11 08:04:03 PM PDT 24	Jul 11 08:06:23 PM PDT 24	2929100546 ps
T131	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.4119465262			Jul 11 08:11:15 PM PDT 24	Jul 11 08:45:36 PM PDT 24	9332355402 ps
T728	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2349382187			Jul 11 08:21:08 PM PDT 24	Jul 11 08:32:38 PM PDT 24	4954975560 ps
T128	/workspace/coverage/default/1.chip_sw_edn_auto_mode.1284211827			Jul 11 08:10:41 PM PDT 24	Jul 11 08:48:35 PM PDT 24	7306680230 ps
T349	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.12607891			Jul 11 08:22:08 PM PDT 24	Jul 11 08:33:45 PM PDT 24	4817008358 ps
T749	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1912091689			Jul 11 08:36:44 PM PDT 24	Jul 11 08:41:52 PM PDT 24	3672177394 ps
T172	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2071092034			Jul 11 08:08:56 PM PDT 24	Jul 11 08:10:49 PM PDT 24	2063376246 ps
T928	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1276892982			Jul 11 08:29:29 PM PDT 24	Jul 11 08:33:57 PM PDT 24	3445835390 ps
T123	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2645198370			Jul 11 08:03:17 PM PDT 24	Jul 11 09:30:06 PM PDT 24	46973981275 ps
T224	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.824361872			Jul 11 08:11:22 PM PDT 24	Jul 11 08:24:00 PM PDT 24	6144665176 ps
T254	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.624335743			Jul 11 08:08:36 PM PDT 24	Jul 11 08:29:19 PM PDT 24	11942872085 ps
T399	/workspace/coverage/default/1.rom_e2e_asm_init_rma.3986647647			Jul 11 08:26:19 PM PDT 24	Jul 11 09:29:46 PM PDT 24	14980989934 ps
T129	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2076027210			Jul 11 08:06:00 PM PDT 24	Jul 11 08:19:01 PM PDT 24	6555224431 ps
T153	/workspace/coverage/default/1.chip_sw_otbn_smoketest.1318849218			Jul 11 08:23:44 PM PDT 24	Jul 11 08:58:26 PM PDT 24	8185689196 ps
T84	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.4181960765			Jul 11 08:37:18 PM PDT 24	Jul 11 08:45:19 PM PDT 24	4099066280 ps
T95	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.777770161			Jul 11 08:08:21 PM PDT 24	Jul 11 08:25:18 PM PDT 24	6617007754 ps
T96	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1186896381			Jul 11 08:24:36 PM PDT 24	Jul 11 08:32:43 PM PDT 24	4391488440 ps
T29	/workspace/coverage/default/0.chip_sw_usbdev_stream.3649086814			Jul 11 08:01:13 PM PDT 24	Jul 11 09:14:57 PM PDT 24	18443456200 ps
T97	/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1189787853			Jul 11 08:05:44 PM PDT 24	Jul 11 08:58:59 PM PDT 24	24155013015 ps
T98	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3096306950			Jul 11 08:07:37 PM PDT 24	Jul 11 08:11:01 PM PDT 24	2781890590 ps
T99	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3564318040			Jul 11 08:23:57 PM PDT 24	Jul 11 08:29:37 PM PDT 24	4871160300 ps
T100	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1093335362			Jul 11 08:32:56 PM PDT 24	Jul 11 08:40:32 PM PDT 24	3336222440 ps
T101	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.727727026			Jul 11 08:23:42 PM PDT 24	Jul 11 08:27:52 PM PDT 24	2589433537 ps
T102	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.4169233930			Jul 11 08:09:56 PM PDT 24	Jul 11 08:16:25 PM PDT 24	3589422498 ps
T929	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2828331524			Jul 11 08:21:03 PM PDT 24	Jul 11 08:29:09 PM PDT 24	3311644552 ps
T240	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1543216029			Jul 11 08:05:49 PM PDT 24	Jul 11 08:19:18 PM PDT 24	6488361392 ps
T731	/workspace/coverage/default/4.chip_sw_all_escalation_resets.2520642561			Jul 11 08:31:05 PM PDT 24	Jul 11 08:41:45 PM PDT 24	5438612452 ps
T930	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2803856112			Jul 11 08:12:49 PM PDT 24	Jul 11 08:17:31 PM PDT 24	3399523568 ps
T177	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1729920089			Jul 11 08:31:07 PM PDT 24	Jul 11 08:49:27 PM PDT 24	13479937986 ps
T931	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.927460679			Jul 11 08:21:48 PM PDT 24	Jul 11 08:25:16 PM PDT 24	2402427160 ps
T182	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1929681219			Jul 11 08:08:32 PM PDT 24	Jul 11 08:10:49 PM PDT 24	3093649058 ps
T31	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2345841553			Jul 11 08:26:56 PM PDT 24	Jul 11 08:53:49 PM PDT 24	23704515682 ps
T932	/workspace/coverage/default/1.chip_sw_aes_idle.2289458731			Jul 11 08:09:21 PM PDT 24	Jul 11 08:12:21 PM PDT 24	3506441800 ps
T164	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1994395451			Jul 11 08:29:03 PM PDT 24	Jul 11 08:35:24 PM PDT 24	3339031794 ps
T222	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2557293886			Jul 11 08:27:08 PM PDT 24	Jul 11 08:54:14 PM PDT 24	8474864064 ps
T933	/workspace/coverage/default/1.chip_sw_aes_entropy.1659727806			Jul 11 08:11:06 PM PDT 24	Jul 11 08:13:56 PM PDT 24	2415754760 ps
T174	/workspace/coverage/default/91.chip_sw_all_escalation_resets.4047344308			Jul 11 08:39:05 PM PDT 24	Jul 11 08:50:24 PM PDT 24	6093178200 ps
T406	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.693836789			Jul 11 08:28:11 PM PDT 24	Jul 11 08:34:56 PM PDT 24	4970023652 ps
T440	/workspace/coverage/default/1.chip_sw_example_flash.2390872217			Jul 11 08:05:19 PM PDT 24	Jul 11 08:07:47 PM PDT 24	2470811352 ps
T441	/workspace/coverage/default/0.chip_sw_aes_masking_off.1421169961			Jul 11 08:03:00 PM PDT 24	Jul 11 08:08:32 PM PDT 24	3688850607 ps
T173	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.519745675			Jul 11 08:24:44 PM PDT 24	Jul 11 08:41:02 PM PDT 24	7641867856 ps
T442	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.563211478			Jul 11 08:01:18 PM PDT 24	Jul 11 08:07:13 PM PDT 24	3014711720 ps
T181	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1015841977			Jul 11 08:00:38 PM PDT 24	Jul 11 08:41:46 PM PDT 24	23422020359 ps
T443	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.35290127			Jul 11 08:38:30 PM PDT 24	Jul 11 08:47:04 PM PDT 24	3267558710 ps
T21	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2122425833			Jul 11 08:23:49 PM PDT 24	Jul 11 08:29:19 PM PDT 24	2908550330 ps
T251	/workspace/coverage/default/0.chip_sw_rv_timer_irq.1162274374			Jul 11 08:03:41 PM PDT 24	Jul 11 08:06:57 PM PDT 24	3333437288 ps
T444	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3545084972			Jul 11 08:12:29 PM PDT 24	Jul 11 08:18:37 PM PDT 24	3503003516 ps
T400	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3057704845			Jul 11 08:35:25 PM PDT 24	Jul 11 09:32:45 PM PDT 24	14965277596 ps
T744	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2231510839			Jul 11 08:38:37 PM PDT 24	Jul 11 08:45:10 PM PDT 24	3507484000 ps
T934	/workspace/coverage/default/1.chip_sw_example_rom.1099774354			Jul 11 08:08:45 PM PDT 24	Jul 11 08:11:17 PM PDT 24	2540525224 ps
T319	/workspace/coverage/default/72.chip_sw_all_escalation_resets.3092345024			Jul 11 08:37:54 PM PDT 24	Jul 11 08:47:55 PM PDT 24	4781964478 ps
T45	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.751672754			Jul 11 08:02:46 PM PDT 24	Jul 11 08:07:59 PM PDT 24	2541601416 ps
T165	/workspace/coverage/default/86.chip_sw_all_escalation_resets.3439008379			Jul 11 08:37:45 PM PDT 24	Jul 11 08:45:38 PM PDT 24	4844185008 ps
T124	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2118031666			Jul 11 08:27:19 PM PDT 24	Jul 11 08:40:18 PM PDT 24	4293699218 ps
T55	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2474504120			Jul 11 08:30:47 PM PDT 24	Jul 11 09:32:13 PM PDT 24	14543949352 ps
T935	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2224794240			Jul 11 08:12:27 PM PDT 24	Jul 11 09:35:05 PM PDT 24	15340220930 ps
T28	/workspace/coverage/default/1.chip_sw_gpio_smoketest.1241554310			Jul 11 08:22:31 PM PDT 24	Jul 11 08:26:50 PM PDT 24	2410565398 ps
T936	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3779692134			Jul 11 08:27:20 PM PDT 24	Jul 11 08:33:35 PM PDT 24	7280467788 ps
T750	/workspace/coverage/default/40.chip_sw_all_escalation_resets.1515557228			Jul 11 08:35:25 PM PDT 24	Jul 11 08:45:29 PM PDT 24	5307425074 ps
T219	/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1350492215			Jul 11 08:05:19 PM PDT 24	Jul 11 08:51:25 PM PDT 24	29243851970 ps
T258	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.4290155576			Jul 11 08:06:21 PM PDT 24	Jul 11 09:52:40 PM PDT 24	27010976972 ps
T355	/workspace/coverage/default/85.chip_sw_all_escalation_resets.3728244988			Jul 11 08:42:25 PM PDT 24	Jul 11 08:49:55 PM PDT 24	5030075268 ps
T255	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.983598252			Jul 11 08:07:46 PM PDT 24	Jul 11 08:31:54 PM PDT 24	14720220882 ps
T376	/workspace/coverage/default/0.chip_tap_straps_dev.1732000038			Jul 11 08:04:08 PM PDT 24	Jul 11 08:08:00 PM PDT 24	3377379800 ps
T125	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.31249878			Jul 11 08:03:03 PM PDT 24	Jul 11 08:11:32 PM PDT 24	3726663438 ps
T746	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.4105706901			Jul 11 08:37:16 PM PDT 24	Jul 11 08:42:57 PM PDT 24	3934230654 ps
T350	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.522750708			Jul 11 08:21:00 PM PDT 24	Jul 11 08:32:12 PM PDT 24	4167162044 ps
T695	/workspace/coverage/default/71.chip_sw_all_escalation_resets.2692053917			Jul 11 08:37:09 PM PDT 24	Jul 11 08:47:30 PM PDT 24	5403890020 ps
T815	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2269591504			Jul 11 08:31:39 PM PDT 24	Jul 11 08:38:28 PM PDT 24	3759752364 ps
T184	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2363630324			Jul 11 08:02:18 PM PDT 24	Jul 11 08:12:24 PM PDT 24	6527814688 ps
T356	/workspace/coverage/default/43.chip_sw_all_escalation_resets.2347010193			Jul 11 08:36:21 PM PDT 24	Jul 11 08:44:05 PM PDT 24	4260104734 ps
T233	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2491938819			Jul 11 08:09:20 PM PDT 24	Jul 11 09:45:43 PM PDT 24	48416020504 ps
T394	/workspace/coverage/default/3.chip_sw_all_escalation_resets.2596242071			Jul 11 08:25:50 PM PDT 24	Jul 11 08:34:59 PM PDT 24	5626830306 ps
T937	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1076087740			Jul 11 08:07:59 PM PDT 24	Jul 11 08:14:18 PM PDT 24	4170005372 ps
T30	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2926993429			Jul 11 08:06:49 PM PDT 24	Jul 11 08:15:13 PM PDT 24	5331554304 ps
T271	/workspace/coverage/default/0.rom_volatile_raw_unlock.3732326450			Jul 11 08:09:25 PM PDT 24	Jul 11 08:11:12 PM PDT 24	2372025324 ps
T152	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3103063523			Jul 11 07:59:49 PM PDT 24	Jul 11 08:45:55 PM PDT 24	13509387987 ps
T225	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1941806564			Jul 11 08:06:52 PM PDT 24	Jul 11 08:16:08 PM PDT 24	4257144723 ps
T156	/workspace/coverage/default/0.rom_raw_unlock.4231763036			Jul 11 08:08:45 PM PDT 24	Jul 11 08:12:32 PM PDT 24	5871579223 ps
T367	/workspace/coverage/default/57.chip_sw_all_escalation_resets.2198222699			Jul 11 08:41:54 PM PDT 24	Jul 11 08:49:55 PM PDT 24	5740619864 ps
T729	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3310110520			Jul 11 08:22:16 PM PDT 24	Jul 11 08:34:11 PM PDT 24	4935613784 ps
T67	/workspace/coverage/default/4.chip_tap_straps_testunlock0.477822360			Jul 11 08:26:30 PM PDT 24	Jul 11 08:29:33 PM PDT 24	2432556767 ps
T303	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3508397536			Jul 11 08:29:25 PM PDT 24	Jul 11 09:02:49 PM PDT 24	13349798664 ps
T368	/workspace/coverage/default/52.chip_sw_all_escalation_resets.299664479			Jul 11 08:38:33 PM PDT 24	Jul 11 08:49:35 PM PDT 24	5578942684 ps
T22	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2064462447			Jul 11 08:10:09 PM PDT 24	Jul 11 08:14:55 PM PDT 24	3357678804 ps
T273	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.4080008555			Jul 11 08:04:26 PM PDT 24	Jul 11 08:17:32 PM PDT 24	5801557758 ps
T276	/workspace/coverage/default/2.chip_sw_example_concurrency.736457549			Jul 11 08:24:41 PM PDT 24	Jul 11 08:30:08 PM PDT 24	2727716600 ps
T24	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1081317644			Jul 11 08:24:01 PM PDT 24	Jul 11 08:34:12 PM PDT 24	5173663539 ps
T168	/workspace/coverage/default/37.chip_sw_all_escalation_resets.3836827925			Jul 11 08:34:56 PM PDT 24	Jul 11 08:45:31 PM PDT 24	5692733020 ps
T232	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2030107943			Jul 11 08:08:55 PM PDT 24	Jul 11 09:53:05 PM PDT 24	49009810917 ps
T248	/workspace/coverage/default/1.chip_sw_plic_sw_irq.1749427658			Jul 11 08:19:53 PM PDT 24	Jul 11 08:24:10 PM PDT 24	2183649972 ps
T277	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2091717806			Jul 11 08:01:31 PM PDT 24	Jul 11 08:20:15 PM PDT 24	5179795275 ps
T278	/workspace/coverage/default/2.chip_sw_all_escalation_resets.3631455784			Jul 11 08:22:56 PM PDT 24	Jul 11 08:33:41 PM PDT 24	5782193400 ps
T279	/workspace/coverage/default/63.chip_sw_all_escalation_resets.1131183071			Jul 11 08:36:09 PM PDT 24	Jul 11 08:45:34 PM PDT 24	4789806994 ps
T68	/workspace/coverage/default/1.chip_tap_straps_testunlock0.3404757694			Jul 11 08:20:35 PM PDT 24	Jul 11 08:23:40 PM PDT 24	2877133147 ps
T139	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1495596405			Jul 11 08:30:13 PM PDT 24	Jul 11 08:43:56 PM PDT 24	7263092316 ps
T119	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.395333187			Jul 11 08:10:48 PM PDT 24	Jul 11 08:34:25 PM PDT 24	6307446237 ps
T120	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3259337365			Jul 11 08:00:52 PM PDT 24	Jul 11 08:45:15 PM PDT 24	13995783812 ps
T388	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.4077516145			Jul 11 08:35:57 PM PDT 24	Jul 11 08:42:09 PM PDT 24	3627937150 ps
T154	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2909677723			Jul 11 08:03:24 PM PDT 24	Jul 11 09:12:32 PM PDT 24	18200290629 ps
T241	/workspace/coverage/default/7.chip_sw_all_escalation_resets.3882778555			Jul 11 08:28:43 PM PDT 24	Jul 11 08:37:16 PM PDT 24	4936264800 ps
T186	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.719592042			Jul 11 08:05:23 PM PDT 24	Jul 11 08:09:05 PM PDT 24	3094732217 ps
T264	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2127130921			Jul 11 08:26:22 PM PDT 24	Jul 11 09:07:24 PM PDT 24	11804336448 ps
T32	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.303953538			Jul 11 08:02:28 PM PDT 24	Jul 11 08:27:08 PM PDT 24	22513025774 ps
T265	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.164403292			Jul 11 08:06:24 PM PDT 24	Jul 11 08:19:14 PM PDT 24	4986069570 ps
T266	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.63585311			Jul 11 08:07:12 PM PDT 24	Jul 11 08:11:31 PM PDT 24	2520082440 ps
T267	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.872630675			Jul 11 08:21:05 PM PDT 24	Jul 11 08:25:11 PM PDT 24	3449829057 ps
T268	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3109386636			Jul 11 08:06:55 PM PDT 24	Jul 11 08:16:57 PM PDT 24	4215941264 ps
T269	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1677817462			Jul 11 08:02:41 PM PDT 24	Jul 11 08:08:31 PM PDT 24	2957886091 ps
T270	/workspace/coverage/default/77.chip_sw_all_escalation_resets.1798124784			Jul 11 08:37:02 PM PDT 24	Jul 11 08:46:26 PM PDT 24	6664791954 ps
T360	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2270960614			Jul 11 08:02:09 PM PDT 24	Jul 11 08:12:03 PM PDT 24	4345862934 ps
T814	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.629788057			Jul 11 08:36:18 PM PDT 24	Jul 11 08:41:16 PM PDT 24	3272853840 ps
T214	/workspace/coverage/default/20.chip_sw_all_escalation_resets.381828058			Jul 11 08:32:36 PM PDT 24	Jul 11 08:41:04 PM PDT 24	5598389536 ps
T85	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.2896607256			Jul 11 08:10:08 PM PDT 24	Jul 11 08:14:13 PM PDT 24	3602199953 ps
T205	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2138770838			Jul 11 08:25:28 PM PDT 24	Jul 11 08:37:36 PM PDT 24	4379847621 ps
T155	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.694535680			Jul 11 08:12:37 PM PDT 24	Jul 11 09:20:14 PM PDT 24	17551601368 ps
T692	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.929585321			Jul 11 08:36:13 PM PDT 24	Jul 11 08:43:38 PM PDT 24	3516156400 ps
T366	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2170223390			Jul 11 08:26:33 PM PDT 24	Jul 11 08:52:14 PM PDT 24	7998481590 ps
T938	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.4291727444			Jul 11 08:21:50 PM PDT 24	Jul 11 08:25:56 PM PDT 24	2584253086 ps
T178	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2070056941			Jul 11 08:05:44 PM PDT 24	Jul 11 08:14:31 PM PDT 24	5567761448 ps
T460	/workspace/coverage/default/1.chip_sw_kmac_idle.3677727405			Jul 11 08:19:39 PM PDT 24	Jul 11 08:24:52 PM PDT 24	2942584150 ps
T274	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.827059990			Jul 11 08:25:35 PM PDT 24	Jul 11 08:39:16 PM PDT 24	4641198952 ps
T135	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.164780932			Jul 11 08:26:56 PM PDT 24	Jul 11 08:40:30 PM PDT 24	7113466246 ps
T223	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2117816161			Jul 11 08:01:17 PM PDT 24	Jul 11 08:11:08 PM PDT 24	5817262307 ps
T939	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.1938079244			Jul 11 08:20:08 PM PDT 24	Jul 11 08:24:54 PM PDT 24	2563958111 ps
T940	/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.924690751			Jul 11 08:03:10 PM PDT 24	Jul 11 08:08:14 PM PDT 24	2966478410 ps
T773	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1751126921			Jul 11 08:35:05 PM PDT 24	Jul 11 08:41:21 PM PDT 24	3509610008 ps
T130	/workspace/coverage/default/0.chip_sw_edn_kat.3374488512			Jul 11 08:02:58 PM PDT 24	Jul 11 08:12:27 PM PDT 24	3790279144 ps
T337	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1622741277			Jul 11 08:31:08 PM PDT 24	Jul 11 09:09:57 PM PDT 24	13794815944 ps
T300	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.545622868			Jul 11 08:23:00 PM PDT 24	Jul 11 08:37:29 PM PDT 24	6698050639 ps
T336	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3677262824			Jul 11 08:31:43 PM PDT 24	Jul 11 08:41:04 PM PDT 24	4142734172 ps
T226	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1912985745			Jul 11 08:21:40 PM PDT 24	Jul 11 08:32:55 PM PDT 24	5765000088 ps
T941	/workspace/coverage/default/0.chip_sw_uart_smoketest.272216517			Jul 11 08:09:22 PM PDT 24	Jul 11 08:13:32 PM PDT 24	3596649738 ps
T942	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.370691530			Jul 11 08:05:57 PM PDT 24	Jul 11 08:11:55 PM PDT 24	5119479804 ps
T33	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3670491314			Jul 11 08:02:37 PM PDT 24	Jul 11 09:06:29 PM PDT 24	20764674994 ps
T157	/workspace/coverage/default/1.rom_raw_unlock.240736412			Jul 11 08:22:16 PM PDT 24	Jul 11 08:27:25 PM PDT 24	5643322344 ps
T280	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3941606202			Jul 11 08:29:07 PM PDT 24	Jul 11 08:37:39 PM PDT 24	4015878504 ps
T943	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2182645953			Jul 11 08:24:54 PM PDT 24	Jul 11 08:34:02 PM PDT 24	5236631922 ps
T134	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2885870246			Jul 11 08:02:56 PM PDT 24	Jul 11 08:13:59 PM PDT 24	6506317498 ps
T944	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2530963760			Jul 11 08:12:56 PM PDT 24	Jul 11 08:17:04 PM PDT 24	2657459810 ps
T158	/workspace/coverage/default/2.rom_raw_unlock.3737963329			Jul 11 08:26:41 PM PDT 24	Jul 11 08:30:29 PM PDT 24	3907116857 ps
T945	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3290601704			Jul 11 08:23:19 PM PDT 24	Jul 11 09:03:04 PM PDT 24	32184327486 ps
T217	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.746310049			Jul 11 08:08:06 PM PDT 24	Jul 11 08:17:08 PM PDT 24	3339035484 ps
T743	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.43332869			Jul 11 08:06:46 PM PDT 24	Jul 11 08:26:33 PM PDT 24	7626030656 ps
T946	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1949060452			Jul 11 08:03:24 PM PDT 24	Jul 11 08:13:57 PM PDT 24	4845474152 ps
T838	/workspace/coverage/default/82.chip_sw_all_escalation_resets.3193195441			Jul 11 08:38:06 PM PDT 24	Jul 11 08:49:39 PM PDT 24	5899233516 ps
T947	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3069536192			Jul 11 08:24:44 PM PDT 24	Jul 11 08:35:40 PM PDT 24	5744919976 ps
T948	/workspace/coverage/default/1.chip_sw_flash_crash_alert.1734596144			Jul 11 08:21:05 PM PDT 24	Jul 11 08:33:42 PM PDT 24	6405920360 ps
T378	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2544899125			Jul 11 08:09:52 PM PDT 24	Jul 11 09:11:18 PM PDT 24	15865045892 ps
T949	/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.90080628			Jul 11 08:25:18 PM PDT 24	Jul 11 08:29:24 PM PDT 24	2316587446 ps
T56	/workspace/coverage/default/2.rom_e2e_shutdown_output.1535229689			Jul 11 08:29:56 PM PDT 24	Jul 11 09:26:35 PM PDT 24	28840385400 ps
T950	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.638769552			Jul 11 08:30:56 PM PDT 24	Jul 11 08:39:38 PM PDT 24	5646187652 ps
T361	/workspace/coverage/default/1.chip_sival_flash_info_access.3563282890			Jul 11 08:07:24 PM PDT 24	Jul 11 08:13:00 PM PDT 24	3547931040 ps
T951	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1400259064			Jul 11 08:11:39 PM PDT 24	Jul 11 10:03:47 PM PDT 24	23386415136 ps
T320	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.263686383			Jul 11 08:37:00 PM PDT 24	Jul 11 08:43:05 PM PDT 24	3387562978 ps
T952	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2927505924			Jul 11 08:29:32 PM PDT 24	Jul 11 08:35:54 PM PDT 24	2956176808 ps
T115	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.86375031			Jul 11 08:12:40 PM PDT 24	Jul 11 08:22:05 PM PDT 24	19166976050 ps
T72	/workspace/coverage/default/0.chip_tap_straps_testunlock0.1037102765			Jul 11 08:05:47 PM PDT 24	Jul 11 08:09:08 PM PDT 24	3473472787 ps
T245	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.4035691484			Jul 11 08:37:59 PM PDT 24	Jul 11 08:44:35 PM PDT 24	3421768790 ps
T290	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.543380614			Jul 11 08:23:25 PM PDT 24	Jul 11 08:28:30 PM PDT 24	2279422020 ps
T291	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3362854179			Jul 11 08:02:44 PM PDT 24	Jul 11 08:12:21 PM PDT 24	3653799296 ps
T292	/workspace/coverage/default/76.chip_sw_all_escalation_resets.2893256998			Jul 11 08:37:39 PM PDT 24	Jul 11 08:48:07 PM PDT 24	4786535964 ps
T215	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1507278555			Jul 11 08:03:17 PM PDT 24	Jul 11 08:25:58 PM PDT 24	7715742014 ps
T293	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1941165988			Jul 11 08:11:28 PM PDT 24	Jul 11 09:19:14 PM PDT 24	14728223070 ps
T294	/workspace/coverage/default/24.chip_sw_all_escalation_resets.1598773339			Jul 11 08:36:06 PM PDT 24	Jul 11 08:45:26 PM PDT 24	4729310734 ps
T295	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.959029847			Jul 11 08:28:06 PM PDT 24	Jul 11 08:36:13 PM PDT 24	4059303648 ps
T296	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1341084536			Jul 11 08:08:59 PM PDT 24	Jul 11 08:55:28 PM PDT 24	24493210500 ps
T297	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2377103538			Jul 11 08:32:02 PM PDT 24	Jul 11 08:40:02 PM PDT 24	4011383520 ps
T855	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.948195612			Jul 11 08:33:34 PM PDT 24	Jul 11 08:39:27 PM PDT 24	4098163096 ps
T787	/workspace/coverage/default/36.chip_sw_all_escalation_resets.2696954781			Jul 11 08:34:27 PM PDT 24	Jul 11 08:43:17 PM PDT 24	5322454456 ps
T227	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2093118745			Jul 11 08:19:56 PM PDT 24	Jul 11 09:13:03 PM PDT 24	12398173932 ps
T953	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1698725067			Jul 11 08:02:30 PM PDT 24	Jul 11 08:11:30 PM PDT 24	4544712814 ps
T753	/workspace/coverage/default/80.chip_sw_all_escalation_resets.4263771814			Jul 11 08:37:39 PM PDT 24	Jul 11 08:48:10 PM PDT 24	5661008040 ps
T954	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1303544030			Jul 11 08:02:23 PM PDT 24	Jul 11 08:14:53 PM PDT 24	3576826312 ps
T955	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3821920935			Jul 11 08:03:47 PM PDT 24	Jul 11 08:13:32 PM PDT 24	5127915160 ps
T74	/workspace/coverage/default/1.chip_tap_straps_prod.4056375424			Jul 11 08:20:11 PM PDT 24	Jul 11 08:30:46 PM PDT 24	6933709437 ps
T244	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.3296445581			Jul 11 08:28:51 PM PDT 24	Jul 11 08:35:14 PM PDT 24	4565462592 ps
T747	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4107910173			Jul 11 08:37:05 PM PDT 24	Jul 11 08:43:02 PM PDT 24	3987290300 ps
T242	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1934498401			Jul 11 08:09:42 PM PDT 24	Jul 11 08:20:53 PM PDT 24	6823170500 ps
T956	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3720802710			Jul 11 08:22:35 PM PDT 24	Jul 11 08:27:18 PM PDT 24	3547139243 ps
T401	/workspace/coverage/default/2.chip_sw_kmac_app_rom.1000859796			Jul 11 08:28:29 PM PDT 24	Jul 11 08:31:23 PM PDT 24	2595450094 ps
T1	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2148833316			Jul 11 08:03:36 PM PDT 24	Jul 11 08:34:25 PM PDT 24	23256445464 ps
T107	/workspace/coverage/default/22.chip_sw_all_escalation_resets.2229097242			Jul 11 08:33:11 PM PDT 24	Jul 11 08:44:59 PM PDT 24	5802876012 ps
T108	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.977730266			Jul 11 08:01:32 PM PDT 24	Jul 11 08:20:40 PM PDT 24	8506000906 ps
T109	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1838013981			Jul 11 08:24:40 PM PDT 24	Jul 11 08:32:08 PM PDT 24	4171762270 ps
T110	/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2218113395			Jul 11 08:26:54 PM PDT 24	Jul 11 08:36:05 PM PDT 24	2877471752 ps
T111	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.2673435610			Jul 11 08:27:42 PM PDT 24	Jul 11 08:32:02 PM PDT 24	2673590744 ps
T86	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.3525693700			Jul 11 08:27:43 PM PDT 24	Jul 11 08:34:04 PM PDT 24	3658215659 ps
T112	/workspace/coverage/default/89.chip_sw_all_escalation_resets.2998774135			Jul 11 08:42:33 PM PDT 24	Jul 11 08:50:49 PM PDT 24	5112236430 ps
T113	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1229176006			Jul 11 08:25:14 PM PDT 24	Jul 11 08:32:27 PM PDT 24	4464674808 ps
T114	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1440282101			Jul 11 08:07:20 PM PDT 24	Jul 11 08:59:20 PM PDT 24	12762026961 ps
T957	/workspace/coverage/default/1.rom_keymgr_functest.1940131603			Jul 11 08:23:47 PM PDT 24	Jul 11 08:35:29 PM PDT 24	4880111808 ps
T116	/workspace/coverage/default/1.chip_sw_power_sleep_load.2255331739			Jul 11 08:21:56 PM PDT 24	Jul 11 08:31:59 PM PDT 24	10324982978 ps
T281	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2808600550			Jul 11 08:29:24 PM PDT 24	Jul 11 08:40:21 PM PDT 24	5688422528 ps
T259	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.944812148			Jul 11 08:26:11 PM PDT 24	Jul 11 09:17:09 PM PDT 24	14880632960 ps
T760	/workspace/coverage/default/12.chip_sw_all_escalation_resets.3767221976			Jul 11 08:31:56 PM PDT 24	Jul 11 08:40:49 PM PDT 24	4047866510 ps