Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	159277	1			T78	6		T79	9		T80	279
values[2]	4455	1			T83	3		T792	1		T462	2
values[3]	2317	1			T792	1		T521	1		T653	47
values[4]	1593	1			T792	1		T653	59		T862	60
values[5]	1185	1			T792	1		T653	53		T862	37
values[6]	1062	1			T792	1		T653	44		T862	42
values[7]	945	1			T792	1		T653	48		T862	37
values[8]	880	1			T792	1		T653	54		T862	22
values[9]	718	1			T792	1		T653	31		T862	5
values[10]	664	1			T792	1		T653	15		T862	8
values[11]	635	1			T792	1		T653	31		T862	10
values[12]	557	1			T792	1		T653	24		T862	34
values[13]	550	1			T792	1		T653	28		T862	38
values[14]	481	1			T792	1		T653	25		T862	37
values[15]	359	1			T792	1		T653	8		T862	20
values[16]	284	1			T792	1		T653	9		T862	28
values[17]	279	1			T792	1		T653	3		T862	9
values[18]	220	1			T792	1		T862	1		T876	5
values[19]	185	1			T792	1		T862	1		T876	4
values[20]	231	1			T792	1		T876	13		T577	6
values[21]	240	1			T792	1		T876	17		T577	4
values[22]	237	1			T792	1		T876	13		T577	4
values[23]	206	1			T792	1		T876	6		T577	3
values[24]	232	1			T792	1		T876	2		T577	5
values[25]	198	1			T792	1		T577	6		T592	3
values[26]	192	1			T792	1		T577	10		T592	8
values[27]	210	1			T792	1		T577	10		T592	39
values[28]	179	1			T792	1		T577	5		T592	35
values[29]	131	1			T792	1		T577	8		T592	22
values[30]	128	1			T792	1		T577	6		T592	23
values[31]	105	1			T792	1		T577	3		T592	19
values[32]	128	1			T792	1		T577	4		T592	41
values[33]	121	1			T792	1		T577	5		T592	38
values[34]	130	1			T792	1		T577	4		T592	46
values[35]	123	1			T792	1		T577	2		T592	43
values[36]	130	1			T792	1		T577	4		T592	47
values[37]	80	1			T792	1		T577	2		T592	8
values[38]	76	1			T792	1		T577	5		T509	16
values[39]	55	1			T792	1		T577	2		T509	5
values[40]	50	1			T792	1		T577	3		T509	3
values[41]	61	1			T792	1		T577	12		T505	1
values[42]	65	1			T792	1		T577	16		T505	1
values[43]	60	1			T792	1		T577	10		T505	1
values[44]	67	1			T792	1		T577	12		T505	1
values[45]	49	1			T792	1		T577	3		T505	1
values[46]	50	1			T792	1		T577	5		T505	1
values[47]	49	1			T792	1		T577	3		T505	1
values[48]	58	1			T792	1		T577	6		T505	1
values[49]	51	1			T792	1		T577	5		T505	1
values[50]	79	1			T792	1		T577	5		T505	1
values[51]	64	1			T792	1		T577	6		T505	1
values[52]	59	1			T792	1		T577	4		T505	1
values[53]	51	1			T792	1		T577	2		T505	1
values[54]	63	1			T792	1		T577	4		T505	1
values[55]	45	1			T792	1		T577	3		T505	1
values[56]	56	1			T792	1		T577	3		T505	1
values[57]	58	1			T792	1		T577	3		T505	1
values[58]	42	1			T792	1		T577	4		T505	1
values[59]	53	1			T792	1		T577	8		T505	1
values[60]	59	1			T792	1		T577	8		T505	1
values[61]	61	1			T792	1		T577	3		T505	1
values[62]	52	1			T792	1		T577	4		T505	1
values[63]	55	1			T792	1		T577	4		T505	1
values[64]	48	1			T792	1		T577	7		T505	1
values[65]	67	1			T792	1		T577	10		T505	1
values[66]	55	1			T792	1		T577	5		T505	1
values[67]	52	1			T792	1		T577	5		T505	1
values[68]	50	1			T792	1		T577	3		T505	1
values[69]	55	1			T792	1		T577	4		T505	1
values[70]	62	1			T792	1		T577	5		T505	1
values[71]	53	1			T792	1		T577	6		T505	1
values[72]	58	1			T792	1		T577	7		T505	1
values[73]	59	1			T792	1		T577	4		T505	1
values[74]	54	1			T792	1		T577	4		T505	1
values[75]	66	1			T792	1		T577	4		T505	1
values[76]	79	1			T792	1		T577	5		T505	1
values[77]	59	1			T792	1		T577	3		T505	1
values[78]	55	1			T792	1		T577	6		T505	1
values[79]	51	1			T792	1		T577	3		T505	1
values[80]	45	1			T792	1		T577	3		T505	1
values[81]	68	1			T792	1		T577	9		T505	1
values[82]	57	1			T792	1		T577	5		T505	1
values[83]	59	1			T792	1		T577	8		T505	1
values[84]	63	1			T792	1		T577	8		T505	1
values[85]	66	1			T792	1		T577	5		T505	1
values[86]	69	1			T792	1		T577	6		T505	1
values[87]	71	1			T792	1		T577	9		T505	1
values[88]	67	1			T792	1		T577	7		T505	1
values[89]	68	1			T792	1		T577	7		T505	1
values[90]	68	1			T792	1		T577	10		T505	1
values[91]	63	1			T792	1		T577	9		T505	1
values[92]	71	1			T792	1		T577	7		T505	1
values[93]	83	1			T792	1		T577	8		T505	1
values[94]	84	1			T792	1		T577	4		T505	1
values[95]	68	1			T792	1		T577	7		T505	1
values[96]	70	1			T792	1		T577	6		T505	1
values[97]	66	1			T792	2		T577	4		T505	1
values[98]	81	1			T792	1		T577	5		T505	2
values[99]	93	1			T792	1		T577	4		T505	1
values[100]	70	1			T792	1		T577	2		T505	1
values[101]	71	1			T792	1		T577	4		T505	1
values[102]	72	1			T792	1		T577	4		T505	1
values[103]	72	1			T792	1		T577	5		T505	1
values[104]	84	1			T792	2		T577	5		T505	1
values[105]	82	1			T792	3		T577	3		T505	1
values[106]	90	1			T792	3		T577	8		T505	1
values[107]	104	1			T792	5		T577	9		T505	1
values[108]	72	1			T792	1		T577	5		T505	1
values[109]	80	1			T792	3		T577	10		T505	1
values[110]	115	1			T792	2		T577	11		T505	1
values[111]	88	1			T792	1		T577	11		T505	1
values[112]	84	1			T792	3		T577	4		T505	1
values[113]	82	1			T792	1		T577	10		T505	1
values[114]	86	1			T792	1		T577	11		T505	1
values[115]	94	1			T792	1		T577	8		T505	1
values[116]	97	1			T792	1		T577	8		T505	1
values[117]	116	1			T792	2		T577	14		T505	1
values[118]	116	1			T792	4		T577	5		T505	1
values[119]	101	1			T792	4		T577	7		T505	2
values[120]	109	1			T792	4		T577	7		T505	1
values[121]	138	1			T792	6		T577	11		T505	1
values[122]	121	1			T792	7		T577	6		T505	2
values[123]	130	1			T792	5		T577	16		T505	1
values[124]	206	1			T792	2		T577	41		T505	3
values[125]	395	1			T792	2		T577	70		T505	2
values[126]	812	1			T792	5		T577	111		T505	7
values[127]	2604	1			T792	119		T577	38		T505	119
values[128]	4466	1			T792	194		T577	2		T505	199