Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	495	1			T462	1		T521	2		T415	4
all_values[1]	502	1			T462	1		T540	1		T521	1
all_values[2]	476	1			T80	1		T540	5		T415	1
all_values[3]	476	1			T80	1		T792	1		T540	1
all_values[4]	506	1			T792	1		T462	2		T540	1
all_values[5]	530	1			T540	3		T521	2		T415	1
all_values[6]	515	1			T80	1		T540	3		T521	3
all_values[7]	492	1			T540	3		T521	2		T415	4
all_values[8]	547	1			T540	2		T521	1		T415	5
all_values[9]	487	1			T80	1		T462	2		T540	3
all_values[10]	468	1			T80	1		T462	1		T540	2
all_values[11]	530	1			T80	2		T792	1		T462	1
all_values[12]	492	1			T540	2		T415	4		T535	3
all_values[13]	483	1			T792	1		T462	1		T540	2
all_values[14]	503	1			T792	1		T540	2		T521	1
all_values[15]	526	1			T521	1		T415	1		T535	1
all_values[16]	513	1			T540	2		T521	2		T415	1
all_values[17]	535	1			T462	1		T540	3		T521	6
all_values[18]	520	1			T540	3		T415	3		T535	3
all_values[19]	496	1			T540	2		T521	1		T535	3
all_values[20]	510	1			T540	3		T521	1		T415	4
all_values[21]	478	1			T540	2		T521	2		T415	2
all_values[22]	460	1			T540	6		T521	3		T429	1
all_values[23]	512	1			T540	3		T415	4		T535	8
all_values[24]	510	1			T792	1		T462	2		T540	4
all_values[25]	484	1			T80	1		T462	2		T540	3
all_values[26]	502	1			T80	2		T540	3		T521	2
all_values[27]	514	1			T540	4		T521	3		T415	3
all_values[28]	481	1			T792	1		T540	3		T521	1
all_values[29]	462	1			T462	2		T540	8		T521	1
all_values[30]	553	1			T792	1		T540	1		T521	2
all_values[31]	506	1			T792	1		T462	1		T540	2
all_values[32]	519	1			T540	2		T415	4		T535	1
all_values[33]	498	1			T80	2		T540	4		T521	1
all_values[34]	482	1			T540	2		T521	2		T535	6
all_values[35]	495	1			T792	1		T540	5		T521	2
all_values[36]	489	1			T462	1		T540	3		T521	1
all_values[37]	464	1			T462	1		T540	5		T521	1
all_values[38]	521	1			T540	1		T521	3		T535	3
all_values[39]	535	1			T540	3		T415	3		T535	4
all_values[40]	473	1			T540	1		T521	2		T415	3
all_values[41]	485	1			T80	1		T462	2		T540	2
all_values[42]	491	1			T462	1		T540	2		T521	3
all_values[43]	474	1			T540	4		T521	1		T535	4
all_values[44]	494	1			T80	1		T540	1		T521	1
all_values[45]	519	1			T540	1		T521	2		T415	1
all_values[46]	446	1			T462	1		T540	4		T521	3
all_values[47]	522	1			T80	1		T462	1		T540	2
all_values[48]	491	1			T80	1		T462	1		T540	1
all_values[49]	462	1			T540	6		T521	1		T415	1