Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3543	1			T539	2		T462	11		T540	17
all_values[1]	3554	1			T539	2		T462	10		T540	22
all_values[2]	3509	1			T539	1		T462	4		T540	21
all_values[3]	3558	1			T462	10		T540	19		T521	10
all_values[4]	3496	1			T539	1		T462	4		T540	22
all_values[5]	3567	1			T539	2		T462	10		T540	30
all_values[6]	3489	1			T539	2		T462	6		T540	16
all_values[7]	3484	1			T462	7		T540	26		T521	8
all_values[8]	3686	1			T539	1		T462	5		T540	25
all_values[9]	3574	1			T539	1		T462	5		T540	19
all_values[10]	3533	1			T539	3		T462	7		T540	20
all_values[11]	3448	1			T539	2		T462	6		T540	23
all_values[12]	3515	1			T539	2		T462	8		T540	14
all_values[13]	3611	1			T462	6		T540	20		T521	9
all_values[14]	3423	1			T462	9		T540	22		T521	12
all_values[15]	3546	1			T539	1		T462	5		T540	23
all_values[16]	3439	1			T539	1		T462	6		T540	26
all_values[17]	3490	1			T539	4		T462	1		T540	18
all_values[18]	3581	1			T462	3		T540	19		T521	10
all_values[19]	3449	1			T539	2		T462	11		T540	19
all_values[20]	3513	1			T539	2		T462	13		T540	22
all_values[21]	3534	1			T462	3		T540	15		T521	11
all_values[22]	3492	1			T539	1		T462	4		T540	16
all_values[23]	3583	1			T539	1		T462	8		T540	11
all_values[24]	3478	1			T462	5		T540	17		T521	16
all_values[25]	3459	1			T462	5		T540	18		T521	18
all_values[26]	3590	1			T539	1		T462	5		T540	24
all_values[27]	3441	1			T539	1		T462	4		T540	20
all_values[28]	3529	1			T539	1		T462	10		T540	26
all_values[29]	3598	1			T539	1		T462	5		T540	19
all_values[30]	3577	1			T539	1		T462	4		T540	19
all_values[31]	3477	1			T539	1		T462	10		T540	17
all_values[32]	3521	1			T539	1		T462	9		T540	33
all_values[33]	3506	1			T539	2		T462	6		T540	28
all_values[34]	3558	1			T462	11		T540	24		T521	8
all_values[35]	3607	1			T539	5		T462	6		T540	18
all_values[36]	3551	1			T539	4		T462	9		T540	12
all_values[37]	3615	1			T539	3		T462	1		T540	26
all_values[38]	3506	1			T539	3		T462	4		T540	19
all_values[39]	3595	1			T539	3		T462	6		T540	14
all_values[40]	3408	1			T539	1		T462	4		T540	16
all_values[41]	3579	1			T539	2		T462	4		T540	27
all_values[42]	3595	1			T539	1		T462	9		T540	26
all_values[43]	3480	1			T539	2		T462	7		T540	21
all_values[44]	3534	1			T462	5		T540	23		T521	15
all_values[45]	3463	1			T539	1		T462	5		T540	21
all_values[46]	3424	1			T539	1		T462	5		T540	15
all_values[47]	3442	1			T539	4		T462	9		T540	15
all_values[48]	3525	1			T539	2		T462	8		T540	17
all_values[49]	3590	1			T462	9		T540	20		T521	9
all_values[50]	3537	1			T539	2		T462	7		T540	19
all_values[51]	3581	1			T539	1		T462	8		T540	22
all_values[52]	3580	1			T539	1		T462	7		T540	10
all_values[53]	3564	1			T539	2		T462	5		T540	13
all_values[54]	3479	1			T539	2		T462	8		T540	16
all_values[55]	3538	1			T539	2		T462	8		T540	19
all_values[56]	3503	1			T539	4		T462	7		T540	21
all_values[57]	3531	1			T462	7		T540	24		T521	9
all_values[58]	3532	1			T539	3		T462	6		T540	23
all_values[59]	3432	1			T539	2		T462	9		T540	17
all_values[60]	3494	1			T539	2		T462	10		T540	20
all_values[61]	3552	1			T462	7		T540	20		T521	13
all_values[62]	3498	1			T539	2		T462	7		T540	19
all_values[63]	3593	1			T539	2		T462	12		T540	21