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LINE 18002
EXPRESSION (addr_hit[199] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | 1 | Covered | T16,T17,T18 |
| 1 | 1 | 0 | Covered | T544,T570,T620 |
| 1 | 1 | 1 | Covered | T16,T17,T18 |
LINE 18005
EXPRESSION (addr_hit[200] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | 1 | Covered | T250,T132,T544 |
| 1 | 1 | 0 | Covered | T563,T564,T558 |
| 1 | 1 | 1 | Covered | T248,T249,T250 |
LINE 18008
EXPRESSION (addr_hit[201] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | 1 | Covered | T132,T381,T562 |
| 1 | 1 | 0 | Covered | T544,T558,T570 |
| 1 | 1 | 1 | Covered | T59,T60,T61 |