Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	152661	1			T77	2		T78	26		T79	4
values[2]	5153	1			T77	2		T83	181		T409	1
values[3]	2476	1			T77	2		T83	155		T508	2
values[4]	1804	1			T77	2		T83	104		T508	2
values[5]	1293	1			T77	2		T83	64		T508	2
values[6]	1011	1			T77	2		T83	32		T508	2
values[7]	863	1			T77	2		T83	41		T508	2
values[8]	740	1			T77	2		T83	46		T508	2
values[9]	637	1			T77	2		T83	52		T508	2
values[10]	506	1			T77	2		T83	28		T508	2
values[11]	387	1			T77	2		T83	12		T508	2
values[12]	394	1			T77	2		T83	6		T508	2
values[13]	380	1			T77	2		T83	1		T508	2
values[14]	308	1			T77	2		T508	2		T456	19
values[15]	314	1			T77	2		T508	2		T456	4
values[16]	353	1			T77	2		T508	2		T456	3
values[17]	362	1			T77	2		T508	2		T460	4
values[18]	377	1			T77	2		T508	2		T460	4
values[19]	346	1			T77	2		T508	2		T460	4
values[20]	325	1			T77	2		T508	2		T460	11
values[21]	289	1			T77	2		T508	2		T460	11
values[22]	314	1			T77	2		T508	2		T460	13
values[23]	267	1			T77	2		T508	2		T460	13
values[24]	259	1			T77	2		T508	2		T460	8
values[25]	212	1			T77	2		T508	2		T460	7
values[26]	227	1			T77	2		T508	2		T460	5
values[27]	228	1			T77	2		T508	2		T460	15
values[28]	233	1			T77	2		T508	2		T460	16
values[29]	258	1			T77	2		T508	2		T460	27
values[30]	227	1			T77	2		T508	2		T460	27
values[31]	228	1			T77	2		T508	3		T460	30
values[32]	237	1			T77	2		T508	2		T460	26
values[33]	210	1			T77	2		T508	2		T460	23
values[34]	247	1			T77	2		T508	2		T460	27
values[35]	243	1			T77	2		T508	2		T460	17
values[36]	224	1			T77	2		T508	2		T460	9
values[37]	203	1			T77	2		T508	2		T460	9
values[38]	148	1			T77	2		T508	2		T460	12
values[39]	124	1			T77	2		T508	2		T460	6
values[40]	144	1			T77	2		T508	2		T460	13
values[41]	125	1			T77	2		T508	2		T460	1
values[42]	114	1			T77	2		T508	2		T768	1
values[43]	106	1			T77	2		T508	2		T768	1
values[44]	103	1			T77	2		T508	2		T768	1
values[45]	104	1			T77	2		T508	2		T768	1
values[46]	108	1			T77	2		T508	2		T768	1
values[47]	117	1			T77	2		T508	2		T768	1
values[48]	102	1			T77	2		T508	2		T768	1
values[49]	93	1			T77	2		T508	2		T768	1
values[50]	96	1			T77	2		T508	2		T768	1
values[51]	83	1			T77	2		T508	2		T768	1
values[52]	78	1			T77	2		T508	2		T768	1
values[53]	56	1			T77	2		T508	2		T768	1
values[54]	90	1			T77	2		T508	2		T768	1
values[55]	72	1			T77	2		T508	2		T768	1
values[56]	64	1			T77	2		T508	2		T768	1
values[57]	55	1			T77	2		T508	2		T768	1
values[58]	68	1			T77	2		T508	2		T768	1
values[59]	60	1			T77	2		T508	2		T768	1
values[60]	62	1			T77	2		T508	2		T768	1
values[61]	54	1			T77	2		T508	2		T768	1
values[62]	56	1			T77	2		T508	2		T768	1
values[63]	54	1			T77	2		T508	2		T768	1
values[64]	52	1			T77	2		T508	2		T768	1
values[65]	51	1			T77	2		T508	2		T768	1
values[66]	52	1			T77	2		T508	2		T768	1
values[67]	66	1			T77	2		T508	2		T768	1
values[68]	56	1			T77	2		T508	2		T768	1
values[69]	69	1			T77	2		T508	2		T768	1
values[70]	72	1			T77	2		T508	2		T768	1
values[71]	62	1			T77	2		T508	2		T768	1
values[72]	57	1			T77	2		T508	2		T768	1
values[73]	70	1			T77	2		T508	2		T768	1
values[74]	56	1			T77	2		T508	2		T768	1
values[75]	68	1			T77	2		T508	3		T768	1
values[76]	60	1			T77	2		T508	2		T768	1
values[77]	52	1			T77	2		T508	2		T768	1
values[78]	65	1			T77	2		T508	2		T768	1
values[79]	64	1			T77	2		T508	2		T768	1
values[80]	61	1			T77	2		T508	2		T768	1
values[81]	58	1			T77	2		T508	2		T768	1
values[82]	73	1			T77	2		T508	2		T768	1
values[83]	79	1			T77	2		T508	2		T768	1
values[84]	91	1			T77	2		T508	2		T768	1
values[85]	83	1			T77	2		T508	2		T768	1
values[86]	89	1			T77	2		T508	3		T768	1
values[87]	80	1			T77	2		T508	2		T768	2
values[88]	101	1			T77	2		T508	2		T768	3
values[89]	102	1			T77	2		T508	2		T768	1
values[90]	82	1			T77	2		T508	2		T768	4
values[91]	95	1			T77	3		T508	2		T768	2
values[92]	90	1			T77	3		T508	2		T768	4
values[93]	96	1			T77	4		T508	3		T768	2
values[94]	79	1			T77	2		T508	2		T768	1
values[95]	84	1			T77	5		T508	3		T768	2
values[96]	86	1			T77	4		T508	5		T768	6
values[97]	92	1			T77	3		T508	3		T768	7
values[98]	77	1			T77	4		T508	3		T768	4
values[99]	77	1			T77	3		T508	3		T768	2
values[100]	77	1			T77	3		T508	2		T768	2
values[101]	76	1			T77	2		T508	3		T768	1
values[102]	89	1			T77	3		T508	6		T768	3
values[103]	80	1			T77	2		T508	5		T768	3
values[104]	89	1			T77	4		T508	3		T768	2
values[105]	76	1			T77	2		T508	2		T768	1
values[106]	85	1			T77	5		T508	2		T768	5
values[107]	96	1			T77	5		T508	2		T768	1
values[108]	99	1			T77	4		T508	3		T768	1
values[109]	104	1			T77	4		T508	4		T768	2
values[110]	117	1			T77	3		T508	3		T768	1
values[111]	87	1			T77	3		T508	3		T768	1
values[112]	89	1			T77	3		T508	5		T768	2
values[113]	96	1			T77	4		T508	3		T768	2
values[114]	93	1			T77	4		T508	2		T768	1
values[115]	96	1			T77	4		T508	4		T768	3
values[116]	102	1			T77	3		T508	2		T768	2
values[117]	89	1			T77	3		T508	2		T768	2
values[118]	100	1			T77	2		T508	7		T768	1
values[119]	105	1			T77	2		T508	3		T768	1
values[120]	109	1			T77	2		T508	4		T768	1
values[121]	119	1			T77	4		T508	2		T768	3
values[122]	115	1			T77	8		T508	3		T768	2
values[123]	122	1			T77	6		T508	3		T768	1
values[124]	175	1			T77	4		T508	5		T768	5
values[125]	363	1			T77	2		T508	8		T768	1
values[126]	873	1			T77	33		T508	24		T768	9
values[127]	2803	1			T77	217		T508	212		T768	71
values[128]	5313	1			T77	452		T508	465		T768	207