Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.18	95.58	94.06	95.46		94.88	97.53	99.58

Total tests in report: 2902

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.56	39.56	44.90	44.90	43.07	43.07	31.59	31.59			57.96	57.96	59.44	59.44	0.39	0.39	/workspace/coverage/default/62.chip_sw_all_escalation_resets.1634210053
49.09	9.54	53.60	8.70	52.50	9.44	35.42	3.83			66.47	8.51	85.66	26.22	0.90	0.52	/workspace/coverage/default/1.chip_jtag_csr_rw.1210072667
56.17	7.08	62.07	8.47	56.80	4.30	41.48	6.07			66.73	0.26	85.66	0.00	24.29	23.38	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.142761164
62.19	6.02	74.70	12.63	65.16	8.36	45.22	3.74			78.10	11.37	85.66	0.00	24.29	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.2992458296
65.64	3.45	80.64	5.94	69.44	4.28	49.16	3.94			80.11	2.00	90.21	4.55	24.29	0.00	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.471062255
69.04	3.40	80.64	0.00	69.53	0.10	49.16	0.00			80.11	0.00	90.21	0.00	44.59	20.30	/workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.710900658
71.89	2.85	83.44	2.80	77.25	7.71	49.60	0.44			85.21	5.10	90.21	0.00	45.62	1.03	/workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.2236866118
74.50	2.61	83.44	0.00	77.25	0.00	65.25	15.66			85.21	0.00	90.21	0.00	45.62	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2628405547
76.90	2.40	86.03	2.59	80.28	3.03	71.14	5.89			87.58	2.37	90.73	0.52	45.62	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2636604056
79.24	2.34	86.03	0.00	80.28	0.00	71.14	0.00			87.58	0.00	90.73	0.00	59.65	14.03	/workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1360448263
81.04	1.80	86.03	0.00	80.28	0.00	71.14	0.00			87.58	0.00	90.73	0.00	70.47	10.82	/workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2979036745
82.58	1.54	86.03	0.00	80.41	0.13	71.14	0.00			87.59	0.02	90.73	0.00	79.57	9.09	/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2069852657
83.85	1.27	86.14	0.11	80.42	0.01	78.49	7.35			87.60	0.01	90.91	0.17	79.57	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.132614749
84.97	1.12	86.14	0.00	80.51	0.09	78.49	0.00			87.63	0.02	90.91	0.00	86.17	6.60	/workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.3104938033
86.06	1.09	86.69	0.55	81.25	0.74	81.52	3.03			88.14	0.51	90.91	0.00	87.87	1.70	/workspace/coverage/default/2.chip_sw_alert_test.2194073495
87.04	0.98	88.08	1.39	83.05	1.80	81.79	0.26			89.85	1.71	91.61	0.70	87.87	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.886032772
87.82	0.78	89.35	1.27	84.14	1.09	82.86	1.07			91.12	1.27	91.61	0.00	87.87	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.216276808
88.58	0.76	89.77	0.43	84.27	0.13	82.87	0.01			91.25	0.14	95.45	3.85	87.87	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.537534659
89.23	0.64	91.23	1.46	85.34	1.07	83.29	0.42			92.16	0.91	95.45	0.00	87.87	0.00	/workspace/coverage/default/2.chip_sw_gpio.4152201949
89.81	0.58	91.24	0.01	85.34	0.01	86.77	3.48			92.16	0.00	95.45	0.00	87.87	0.00	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1962265774
90.39	0.58	91.25	0.01	88.41	3.07	86.77	0.00			92.16	0.00	95.45	0.00	88.29	0.41	/workspace/coverage/cover_reg_top/14.chip_tl_errors.1615370892
90.91	0.52	91.25	0.00	88.55	0.14	86.77	0.00			92.18	0.02	95.45	0.00	91.27	2.98	/workspace/coverage/cover_reg_top/75.xbar_stress_all.2752145033
91.34	0.42	91.83	0.58	89.03	0.48	87.12	0.34			92.79	0.61	95.98	0.52	91.27	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2825966618
91.72	0.38	92.34	0.51	89.51	0.48	87.94	0.82			93.25	0.46	95.98	0.00	91.27	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.1676092458
92.08	0.36	93.16	0.82	89.52	0.01	88.05	0.11			93.25	0.00	95.98	0.00	92.50	1.23	/workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.1879485538
92.39	0.31	93.16	0.00	89.53	0.01	88.05	0.00			93.25	0.00	95.98	0.00	94.36	1.86	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.3271881845
92.64	0.26	93.16	0.00	89.60	0.07	88.05	0.00			93.25	0.00	95.98	0.00	95.83	1.47	/workspace/coverage/cover_reg_top/1.xbar_stress_all.393104498
92.90	0.26	93.34	0.18	89.74	0.14	89.09	1.04			93.42	0.17	95.98	0.00	95.83	0.00	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3758683259
93.14	0.24	93.34	0.00	89.78	0.05	89.09	0.00			93.42	0.00	95.98	0.00	97.23	1.40	/workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.3826848593
93.35	0.21	93.70	0.36	89.97	0.19	89.46	0.37			93.57	0.15	96.15	0.17	97.24	0.01	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.972344709
93.50	0.16	93.85	0.15	90.08	0.11	89.66	0.21			93.69	0.12	96.50	0.35	97.24	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4081155565
93.65	0.15	94.06	0.21	90.40	0.32	90.02	0.36			93.69	0.00	96.50	0.00	97.24	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.913634285
93.77	0.12	94.06	0.01	90.74	0.34	90.03	0.01			94.08	0.39	96.50	0.00	97.24	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1476683756
93.90	0.12	94.21	0.15	90.83	0.10	90.44	0.41			94.16	0.08	96.50	0.00	97.24	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.80652506
94.01	0.12	94.21	0.00	91.53	0.70	90.44	0.00			94.16	0.00	96.50	0.00	97.24	0.00	/workspace/coverage/cover_reg_top/25.chip_tl_errors.3334777852
94.13	0.11	94.21	0.00	91.53	0.00	91.11	0.68			94.16	0.00	96.50	0.00	97.24	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3772452306
94.24	0.11	94.21	0.00	91.53	0.00	91.11	0.00			94.16	0.00	96.50	0.00	97.90	0.66	/workspace/coverage/cover_reg_top/70.xbar_random_large_delays.3679826219
94.34	0.11	94.21	0.00	91.53	0.00	91.76	0.65			94.16	0.00	96.50	0.00	97.90	0.00	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2615813702
94.45	0.11	94.21	0.01	91.55	0.02	92.20	0.44			94.16	0.00	96.68	0.17	97.90	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2116103519
94.54	0.09	94.21	0.00	91.55	0.00	92.74	0.54			94.16	0.00	96.68	0.00	97.90	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3935877725
94.62	0.09	94.21	0.00	91.55	0.00	93.25	0.51			94.16	0.00	96.68	0.00	97.90	0.00	/workspace/coverage/default/2.chip_sw_edn_auto_mode.2650674435
94.70	0.08	94.22	0.01	91.77	0.23	93.27	0.02			94.39	0.23	96.68	0.00	97.90	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1042455692
94.77	0.07	94.33	0.11	91.91	0.13	93.39	0.12			94.44	0.06	96.68	0.00	97.90	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3074523326
94.84	0.07	94.33	0.00	91.93	0.02	93.75	0.36			94.46	0.02	96.68	0.00	97.91	0.01	/workspace/coverage/default/0.chip_sw_flash_init.1488443485
94.90	0.06	94.33	0.00	91.96	0.02	93.75	0.00			94.46	0.00	96.68	0.00	98.23	0.32	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.992258870
94.95	0.05	94.47	0.14	91.98	0.03	93.85	0.10			94.47	0.02	96.68	0.00	98.24	0.01	/workspace/coverage/default/88.chip_sw_all_escalation_resets.3178596149
95.00	0.05	94.47	0.00	91.98	0.00	94.13	0.28			94.47	0.00	96.68	0.00	98.24	0.00	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3458703327
95.04	0.04	94.48	0.01	92.00	0.02	94.15	0.02			94.50	0.02	96.85	0.17	98.25	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.22397447
95.08	0.04	94.48	0.00	92.24	0.24	94.15	0.00			94.50	0.00	96.85	0.00	98.25	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.3449946178
95.12	0.04	94.49	0.01	92.33	0.08	94.28	0.14			94.51	0.01	96.85	0.00	98.25	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3596714528
95.16	0.04	94.52	0.03	92.33	0.01	94.29	0.01			94.52	0.01	97.03	0.17	98.26	0.01	/workspace/coverage/default/64.chip_sw_all_escalation_resets.2457236426
95.19	0.04	94.52	0.01	92.34	0.01	94.29	0.01			94.52	0.01	97.20	0.17	98.27	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.1956939193
95.23	0.04	94.53	0.01	92.35	0.01	94.29	0.00			94.53	0.01	97.38	0.17	98.28	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.3087147173
95.26	0.03	94.53	0.00	92.35	0.00	94.33	0.03			94.53	0.00	97.55	0.17	98.28	0.00	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.2933384438
95.30	0.03	94.53	0.00	92.44	0.08	94.33	0.00			94.58	0.05	97.55	0.00	98.36	0.07	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3348172258
95.33	0.03	94.57	0.03	92.53	0.10	94.33	0.00			94.64	0.06	97.55	0.00	98.36	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3360792480
95.36	0.03	94.57	0.00	92.70	0.17	94.33	0.00			94.64	0.00	97.55	0.00	98.36	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.1854956877
95.38	0.03	94.60	0.04	92.75	0.04	94.39	0.06			94.66	0.02	97.55	0.00	98.36	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1884294601
95.41	0.03	94.60	0.00	92.75	0.00	94.39	0.00			94.66	0.00	97.55	0.00	98.52	0.16	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.134257652
95.44	0.02	94.67	0.07	92.77	0.03	94.39	0.01			94.71	0.05	97.55	0.00	98.52	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.473929318
95.46	0.02	94.67	0.00	92.77	0.00	94.54	0.14			94.71	0.00	97.55	0.00	98.52	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.569520905
95.48	0.02	94.70	0.03	92.82	0.04	94.58	0.04			94.73	0.02	97.55	0.00	98.52	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2643397722
95.51	0.02	94.77	0.07	92.82	0.00	94.63	0.05			94.74	0.01	97.55	0.00	98.52	0.00	/workspace/coverage/default/3.chip_tap_straps_rma.2407203732
95.53	0.02	94.82	0.06	92.87	0.05	94.63	0.00			94.77	0.02	97.55	0.00	98.52	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2354613178
95.55	0.02	94.82	0.00	92.95	0.08	94.63	0.00			94.80	0.03	97.55	0.00	98.53	0.01	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.1916701154
95.57	0.02	94.83	0.01	93.06	0.12	94.64	0.01			94.80	0.00	97.55	0.00	98.53	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_rw.546681241
95.59	0.02	94.83	0.00	93.15	0.09	94.64	0.00			94.82	0.02	97.55	0.00	98.53	0.00	/workspace/coverage/cover_reg_top/47.xbar_stress_all.1416533670
95.60	0.02	94.84	0.01	93.22	0.07	94.66	0.02			94.82	0.00	97.55	0.00	98.53	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.3975120283
95.62	0.02	94.85	0.01	93.27	0.05	94.67	0.02			94.83	0.02	97.55	0.00	98.53	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3877348691
95.63	0.02	94.89	0.03	93.28	0.01	94.71	0.04			94.84	0.01	97.55	0.00	98.53	0.00	/workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.1947010862
95.65	0.01	94.89	0.00	93.28	0.00	94.80	0.09			94.84	0.00	97.55	0.00	98.53	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.502333636
95.66	0.01	94.89	0.00	93.28	0.00	94.88	0.08			94.84	0.00	97.55	0.00	98.53	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1696636437
95.67	0.01	94.89	0.00	93.30	0.02	94.94	0.06			94.84	0.00	97.55	0.00	98.53	0.00	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.590832687
95.69	0.01	94.89	0.00	93.37	0.07	94.94	0.00			94.84	0.00	97.55	0.00	98.53	0.00	/workspace/coverage/cover_reg_top/7.chip_tl_errors.839194722
95.70	0.01	94.89	0.00	93.44	0.07	94.94	0.00			94.84	0.00	97.55	0.00	98.53	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.1964542206
95.71	0.01	94.89	0.00	93.44	0.00	94.94	0.00			94.84	0.00	97.55	0.00	98.60	0.07	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2304654361
95.72	0.01	94.92	0.03	93.46	0.02	94.94	0.00			94.85	0.01	97.55	0.00	98.60	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.330130614
95.73	0.01	94.92	0.00	93.52	0.06	94.94	0.00			94.85	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.677175212
95.74	0.01	94.92	0.00	93.54	0.01	94.98	0.05			94.85	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1905725481
95.75	0.01	94.94	0.01	93.56	0.02	95.00	0.02			94.85	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.914018388
95.76	0.01	94.94	0.00	93.60	0.05	95.00	0.01			94.85	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.4208654570
95.77	0.01	94.94	0.00	93.60	0.00	95.05	0.05			94.85	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2968579806
95.77	0.01	94.94	0.00	93.65	0.04	95.06	0.01			94.85	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3062165636
95.78	0.01	94.94	0.00	93.65	0.00	95.06	0.00			94.85	0.00	97.55	0.00	98.65	0.05	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.2452404843
95.79	0.01	94.94	0.00	93.65	0.00	95.06	0.00			94.85	0.00	97.55	0.00	98.70	0.05	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.3680972823
95.80	0.01	94.96	0.02	93.65	0.01	95.06	0.01			94.86	0.02	97.55	0.00	98.70	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2799468219
95.80	0.01	94.96	0.00	93.65	0.00	95.10	0.04			94.86	0.00	97.55	0.00	98.70	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2320622452
95.81	0.01	94.96	0.00	93.69	0.04	95.10	0.00			94.86	0.00	97.55	0.00	98.70	0.00	/workspace/coverage/cover_reg_top/11.xbar_stress_all.2664548406
95.82	0.01	94.96	0.00	93.69	0.00	95.14	0.04			94.86	0.00	97.55	0.00	98.70	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.954231469
95.82	0.01	94.96	0.01	93.72	0.03	95.14	0.01			94.86	0.00	97.55	0.00	98.70	0.00	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.3743573463
95.83	0.01	94.96	0.00	93.72	0.00	95.14	0.00			94.86	0.00	97.55	0.00	98.73	0.04	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.2474884401
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96.04	0.01	94.99	0.00	93.94	0.00	95.38	0.00			94.86	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/76.chip_sw_all_escalation_resets.105118148
96.04	0.01	94.99	0.00	93.94	0.00	95.38	0.00			94.86	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1024824148
96.05	0.01	94.99	0.00	93.94	0.00	95.38	0.00			94.86	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/86.chip_sw_all_escalation_resets.3355189084
96.05	0.01	94.99	0.00	93.94	0.00	95.38	0.00			94.86	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4189655877
96.05	0.01	94.99	0.00	93.94	0.00	95.38	0.00			94.86	0.00	97.55	0.00	99.57	0.01	/workspace/coverage/default/94.chip_sw_all_escalation_resets.3298967282
96.05	0.01	94.99	0.00	93.94	0.00	95.38	0.00			94.86	0.00	97.55	0.00	99.58	0.01	/workspace/coverage/default/98.chip_sw_all_escalation_resets.544605562
96.05	0.01	94.99	0.00	93.94	0.00	95.39	0.01			94.86	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3900272035
96.05	0.01	94.99	0.00	93.95	0.01	95.39	0.00			94.86	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/1.chip_tl_errors.3561604897
96.06	0.01	94.99	0.00	93.96	0.01	95.39	0.00			94.86	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_gpio.868295376
96.06	0.01	94.99	0.00	93.98	0.01	95.39	0.00			94.86	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3738345092
96.06	0.01	94.99	0.00	93.99	0.01	95.39	0.00			94.86	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3543835641
96.06	0.01	94.99	0.00	94.00	0.01	95.39	0.00			94.86	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3951074203
96.06	0.01	94.99	0.00	94.00	0.00	95.40	0.01			94.86	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.139839804
96.06	0.01	94.99	0.00	94.00	0.00	95.41	0.01			94.86	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1767998427
96.07	0.01	94.99	0.00	94.00	0.00	95.41	0.01			94.87	0.01	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2348077028
96.07	0.01	94.99	0.00	94.00	0.00	95.42	0.01			94.87	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3306325716
96.07	0.01	94.99	0.00	94.00	0.00	95.42	0.00			94.88	0.01	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.2605672251
96.07	0.01	94.99	0.00	94.00	0.01	95.42	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_aon_timer_irq.3921744848
96.07	0.01	94.99	0.01	94.01	0.01	95.42	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2491994450
96.07	0.01	94.99	0.00	94.01	0.00	95.42	0.01			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.3127319119
96.07	0.01	94.99	0.00	94.01	0.00	95.43	0.01			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc.1483577353
96.07	0.01	94.99	0.00	94.01	0.00	95.43	0.01			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.4189875666
96.07	0.01	94.99	0.00	94.01	0.00	95.44	0.01			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3389976966
96.08	0.01	94.99	0.00	94.01	0.01	95.44	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1533147444
96.08	0.01	94.99	0.00	94.01	0.01	95.44	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1101991047
96.08	0.01	94.99	0.00	94.02	0.01	95.44	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.4276608318
96.08	0.01	94.99	0.00	94.02	0.01	95.44	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/20.chip_tl_errors.2778681034
96.08	0.01	94.99	0.00	94.02	0.01	95.44	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.1598106058
96.08	0.01	94.99	0.00	94.03	0.01	95.44	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.2363665917
96.08	0.01	94.99	0.00	94.03	0.01	95.44	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.153860324
96.08	0.01	94.99	0.00	94.04	0.01	95.44	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.4198949436
96.08	0.01	94.99	0.00	94.04	0.01	95.44	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.2145479259
96.08	0.01	94.99	0.00	94.04	0.01	95.44	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.99044864
96.08	0.01	94.99	0.00	94.05	0.01	95.44	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1089163297
96.08	0.01	94.99	0.00	94.05	0.01	95.44	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.932197332
96.08	0.01	94.99	0.00	94.05	0.01	95.44	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3623784233
96.08	0.01	94.99	0.00	94.06	0.01	95.44	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3648847390
96.08	0.01	94.99	0.00	94.06	0.00	95.44	0.01			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_tap_straps_rma.3985236777
96.08	0.01	95.00	0.01	94.06	0.00	95.44	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3458264116
96.08	0.01	95.00	0.01	94.06	0.00	95.44	0.00			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.1854733209
96.08	0.01	95.00	0.00	94.06	0.00	95.44	0.01			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3118694652
96.09	0.01	95.00	0.00	94.06	0.00	95.45	0.01			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1026241942
96.09	0.01	95.00	0.00	94.06	0.00	95.45	0.01			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2533921783
96.09	0.01	95.00	0.00	94.06	0.00	95.45	0.01			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2482134635
96.09	0.01	95.00	0.00	94.06	0.00	95.45	0.01			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2399179147
96.09	0.01	95.00	0.00	94.06	0.00	95.46	0.01			94.88	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.759000605

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3841197678
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2903215676
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3137536808
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3363075783
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.3319386740
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.4280970084
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2219776766
/workspace/coverage/cover_reg_top/0.xbar_error_random.2321349555
/workspace/coverage/cover_reg_top/0.xbar_random.1301862924
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3913176792
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.2792463165
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2637743502
/workspace/coverage/cover_reg_top/0.xbar_same_source.3933077613
/workspace/coverage/cover_reg_top/0.xbar_smoke.427005163
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3231528880
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.586447872
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3478607877
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1853515785
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.749968815
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2692788073
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1831883407
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2605787230
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2661135723
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1424156975
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2689518054
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2116404601
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1585753832
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.4203659102
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.4030619110
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1849093753
/workspace/coverage/cover_reg_top/1.xbar_error_random.3425950739
/workspace/coverage/cover_reg_top/1.xbar_random.3991435528
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.621702502
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1680203745
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.620996248
/workspace/coverage/cover_reg_top/1.xbar_same_source.2681781677
/workspace/coverage/cover_reg_top/1.xbar_smoke.2979862430
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2512354205
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1355766871
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1509423724
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2126655400
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2665978002
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.269919302
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2365614190
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.232982621
/workspace/coverage/cover_reg_top/10.chip_tl_errors.2664599239
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1528751681
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3681665895
/workspace/coverage/cover_reg_top/10.xbar_error_random.711900039
/workspace/coverage/cover_reg_top/10.xbar_random.1168553958
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3914230659
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.4161829956
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1092324990
/workspace/coverage/cover_reg_top/10.xbar_same_source.2705459935
/workspace/coverage/cover_reg_top/10.xbar_smoke.3122288523
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3193606519
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1730812085
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.394884176
/workspace/coverage/cover_reg_top/10.xbar_stress_all.2271561831
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.701583003
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.619155342
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.953746440
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1222029449
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3902792
/workspace/coverage/cover_reg_top/11.chip_tl_errors.1885283737
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.1803639354
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3660122502
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.951742951
/workspace/coverage/cover_reg_top/11.xbar_error_random.1443352441
/workspace/coverage/cover_reg_top/11.xbar_random.1396181130
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3663707150
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3976358661
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2404823806
/workspace/coverage/cover_reg_top/11.xbar_same_source.3958584479
/workspace/coverage/cover_reg_top/11.xbar_smoke.2503120742
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.3193053034
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.857411160
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3691950248
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1856708765
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3756715794
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2709828744
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.649372342
/workspace/coverage/cover_reg_top/12.chip_csr_rw.402861408
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.600890514
/workspace/coverage/cover_reg_top/12.chip_tl_errors.3335408615
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3450663178
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.853128899
/workspace/coverage/cover_reg_top/12.xbar_error_random.1652061872
/workspace/coverage/cover_reg_top/12.xbar_random.2037152224
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2889505961
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3153298989
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2697120551
/workspace/coverage/cover_reg_top/12.xbar_same_source.967099922
/workspace/coverage/cover_reg_top/12.xbar_smoke.879745718
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2966785883
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2430729721
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.767764933
/workspace/coverage/cover_reg_top/12.xbar_stress_all.2075888004
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1991115646
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3846871675
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1801513373
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2005101142
/workspace/coverage/cover_reg_top/13.chip_csr_rw.2609937561
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.122799533
/workspace/coverage/cover_reg_top/13.chip_tl_errors.2058159106
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2967854572
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.386016566
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.4143339641
/workspace/coverage/cover_reg_top/13.xbar_error_random.1209997966
/workspace/coverage/cover_reg_top/13.xbar_random.1062675114
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1055862779
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3917566374
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3875016237
/workspace/coverage/cover_reg_top/13.xbar_same_source.2638602246
/workspace/coverage/cover_reg_top/13.xbar_smoke.658671649
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3961613004
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.4181908302
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.628588845
/workspace/coverage/cover_reg_top/13.xbar_stress_all.3124208978
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2219603469
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3292930307
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3378677924
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.3601562001
/workspace/coverage/cover_reg_top/14.chip_csr_rw.3702208613
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.969649237
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.3710509396
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1648568976
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3919673268
/workspace/coverage/cover_reg_top/14.xbar_error_random.2610463746
/workspace/coverage/cover_reg_top/14.xbar_random.3716940359
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.1962055588
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.3503545977
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/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3048252915
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2832119004
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/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2974775982
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/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3778770845
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1880856281
/workspace/coverage/default/34.chip_sw_all_escalation_resets.1499712207
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1854963726
/workspace/coverage/default/35.chip_sw_all_escalation_resets.3339937247
/workspace/coverage/default/36.chip_sw_all_escalation_resets.3601622992
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2961359681
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1035405284
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/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.4068729021
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3871121037
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/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1809562181
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.373540720
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3765918110
/workspace/coverage/default/4.chip_sw_uart_tx_rx.301489934
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/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.318374093
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1340943836
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3874947934
/workspace/coverage/default/4.chip_tap_straps_dev.682603867
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/workspace/coverage/default/4.chip_tap_straps_rma.3368160707
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/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3937967006
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/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1198672870
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/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3860454683
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2880084062
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2285539737
/workspace/coverage/default/49.chip_sw_all_escalation_resets.4121078559
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.383192749
/workspace/coverage/default/5.chip_sw_all_escalation_resets.224949312
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2841090686
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3727551874
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1472944116
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3373749324
/workspace/coverage/default/50.chip_sw_all_escalation_resets.3317637657
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1609460363
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.339200719
/workspace/coverage/default/52.chip_sw_all_escalation_resets.4048544559
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1311642044
/workspace/coverage/default/55.chip_sw_all_escalation_resets.287483318
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3973411838
/workspace/coverage/default/57.chip_sw_all_escalation_resets.2588213272
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.475217385
/workspace/coverage/default/58.chip_sw_all_escalation_resets.71827994
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1063561640
/workspace/coverage/default/59.chip_sw_all_escalation_resets.2880185742
/workspace/coverage/default/6.chip_sw_all_escalation_resets.3292102569
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.738486091
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.844408990
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1956324256
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3970527655
/workspace/coverage/default/60.chip_sw_all_escalation_resets.4008691261
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.42877510
/workspace/coverage/default/61.chip_sw_all_escalation_resets.5619514
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3761400547
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.829975005
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.110618457
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2263990098
/workspace/coverage/default/65.chip_sw_all_escalation_resets.19691718
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3192357946
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.91204931
/workspace/coverage/default/67.chip_sw_all_escalation_resets.203735764
/workspace/coverage/default/68.chip_sw_all_escalation_resets.1318719051
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3758498754
/workspace/coverage/default/69.chip_sw_all_escalation_resets.1565074607
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.455904448
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2036689605
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1342165591
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3489543619
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1695459905
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1682610476
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1011629330
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.4017401635
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2423587982
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1108300458
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2329849928
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4135358288
/workspace/coverage/default/75.chip_sw_all_escalation_resets.4285594118
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.931266307
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1373366235
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3908133946
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1369963475
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2709201063
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2626507345
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1856376021
/workspace/coverage/default/8.chip_sw_all_escalation_resets.543345964
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2389154534
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2058098192
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2718879305
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.492875058
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1677480647
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.710511454
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2099466797
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1504838663
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1164349333
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.26889001
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3232597370
/workspace/coverage/default/84.chip_sw_all_escalation_resets.652031641
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3700699210
/workspace/coverage/default/85.chip_sw_all_escalation_resets.1754443847
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.399919407
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2437912146
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1658209891
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2541537107
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1786728360
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2271859128
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2928745243
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1078969597
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2218538436
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1250199587
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3585028624
/workspace/coverage/default/91.chip_sw_all_escalation_resets.4022164498
/workspace/coverage/default/92.chip_sw_all_escalation_resets.1144786354
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2287420006
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3003001931
/workspace/coverage/default/96.chip_sw_all_escalation_resets.158695198
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1913237863
/workspace/coverage/default/99.chip_sw_all_escalation_resets.872657198
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1600151890
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.60541837
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.951468340
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.267002418
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1393735202
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3343712073
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2895609645
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1764504416

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Total test records in report: 2902

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3623784233			Jul 12 07:59:59 PM PDT 24	Jul 12 08:08:10 PM PDT 24	3793482032 ps
T5	/workspace/coverage/default/77.chip_sw_all_escalation_resets.3908133946			Jul 12 08:22:54 PM PDT 24	Jul 12 08:33:42 PM PDT 24	4883984920 ps
T6	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3758683259			Jul 12 07:55:57 PM PDT 24	Jul 12 07:57:59 PM PDT 24	3105873937 ps
T15	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1962265774			Jul 12 07:59:22 PM PDT 24	Jul 12 08:18:54 PM PDT 24	5803257584 ps
T88	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4081155565			Jul 12 07:47:01 PM PDT 24	Jul 12 07:52:24 PM PDT 24	2856840240 ps
T89	/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2717765844			Jul 12 07:49:37 PM PDT 24	Jul 12 07:54:47 PM PDT 24	3498397640 ps
T90	/workspace/coverage/default/2.chip_sw_edn_auto_mode.2650674435			Jul 12 08:09:33 PM PDT 24	Jul 12 08:42:48 PM PDT 24	6684108160 ps
T16	/workspace/coverage/default/62.chip_sw_all_escalation_resets.1634210053			Jul 12 08:22:00 PM PDT 24	Jul 12 08:29:48 PM PDT 24	4219088630 ps
T91	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2659295450			Jul 12 07:58:00 PM PDT 24	Jul 12 08:01:17 PM PDT 24	3034283840 ps
T61	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.972344709			Jul 12 08:22:40 PM PDT 24	Jul 12 08:29:31 PM PDT 24	3417778660 ps
T52	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3326755901			Jul 12 08:06:45 PM PDT 24	Jul 12 09:04:16 PM PDT 24	15491764790 ps
T93	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1344207561			Jul 12 07:54:39 PM PDT 24	Jul 12 08:04:53 PM PDT 24	6961413120 ps
T94	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1472944116			Jul 12 08:16:55 PM PDT 24	Jul 12 08:39:12 PM PDT 24	7703015576 ps
T95	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.339200719			Jul 12 08:21:40 PM PDT 24	Jul 12 08:28:31 PM PDT 24	3793523952 ps
T96	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1078159006			Jul 12 07:58:58 PM PDT 24	Jul 12 08:18:19 PM PDT 24	7021915544 ps
T53	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2636604056			Jul 12 07:55:05 PM PDT 24	Jul 12 09:32:35 PM PDT 24	25098563120 ps
T97	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.590832687			Jul 12 07:47:30 PM PDT 24	Jul 12 08:15:30 PM PDT 24	7952071688 ps
T64	/workspace/coverage/default/1.chip_sw_flash_crash_alert.418929671			Jul 12 08:01:03 PM PDT 24	Jul 12 08:14:39 PM PDT 24	4766082588 ps
T98	/workspace/coverage/default/2.chip_sw_uart_smoketest.610777520			Jul 12 08:14:51 PM PDT 24	Jul 12 08:18:42 PM PDT 24	2996460900 ps
T174	/workspace/coverage/default/89.chip_sw_all_escalation_resets.1786728360			Jul 12 08:24:30 PM PDT 24	Jul 12 08:34:09 PM PDT 24	5566009170 ps
T119	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.386985081			Jul 12 07:55:50 PM PDT 24	Jul 12 08:45:17 PM PDT 24	38324442509 ps
T152	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2968579806			Jul 12 08:09:45 PM PDT 24	Jul 12 08:33:10 PM PDT 24	7958847288 ps
T55	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1393912031			Jul 12 08:03:32 PM PDT 24	Jul 12 08:12:16 PM PDT 24	5349594951 ps
T25	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.517230594			Jul 12 08:13:29 PM PDT 24	Jul 12 08:24:26 PM PDT 24	4022555056 ps
T113	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1443460330			Jul 12 07:55:24 PM PDT 24	Jul 12 08:15:07 PM PDT 24	5534095698 ps
T120	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3543835641			Jul 12 07:52:07 PM PDT 24	Jul 12 08:00:28 PM PDT 24	5933921860 ps
T114	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2116103519			Jul 12 07:50:48 PM PDT 24	Jul 12 07:59:45 PM PDT 24	4081204659 ps
T73	/workspace/coverage/default/1.chip_tap_straps_prod.511441115			Jul 12 07:59:44 PM PDT 24	Jul 12 08:09:31 PM PDT 24	6792709423 ps
T285	/workspace/coverage/default/0.chip_sw_hmac_enc.1483577353			Jul 12 07:52:30 PM PDT 24	Jul 12 07:58:06 PM PDT 24	3006495496 ps
T54	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3882199536			Jul 12 07:56:25 PM PDT 24	Jul 12 08:53:43 PM PDT 24	15422444318 ps
T286	/workspace/coverage/default/0.chip_sw_hmac_smoketest.2660055086			Jul 12 07:54:16 PM PDT 24	Jul 12 08:00:36 PM PDT 24	3605960754 ps
T287	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2595131401			Jul 12 07:56:24 PM PDT 24	Jul 12 08:01:11 PM PDT 24	3504801384 ps
T144	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3765918110			Jul 12 08:14:44 PM PDT 24	Jul 12 08:39:48 PM PDT 24	8127117510 ps
T115	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2314326307			Jul 12 07:49:16 PM PDT 24	Jul 12 08:03:20 PM PDT 24	5601794953 ps
T288	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2631481029			Jul 12 08:10:50 PM PDT 24	Jul 12 08:23:32 PM PDT 24	4802592312 ps
T17	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2496332732			Jul 12 07:56:19 PM PDT 24	Jul 12 08:41:18 PM PDT 24	11477132952 ps
T617	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1132876719			Jul 12 07:57:28 PM PDT 24	Jul 12 08:08:10 PM PDT 24	6882871615 ps
T158	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.446523786			Jul 12 08:19:46 PM PDT 24	Jul 12 08:27:29 PM PDT 24	3665779200 ps
T223	/workspace/coverage/default/88.chip_sw_all_escalation_resets.3178596149			Jul 12 08:23:15 PM PDT 24	Jul 12 08:32:36 PM PDT 24	5544971386 ps
T22	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1686556415			Jul 12 07:53:28 PM PDT 24	Jul 12 08:02:54 PM PDT 24	4071294797 ps
T57	/workspace/coverage/default/2.chip_sw_alert_test.2194073495			Jul 12 08:07:47 PM PDT 24	Jul 12 08:12:10 PM PDT 24	2844588088 ps
T56	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2128577557			Jul 12 08:07:11 PM PDT 24	Jul 12 08:09:10 PM PDT 24	2536462128 ps
T255	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.556895388			Jul 12 07:55:26 PM PDT 24	Jul 12 08:11:54 PM PDT 24	5461801616 ps
T378	/workspace/coverage/default/1.chip_sw_kmac_app_rom.2615973266			Jul 12 07:58:00 PM PDT 24	Jul 12 08:01:45 PM PDT 24	2479582050 ps
T107	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1905725481			Jul 12 07:47:48 PM PDT 24	Jul 12 07:58:32 PM PDT 24	18516409484 ps
T18	/workspace/coverage/default/2.chip_jtag_mem_access.3257131600			Jul 12 08:03:25 PM PDT 24	Jul 12 08:31:54 PM PDT 24	14189037086 ps
T612	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.962681821			Jul 12 08:19:53 PM PDT 24	Jul 12 08:27:28 PM PDT 24	3750620200 ps
T44	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1693490668			Jul 12 08:06:43 PM PDT 24	Jul 12 08:15:05 PM PDT 24	5851377640 ps
T68	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2172760496			Jul 12 08:00:14 PM PDT 24	Jul 12 08:11:14 PM PDT 24	4038176616 ps
T333	/workspace/coverage/default/7.chip_sw_all_escalation_resets.945971018			Jul 12 08:17:33 PM PDT 24	Jul 12 08:29:25 PM PDT 24	5611715904 ps
T635	/workspace/coverage/default/1.chip_sw_aes_entropy.1391939566			Jul 12 07:56:55 PM PDT 24	Jul 12 08:00:50 PM PDT 24	2786549960 ps
T26	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1884294601			Jul 12 07:47:48 PM PDT 24	Jul 12 11:38:15 PM PDT 24	77797070157 ps
T401	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.3912531515			Jul 12 07:46:32 PM PDT 24	Jul 12 08:04:44 PM PDT 24	5680195280 ps
T250	/workspace/coverage/default/0.chip_sw_rv_timer_irq.713548041			Jul 12 07:50:44 PM PDT 24	Jul 12 07:56:19 PM PDT 24	3093330428 ps
T403	/workspace/coverage/default/0.chip_sw_kmac_smoketest.1282123289			Jul 12 07:53:12 PM PDT 24	Jul 12 07:58:53 PM PDT 24	3310750720 ps
T224	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2628405547			Jul 12 08:10:23 PM PDT 24	Jul 12 08:33:30 PM PDT 24	7864462060 ps
T832	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.3066237732			Jul 12 07:57:28 PM PDT 24	Jul 12 08:02:18 PM PDT 24	3311314960 ps
T301	/workspace/coverage/default/3.chip_sw_uart_tx_rx.1813884469			Jul 12 08:15:11 PM PDT 24	Jul 12 08:27:14 PM PDT 24	4847211484 ps
T108	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.169348140			Jul 12 08:01:55 PM PDT 24	Jul 12 09:11:52 PM PDT 24	26445869282 ps
T50	/workspace/coverage/default/1.rom_e2e_shutdown_output.3719428008			Jul 12 08:05:36 PM PDT 24	Jul 12 09:01:36 PM PDT 24	26561202335 ps
T251	/workspace/coverage/default/2.chip_plic_all_irqs_0.2992458296			Jul 12 08:12:02 PM PDT 24	Jul 12 08:30:42 PM PDT 24	6204367832 ps
T47	/workspace/coverage/default/0.chip_sw_spi_device_tpm.1882894015			Jul 12 07:46:36 PM PDT 24	Jul 12 07:51:57 PM PDT 24	3455222036 ps
T833	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.376615183			Jul 12 08:10:41 PM PDT 24	Jul 12 08:15:20 PM PDT 24	2732123652 ps
T335	/workspace/coverage/default/27.chip_sw_all_escalation_resets.22397447			Jul 12 08:19:40 PM PDT 24	Jul 12 08:29:09 PM PDT 24	4721843868 ps
T121	/workspace/coverage/default/0.chip_sw_edn_auto_mode.3406603105			Jul 12 07:51:21 PM PDT 24	Jul 12 08:07:28 PM PDT 24	4033871216 ps
T358	/workspace/coverage/default/2.chip_sw_hmac_multistream.2156362800			Jul 12 08:09:44 PM PDT 24	Jul 12 08:42:32 PM PDT 24	8465585432 ps
T188	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.4266818212			Jul 12 07:58:37 PM PDT 24	Jul 12 08:08:06 PM PDT 24	4147242420 ps
T359	/workspace/coverage/default/0.chip_sw_hmac_oneshot.2666242906			Jul 12 07:50:48 PM PDT 24	Jul 12 07:57:02 PM PDT 24	3251825964 ps
T360	/workspace/coverage/default/2.chip_sw_aes_masking_off.1962495474			Jul 12 08:07:08 PM PDT 24	Jul 12 08:13:38 PM PDT 24	3394857069 ps
T334	/workspace/coverage/default/2.chip_sw_all_escalation_resets.3026793306			Jul 12 08:03:08 PM PDT 24	Jul 12 08:12:04 PM PDT 24	5135694920 ps
T361	/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.125064120			Jul 12 08:05:30 PM PDT 24	Jul 12 08:10:48 PM PDT 24	3364014111 ps
T1	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2825966618			Jul 12 07:53:09 PM PDT 24	Jul 12 08:23:24 PM PDT 24	21927746078 ps
T101	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3757286381			Jul 12 07:56:11 PM PDT 24	Jul 12 08:49:55 PM PDT 24	10996543026 ps
T102	/workspace/coverage/default/50.chip_sw_all_escalation_resets.3317637657			Jul 12 08:22:18 PM PDT 24	Jul 12 08:32:17 PM PDT 24	4479320944 ps
T103	/workspace/coverage/default/0.chip_sw_flash_init.1488443485			Jul 12 07:46:46 PM PDT 24	Jul 12 08:25:52 PM PDT 24	24219977950 ps
T69	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2887926993			Jul 12 08:10:42 PM PDT 24	Jul 12 08:18:32 PM PDT 24	4097652136 ps
T104	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.4221551102			Jul 12 07:48:36 PM PDT 24	Jul 12 07:56:59 PM PDT 24	4002889800 ps
T105	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3037365754			Jul 12 07:46:39 PM PDT 24	Jul 12 07:56:38 PM PDT 24	4551073480 ps
T51	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3813855245			Jul 12 07:55:45 PM PDT 24	Jul 12 09:03:11 PM PDT 24	14565482683 ps
T106	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.4144682478			Jul 12 08:03:32 PM PDT 24	Jul 12 08:06:55 PM PDT 24	2305170952 ps
T62	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1456100675			Jul 12 07:47:49 PM PDT 24	Jul 12 07:56:31 PM PDT 24	5849915813 ps
T122	/workspace/coverage/default/0.chip_sw_edn_boot_mode.3127319119			Jul 12 07:48:18 PM PDT 24	Jul 12 07:57:17 PM PDT 24	2998524572 ps
T111	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3017318116			Jul 12 07:56:45 PM PDT 24	Jul 12 08:43:22 PM PDT 24	18781459637 ps
T63	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2043664317			Jul 12 08:17:03 PM PDT 24	Jul 12 08:27:55 PM PDT 24	6855488518 ps
T216	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2491994450			Jul 12 07:47:33 PM PDT 24	Jul 12 07:57:46 PM PDT 24	4008856508 ps
T641	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1453689966			Jul 12 08:12:37 PM PDT 24	Jul 12 08:20:47 PM PDT 24	5592420516 ps
T336	/workspace/coverage/default/73.chip_sw_all_escalation_resets.2423587982			Jul 12 08:21:47 PM PDT 24	Jul 12 08:30:09 PM PDT 24	5249071420 ps
T364	/workspace/coverage/default/63.chip_sw_all_escalation_resets.1338177319			Jul 12 08:22:15 PM PDT 24	Jul 12 08:33:17 PM PDT 24	5094944960 ps
T172	/workspace/coverage/default/1.chip_sw_flash_init.3273414496			Jul 12 07:53:26 PM PDT 24	Jul 12 08:23:51 PM PDT 24	23714904760 ps
T404	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.914611245			Jul 12 07:58:38 PM PDT 24	Jul 12 08:04:13 PM PDT 24	3278538995 ps
T84	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1916749363			Jul 12 08:09:09 PM PDT 24	Jul 12 08:14:10 PM PDT 24	3138831730 ps
T222	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3251682106			Jul 12 07:55:27 PM PDT 24	Jul 12 08:10:31 PM PDT 24	4265053656 ps
T316	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.996106603			Jul 12 08:08:32 PM PDT 24	Jul 12 08:34:29 PM PDT 24	7833956712 ps
T116	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.608274991			Jul 12 07:53:59 PM PDT 24	Jul 12 08:05:49 PM PDT 24	4254596740 ps
T112	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2215763780			Jul 12 08:08:29 PM PDT 24	Jul 12 08:32:56 PM PDT 24	8889153738 ps
T834	/workspace/coverage/default/2.chip_sw_csrng_kat_test.652951875			Jul 12 08:08:31 PM PDT 24	Jul 12 08:11:59 PM PDT 24	2607907276 ps
T193	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.586746774			Jul 12 08:14:34 PM PDT 24	Jul 12 08:27:30 PM PDT 24	5784037047 ps
T835	/workspace/coverage/default/1.chip_sw_uart_smoketest.2106687144			Jul 12 08:05:25 PM PDT 24	Jul 12 08:09:50 PM PDT 24	2867529658 ps
T252	/workspace/coverage/default/1.chip_plic_all_irqs_0.677175212			Jul 12 07:59:09 PM PDT 24	Jul 12 08:19:23 PM PDT 24	6043472244 ps
T644	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3730638685			Jul 12 08:19:17 PM PDT 24	Jul 12 08:28:00 PM PDT 24	4563170300 ps
T362	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2320331476			Jul 12 07:57:28 PM PDT 24	Jul 12 09:41:42 PM PDT 24	23897314200 ps
T836	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1063456739			Jul 12 07:48:24 PM PDT 24	Jul 12 07:53:08 PM PDT 24	3294719092 ps
T58	/workspace/coverage/default/0.chip_sw_alert_test.1096616805			Jul 12 07:58:41 PM PDT 24	Jul 12 08:05:01 PM PDT 24	3428607500 ps
T28	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1220081739			Jul 12 08:04:35 PM PDT 24	Jul 12 08:11:30 PM PDT 24	6299904200 ps
T303	/workspace/coverage/default/34.chip_sw_all_escalation_resets.1499712207			Jul 12 08:20:54 PM PDT 24	Jul 12 08:30:56 PM PDT 24	5598001942 ps
T306	/workspace/coverage/default/0.chip_sw_otbn_randomness.2687636888			Jul 12 07:48:25 PM PDT 24	Jul 12 08:06:27 PM PDT 24	5939115000 ps
T23	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3074523326			Jul 12 07:47:35 PM PDT 24	Jul 12 07:56:58 PM PDT 24	5053164154 ps
T181	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2996560126			Jul 12 08:12:14 PM PDT 24	Jul 12 08:16:33 PM PDT 24	2531626090 ps
T173	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.660324690			Jul 12 08:23:14 PM PDT 24	Jul 12 09:19:58 PM PDT 24	14655206708 ps
T145	/workspace/coverage/default/0.chip_sw_power_idle_load.1854733209			Jul 12 07:50:20 PM PDT 24	Jul 12 08:01:40 PM PDT 24	3899577416 ps
T221	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.183703910			Jul 12 07:49:22 PM PDT 24	Jul 12 08:15:43 PM PDT 24	8963023560 ps
T298	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.140736475			Jul 12 08:01:25 PM PDT 24	Jul 12 08:07:20 PM PDT 24	3305873890 ps
T146	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.125938598			Jul 12 07:48:18 PM PDT 24	Jul 12 08:50:35 PM PDT 24	18813929510 ps
T219	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1026364484			Jul 12 07:57:19 PM PDT 24	Jul 12 08:11:54 PM PDT 24	5507137652 ps
T299	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2434140044			Jul 12 07:47:05 PM PDT 24	Jul 12 07:52:12 PM PDT 24	2840634524 ps
T165	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3935877725			Jul 12 07:48:02 PM PDT 24	Jul 12 07:56:02 PM PDT 24	5298582488 ps
T300	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2994847190			Jul 12 07:56:40 PM PDT 24	Jul 12 08:09:24 PM PDT 24	7805529458 ps
T727	/workspace/coverage/default/57.chip_sw_all_escalation_resets.2588213272			Jul 12 08:21:27 PM PDT 24	Jul 12 08:30:19 PM PDT 24	5133179628 ps
T125	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.758148117			Jul 12 07:58:54 PM PDT 24	Jul 12 08:14:40 PM PDT 24	7421035312 ps
T167	/workspace/coverage/default/1.rom_volatile_raw_unlock.2159248449			Jul 12 08:02:01 PM PDT 24	Jul 12 08:03:48 PM PDT 24	2613176449 ps
T667	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.4075769684			Jul 12 08:20:39 PM PDT 24	Jul 12 08:27:54 PM PDT 24	3651143934 ps
T837	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1540988894			Jul 12 07:58:16 PM PDT 24	Jul 12 08:09:06 PM PDT 24	4056641800 ps
T838	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2032652597			Jul 12 08:03:47 PM PDT 24	Jul 12 08:26:28 PM PDT 24	5393276736 ps
T630	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3519586595			Jul 12 08:06:48 PM PDT 24	Jul 12 08:11:31 PM PDT 24	3441311398 ps
T666	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3908058762			Jul 12 08:00:02 PM PDT 24	Jul 12 08:08:22 PM PDT 24	3914387700 ps
T839	/workspace/coverage/default/1.chip_sw_aes_idle.205843920			Jul 12 07:55:43 PM PDT 24	Jul 12 08:00:18 PM PDT 24	2727550576 ps
T226	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3233924350			Jul 12 07:54:38 PM PDT 24	Jul 12 08:16:10 PM PDT 24	8221715160 ps
T693	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.455904448			Jul 12 08:15:28 PM PDT 24	Jul 12 08:21:49 PM PDT 24	3955915240 ps
T840	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.415548741			Jul 12 07:50:30 PM PDT 24	Jul 12 07:55:11 PM PDT 24	2589126520 ps
T671	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.931266307			Jul 12 08:22:30 PM PDT 24	Jul 12 08:28:17 PM PDT 24	3279779572 ps
T163	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.759000605			Jul 12 07:56:01 PM PDT 24	Jul 12 07:57:50 PM PDT 24	2186094737 ps
T759	/workspace/coverage/default/31.chip_sw_all_escalation_resets.3866310504			Jul 12 08:18:26 PM PDT 24	Jul 12 08:29:00 PM PDT 24	4781685352 ps
T841	/workspace/coverage/default/1.chip_sw_hmac_smoketest.354901402			Jul 12 08:02:10 PM PDT 24	Jul 12 08:07:30 PM PDT 24	2875684140 ps
T19	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1042455692			Jul 12 08:02:39 PM PDT 24	Jul 12 08:08:17 PM PDT 24	3185043851 ps
T406	/workspace/coverage/default/0.chip_sw_kmac_entropy.3670407842			Jul 12 07:47:37 PM PDT 24	Jul 12 07:52:14 PM PDT 24	3675212088 ps
T124	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3426362565			Jul 12 08:07:18 PM PDT 24	Jul 12 08:17:34 PM PDT 24	6285055395 ps
T74	/workspace/coverage/default/1.chip_tap_straps_dev.3285094605			Jul 12 07:59:39 PM PDT 24	Jul 12 08:34:53 PM PDT 24	17448071269 ps
T27	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3874947934			Jul 12 08:14:45 PM PDT 24	Jul 12 08:26:26 PM PDT 24	4505992696 ps
T658	/workspace/coverage/default/21.chip_sw_all_escalation_resets.3336171285			Jul 12 08:17:22 PM PDT 24	Jul 12 08:27:36 PM PDT 24	4369584080 ps
T842	/workspace/coverage/default/2.chip_sw_edn_sw_mode.4285585211			Jul 12 08:09:06 PM PDT 24	Jul 12 08:31:03 PM PDT 24	6690142824 ps
T843	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.265922209			Jul 12 07:58:02 PM PDT 24	Jul 12 08:21:07 PM PDT 24	6074646973 ps
T844	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2631156557			Jul 12 07:52:29 PM PDT 24	Jul 12 08:00:43 PM PDT 24	5579554400 ps
T663	/workspace/coverage/default/35.chip_sw_all_escalation_resets.3339937247			Jul 12 08:18:56 PM PDT 24	Jul 12 08:29:27 PM PDT 24	4744671938 ps
T344	/workspace/coverage/default/2.chip_sw_flash_crash_alert.1518042759			Jul 12 08:11:54 PM PDT 24	Jul 12 08:26:06 PM PDT 24	5617851536 ps
T845	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.2914437455			Jul 12 07:58:04 PM PDT 24	Jul 12 08:01:46 PM PDT 24	3522383160 ps
T168	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.132614749			Jul 12 08:05:40 PM PDT 24	Jul 12 09:31:07 PM PDT 24	49232220300 ps
T846	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.2675284403			Jul 12 07:53:58 PM PDT 24	Jul 12 08:11:06 PM PDT 24	6029390050 ps
T342	/workspace/coverage/default/91.chip_sw_all_escalation_resets.4022164498			Jul 12 08:24:14 PM PDT 24	Jul 12 08:31:25 PM PDT 24	4512407756 ps
T175	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1696636437			Jul 12 07:58:38 PM PDT 24	Jul 12 09:26:52 PM PDT 24	50716286177 ps
T328	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1341875066			Jul 12 08:11:22 PM PDT 24	Jul 12 08:23:41 PM PDT 24	5129268333 ps
T45	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2959174189			Jul 12 07:56:55 PM PDT 24	Jul 12 08:06:30 PM PDT 24	5860029014 ps
T266	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3628274687			Jul 12 08:09:37 PM PDT 24	Jul 12 08:18:08 PM PDT 24	9165283063 ps
T279	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1245365262			Jul 12 08:08:25 PM PDT 24	Jul 12 08:17:30 PM PDT 24	3736201352 ps
T847	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3129229135			Jul 12 07:49:11 PM PDT 24	Jul 12 07:52:24 PM PDT 24	2669463389 ps
T742	/workspace/coverage/default/81.chip_sw_all_escalation_resets.2099466797			Jul 12 08:24:52 PM PDT 24	Jul 12 08:34:50 PM PDT 24	6050442408 ps
T76	/workspace/coverage/default/0.chip_sw_usbdev_pullup.3713876567			Jul 12 07:49:18 PM PDT 24	Jul 12 07:53:49 PM PDT 24	3017362636 ps
T176	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3921682379			Jul 12 07:47:56 PM PDT 24	Jul 12 08:03:36 PM PDT 24	9392380220 ps
T70	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.847924968			Jul 12 08:17:13 PM PDT 24	Jul 12 08:27:01 PM PDT 24	4071985116 ps
T712	/workspace/coverage/default/90.chip_sw_all_escalation_resets.3585028624			Jul 12 08:22:40 PM PDT 24	Jul 12 08:30:44 PM PDT 24	5095592940 ps
T85	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2479286310			Jul 12 08:09:06 PM PDT 24	Jul 12 11:14:04 PM PDT 24	254406240740 ps
T214	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1881331367			Jul 12 08:09:20 PM PDT 24	Jul 12 08:36:26 PM PDT 24	7943104982 ps
T350	/workspace/coverage/default/0.chip_sival_flash_info_access.2073124740			Jul 12 07:47:02 PM PDT 24	Jul 12 07:51:42 PM PDT 24	3340648640 ps
T179	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.418301029			Jul 12 07:53:54 PM PDT 24	Jul 12 08:27:02 PM PDT 24	34573105734 ps
T848	/workspace/coverage/default/1.chip_sw_edn_auto_mode.3456518126			Jul 12 07:58:55 PM PDT 24	Jul 12 08:31:10 PM PDT 24	6157995296 ps
T265	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3746997444			Jul 12 07:57:57 PM PDT 24	Jul 12 08:33:32 PM PDT 24	11686790140 ps
T153	/workspace/coverage/default/2.chip_plic_all_irqs_10.1676092458			Jul 12 08:13:47 PM PDT 24	Jul 12 08:22:35 PM PDT 24	3607905842 ps
T75	/workspace/coverage/default/0.chip_tap_straps_rma.2174447466			Jul 12 07:51:05 PM PDT 24	Jul 12 07:57:57 PM PDT 24	4891080840 ps
T325	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3874054739			Jul 12 08:01:11 PM PDT 24	Jul 12 08:13:08 PM PDT 24	4785923096 ps
T849	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2545171059			Jul 12 07:50:32 PM PDT 24	Jul 12 08:01:54 PM PDT 24	4744447518 ps
T850	/workspace/coverage/default/2.chip_sw_aes_entropy.209507060			Jul 12 08:09:33 PM PDT 24	Jul 12 08:14:13 PM PDT 24	3320973608 ps
T366	/workspace/coverage/default/2.chip_sw_edn_boot_mode.2403474943			Jul 12 08:08:25 PM PDT 24	Jul 12 08:19:35 PM PDT 24	3382003960 ps
T182	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2951342678			Jul 12 07:50:57 PM PDT 24	Jul 12 07:54:56 PM PDT 24	2915737346 ps
T154	/workspace/coverage/default/1.chip_plic_all_irqs_10.2071444362			Jul 12 07:59:38 PM PDT 24	Jul 12 08:08:18 PM PDT 24	4076840800 ps
T370	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2695390262			Jul 12 07:51:16 PM PDT 24	Jul 12 07:59:45 PM PDT 24	4904638200 ps
T851	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1093932864			Jul 12 08:18:53 PM PDT 24	Jul 12 08:28:31 PM PDT 24	6295285486 ps
T35	/workspace/coverage/default/2.chip_sw_gpio.4152201949			Jul 12 08:05:34 PM PDT 24	Jul 12 08:14:32 PM PDT 24	4481141300 ps
T159	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2415616243			Jul 12 07:48:29 PM PDT 24	Jul 12 11:06:26 PM PDT 24	255004190344 ps
T736	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3973411838			Jul 12 08:22:29 PM PDT 24	Jul 12 08:30:15 PM PDT 24	3681010772 ps
T852	/workspace/coverage/default/2.rom_e2e_static_critical.1853753221			Jul 12 08:18:41 PM PDT 24	Jul 12 09:25:21 PM PDT 24	17604074032 ps
T217	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3648253560			Jul 12 07:57:21 PM PDT 24	Jul 12 08:09:21 PM PDT 24	4623473064 ps
T155	/workspace/coverage/default/0.chip_plic_all_irqs_10.171406116			Jul 12 07:50:56 PM PDT 24	Jul 12 07:59:20 PM PDT 24	4492733000 ps
T117	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.722247694			Jul 12 07:52:30 PM PDT 24	Jul 12 08:04:17 PM PDT 24	4410850863 ps
T853	/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.738486091			Jul 12 08:16:11 PM PDT 24	Jul 12 09:16:44 PM PDT 24	15996430232 ps
T854	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4168690282			Jul 12 08:16:43 PM PDT 24	Jul 12 08:25:30 PM PDT 24	3705336708 ps
T705	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.26889001			Jul 12 08:22:49 PM PDT 24	Jul 12 08:28:40 PM PDT 24	3243757280 ps
T670	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.710511454			Jul 12 08:23:20 PM PDT 24	Jul 12 08:28:56 PM PDT 24	3052872184 ps
T855	/workspace/coverage/default/2.chip_sw_example_flash.4206079463			Jul 12 08:03:30 PM PDT 24	Jul 12 08:06:47 PM PDT 24	2152768384 ps
T220	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3066631098			Jul 12 08:04:28 PM PDT 24	Jul 12 08:22:37 PM PDT 24	5704163944 ps
T189	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3458703327			Jul 12 08:08:40 PM PDT 24	Jul 12 08:19:48 PM PDT 24	6935768679 ps
T345	/workspace/coverage/default/11.chip_sw_all_escalation_resets.2413990576			Jul 12 08:18:09 PM PDT 24	Jul 12 08:27:51 PM PDT 24	4612744152 ps
T665	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1846862188			Jul 12 08:03:28 PM PDT 24	Jul 12 08:13:32 PM PDT 24	4463674528 ps
T856	/workspace/coverage/default/2.chip_sw_aes_idle.1118242717			Jul 12 08:07:57 PM PDT 24	Jul 12 08:12:59 PM PDT 24	2741091300 ps
T418	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.87761770			Jul 12 07:47:26 PM PDT 24	Jul 12 08:02:44 PM PDT 24	8306935644 ps
T707	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4135358288			Jul 12 08:22:28 PM PDT 24	Jul 12 08:30:29 PM PDT 24	3885286680 ps
T7	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3333703853			Jul 12 08:00:48 PM PDT 24	Jul 12 08:07:40 PM PDT 24	3526891776 ps
T280	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2582800401			Jul 12 08:03:34 PM PDT 24	Jul 12 08:18:04 PM PDT 24	5020155116 ps
T343	/workspace/coverage/default/6.chip_sw_all_escalation_resets.3292102569			Jul 12 08:17:25 PM PDT 24	Jul 12 08:29:32 PM PDT 24	5946273016 ps
T245	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2427517866			Jul 12 08:19:19 PM PDT 24	Jul 12 08:26:39 PM PDT 24	3525323840 ps
T289	/workspace/coverage/default/52.chip_sw_all_escalation_resets.4048544559			Jul 12 08:20:17 PM PDT 24	Jul 12 08:31:38 PM PDT 24	5839237696 ps
T290	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.2898129342			Jul 12 07:50:33 PM PDT 24	Jul 12 07:54:10 PM PDT 24	2216295777 ps
T291	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1540065816			Jul 12 08:06:01 PM PDT 24	Jul 12 08:26:11 PM PDT 24	6663685266 ps
T36	/workspace/coverage/default/1.chip_sw_gpio.2567363897			Jul 12 07:53:36 PM PDT 24	Jul 12 08:01:33 PM PDT 24	4421624181 ps
T292	/workspace/coverage/default/2.chip_tap_straps_prod.1557605270			Jul 12 08:11:06 PM PDT 24	Jul 12 08:13:47 PM PDT 24	2363582014 ps
T60	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3877348691			Jul 12 07:46:31 PM PDT 24	Jul 12 07:56:54 PM PDT 24	3660556194 ps
T293	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2465726520			Jul 12 07:51:46 PM PDT 24	Jul 12 07:55:03 PM PDT 24	2875044720 ps
T294	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2312215328			Jul 12 07:55:46 PM PDT 24	Jul 12 08:58:52 PM PDT 24	15846362354 ps
T80	/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.4139882633			Jul 12 07:52:54 PM PDT 24	Jul 12 08:35:25 PM PDT 24	27570749146 ps
T209	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1681063831			Jul 12 08:08:41 PM PDT 24	Jul 12 08:13:16 PM PDT 24	2746983278 ps
T857	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3064952306			Jul 12 08:17:07 PM PDT 24	Jul 12 09:06:04 PM PDT 24	14587437024 ps
T664	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2524322360			Jul 12 08:21:11 PM PDT 24	Jul 12 08:27:34 PM PDT 24	3876416180 ps
T673	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2365929419			Jul 12 08:18:30 PM PDT 24	Jul 12 08:24:12 PM PDT 24	4337272182 ps
T331	/workspace/coverage/default/1.chip_sw_pattgen_ios.2895059282			Jul 12 07:52:56 PM PDT 24	Jul 12 07:56:38 PM PDT 24	2740425040 ps
T858	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2162324010			Jul 12 07:58:21 PM PDT 24	Jul 12 08:03:14 PM PDT 24	3055189060 ps
T859	/workspace/coverage/default/0.chip_sw_edn_kat.4001252321			Jul 12 07:48:47 PM PDT 24	Jul 12 07:58:49 PM PDT 24	3583807402 ps
T218	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3777399618			Jul 12 08:19:09 PM PDT 24	Jul 12 08:39:18 PM PDT 24	7586987088 ps
T2	/workspace/coverage/default/1.chip_jtag_csr_rw.1210072667			Jul 12 07:52:58 PM PDT 24	Jul 12 08:19:50 PM PDT 24	12833582307 ps
T281	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3727551874			Jul 12 08:15:11 PM PDT 24	Jul 12 08:25:50 PM PDT 24	5905733800 ps
T233	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2837299457			Jul 12 08:00:25 PM PDT 24	Jul 12 08:34:24 PM PDT 24	23913904667 ps
T225	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.193215615			Jul 12 08:02:49 PM PDT 24	Jul 12 09:18:04 PM PDT 24	16298881300 ps
T267	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.434349098			Jul 12 08:00:40 PM PDT 24	Jul 12 09:10:11 PM PDT 24	14886100940 ps
T3	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3048512934			Jul 12 07:55:05 PM PDT 24	Jul 12 07:59:59 PM PDT 24	4600255250 ps
T386	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3381369016			Jul 12 08:17:19 PM PDT 24	Jul 12 09:12:42 PM PDT 24	14544879810 ps
T9	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.330130614			Jul 12 07:48:16 PM PDT 24	Jul 12 07:56:57 PM PDT 24	5423605000 ps
T340	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1282911299			Jul 12 07:51:04 PM PDT 24	Jul 12 08:05:13 PM PDT 24	4932812246 ps
T387	/workspace/coverage/default/2.chip_sw_rv_timer_irq.3359785800			Jul 12 08:06:41 PM PDT 24	Jul 12 08:11:03 PM PDT 24	2899696548 ps
T860	/workspace/coverage/default/1.chip_sw_otbn_randomness.3765015212			Jul 12 07:57:31 PM PDT 24	Jul 12 08:12:44 PM PDT 24	5591526000 ps
T227	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2533921783			Jul 12 07:50:18 PM PDT 24	Jul 12 08:40:36 PM PDT 24	11400775720 ps
T861	/workspace/coverage/default/2.rom_e2e_asm_init_prod.1270346324			Jul 12 08:22:52 PM PDT 24	Jul 12 09:25:56 PM PDT 24	15763467778 ps
T312	/workspace/coverage/default/0.chip_plic_all_irqs_0.1854956877			Jul 12 07:49:33 PM PDT 24	Jul 12 08:12:57 PM PDT 24	6676341688 ps
T160	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.4068729021			Jul 12 08:15:14 PM PDT 24	Jul 12 08:21:44 PM PDT 24	3456874400 ps
T162	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.4285732240			Jul 12 08:07:20 PM PDT 24	Jul 12 08:09:37 PM PDT 24	2448594339 ps
T309	/workspace/coverage/default/2.chip_plic_all_irqs_20.216276808			Jul 12 08:13:33 PM PDT 24	Jul 12 08:31:54 PM PDT 24	5289179016 ps
T407	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3909186287			Jul 12 08:08:45 PM PDT 24	Jul 12 08:26:49 PM PDT 24	6925233526 ps
T20	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.886032772			Jul 12 07:53:13 PM PDT 24	Jul 12 07:58:46 PM PDT 24	3282825040 ps
T329	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3129289795			Jul 12 07:54:18 PM PDT 24	Jul 12 08:05:45 PM PDT 24	4089284420 ps
T180	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.145189668			Jul 12 07:49:40 PM PDT 24	Jul 12 08:03:02 PM PDT 24	7502955118 ps
T862	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.113822512			Jul 12 07:51:56 PM PDT 24	Jul 12 07:55:40 PM PDT 24	2669610104 ps
T863	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2585336558			Jul 12 07:49:17 PM PDT 24	Jul 12 07:54:18 PM PDT 24	3329325932 ps
T118	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2565108109			Jul 12 08:09:58 PM PDT 24	Jul 12 08:22:05 PM PDT 24	4221346594 ps
T282	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2310183647			Jul 12 08:01:42 PM PDT 24	Jul 12 08:14:58 PM PDT 24	5013332011 ps
T864	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.4109098113			Jul 12 07:54:21 PM PDT 24	Jul 12 07:59:31 PM PDT 24	2968733800 ps
T10	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2354613178			Jul 12 07:58:06 PM PDT 24	Jul 12 08:02:41 PM PDT 24	3593232552 ps
T169	/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.2429683978			Jul 12 08:00:07 PM PDT 24	Jul 12 08:07:46 PM PDT 24	4349423912 ps
T865	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.695295524			Jul 12 08:15:30 PM PDT 24	Jul 12 08:19:35 PM PDT 24	3108020736 ps
T723	/workspace/coverage/default/12.chip_sw_all_escalation_resets.1054463912			Jul 12 08:16:43 PM PDT 24	Jul 12 08:25:49 PM PDT 24	6060970958 ps
T668	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2624492094			Jul 12 08:22:30 PM PDT 24	Jul 12 08:29:51 PM PDT 24	4104816092 ps
T611	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2271603504			Jul 12 08:18:37 PM PDT 24	Jul 12 08:25:10 PM PDT 24	3702169260 ps
T751	/workspace/coverage/default/56.chip_sw_all_escalation_resets.966463189			Jul 12 08:21:00 PM PDT 24	Jul 12 08:28:48 PM PDT 24	5223440170 ps
T268	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3194989828			Jul 12 08:00:05 PM PDT 24	Jul 12 09:43:17 PM PDT 24	22690778862 ps
T253	/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3808265361			Jul 12 07:51:40 PM PDT 24	Jul 12 08:28:56 PM PDT 24	24577988994 ps