Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	134433	1			T78	13		T79	3		T82	163
values[2]	9882	1			T83	112		T502	1		T503	6
values[3]	3809	1			T83	55		T502	1		T503	5
values[4]	2275	1			T83	27		T502	1		T503	17
values[5]	1411	1			T83	6		T502	1		T503	6
values[6]	1041	1			T83	5		T502	1		T503	8
values[7]	766	1			T502	1		T503	5		T508	1
values[8]	554	1			T502	1		T503	17		T508	1
values[9]	426	1			T502	1		T503	3		T508	1
values[10]	434	1			T502	1		T503	3		T508	1
values[11]	370	1			T502	1		T503	4		T508	1
values[12]	345	1			T502	1		T503	23		T508	1
values[13]	344	1			T502	1		T503	9		T508	1
values[14]	343	1			T502	1		T503	5		T508	1
values[15]	306	1			T502	1		T503	7		T508	1
values[16]	327	1			T502	1		T503	8		T508	1
values[17]	316	1			T502	1		T503	11		T508	2
values[18]	320	1			T502	1		T503	26		T508	1
values[19]	302	1			T502	1		T503	2		T508	1
values[20]	300	1			T502	1		T503	7		T508	1
values[21]	293	1			T502	1		T503	5		T508	1
values[22]	299	1			T502	1		T503	5		T508	1
values[23]	289	1			T502	1		T503	8		T508	1
values[24]	352	1			T502	1		T503	10		T508	1
values[25]	337	1			T502	1		T503	12		T508	1
values[26]	314	1			T502	1		T503	8		T508	1
values[27]	278	1			T502	1		T503	3		T508	1
values[28]	268	1			T502	1		T503	4		T508	1
values[29]	309	1			T502	1		T503	5		T508	1
values[30]	304	1			T502	1		T503	9		T508	1
values[31]	357	1			T502	1		T503	7		T508	1
values[32]	288	1			T502	1		T503	6		T508	1
values[33]	303	1			T502	1		T503	3		T508	1
values[34]	331	1			T502	1		T503	13		T508	1
values[35]	279	1			T502	1		T503	4		T508	1
values[36]	295	1			T502	1		T503	3		T508	1
values[37]	311	1			T502	1		T503	19		T508	1
values[38]	274	1			T502	1		T503	12		T508	1
values[39]	286	1			T502	1		T503	13		T508	1
values[40]	310	1			T502	1		T503	6		T508	1
values[41]	274	1			T502	1		T503	5		T508	1
values[42]	348	1			T502	1		T503	7		T508	1
values[43]	355	1			T502	1		T503	7		T508	1
values[44]	322	1			T502	1		T503	3		T508	1
values[45]	317	1			T502	1		T503	2		T508	1
values[46]	331	1			T502	1		T503	10		T508	1
values[47]	257	1			T502	1		T503	4		T508	1
values[48]	260	1			T502	1		T503	3		T508	1
values[49]	240	1			T502	1		T503	8		T508	1
values[50]	268	1			T502	1		T503	13		T508	1
values[51]	237	1			T502	1		T503	5		T508	1
values[52]	273	1			T502	1		T503	6		T508	1
values[53]	263	1			T502	1		T503	6		T508	1
values[54]	272	1			T502	1		T503	5		T508	1
values[55]	228	1			T502	1		T503	19		T508	1
values[56]	200	1			T502	1		T503	5		T508	1
values[57]	231	1			T502	1		T503	9		T508	1
values[58]	239	1			T502	1		T503	2		T508	1
values[59]	220	1			T502	2		T503	8		T508	1
values[60]	228	1			T502	1		T503	11		T508	1
values[61]	202	1			T502	1		T503	6		T508	1
values[62]	207	1			T502	2		T503	7		T508	1
values[63]	189	1			T502	1		T503	4		T508	1
values[64]	161	1			T502	1		T503	6		T508	1
values[65]	189	1			T502	1		T503	3		T508	1
values[66]	213	1			T502	1		T508	1		T763	1
values[67]	197	1			T502	1		T508	1		T763	1
values[68]	142	1			T502	1		T508	1		T763	1
values[69]	155	1			T502	1		T508	1		T763	1
values[70]	123	1			T502	1		T508	1		T763	1
values[71]	122	1			T502	1		T508	1		T763	1
values[72]	103	1			T502	1		T508	1		T763	1
values[73]	76	1			T502	1		T508	1		T763	1
values[74]	112	1			T502	1		T508	1		T763	1
values[75]	85	1			T502	1		T508	1		T763	1
values[76]	85	1			T502	1		T508	1		T763	2
values[77]	76	1			T502	1		T508	1		T763	1
values[78]	86	1			T502	1		T508	1		T763	1
values[79]	95	1			T502	1		T508	1		T763	1
values[80]	79	1			T502	1		T508	1		T763	1
values[81]	87	1			T502	1		T508	1		T763	1
values[82]	75	1			T502	1		T508	1		T763	1
values[83]	61	1			T502	1		T508	1		T763	2
values[84]	71	1			T502	3		T508	1		T763	1
values[85]	85	1			T502	3		T508	1		T763	1
values[86]	81	1			T502	5		T508	1		T763	1
values[87]	85	1			T502	8		T508	1		T763	1
values[88]	68	1			T502	1		T508	2		T763	1
values[89]	62	1			T502	6		T508	1		T763	1
values[90]	78	1			T502	4		T508	1		T763	1
values[91]	57	1			T502	3		T508	1		T763	1
values[92]	75	1			T502	10		T508	1		T763	1
values[93]	92	1			T502	5		T508	1		T763	1
values[94]	74	1			T502	1		T508	1		T763	1
values[95]	79	1			T502	1		T508	1		T763	1
values[96]	76	1			T502	2		T508	1		T763	1
values[97]	71	1			T502	1		T508	1		T763	1
values[98]	67	1			T502	2		T508	1		T763	1
values[99]	58	1			T502	2		T508	1		T763	1
values[100]	81	1			T502	2		T508	1		T763	1
values[101]	52	1			T502	1		T508	1		T763	1
values[102]	63	1			T502	2		T508	1		T763	1
values[103]	57	1			T502	3		T508	2		T763	1
values[104]	79	1			T502	5		T508	1		T763	1
values[105]	68	1			T502	6		T508	1		T763	1
values[106]	66	1			T502	3		T508	1		T763	1
values[107]	54	1			T502	1		T508	1		T763	1
values[108]	67	1			T502	1		T508	1		T763	1
values[109]	66	1			T502	2		T508	1		T763	1
values[110]	61	1			T502	2		T508	1		T763	1
values[111]	62	1			T502	2		T508	2		T763	1
values[112]	75	1			T502	4		T508	3		T763	1
values[113]	68	1			T502	1		T508	1		T763	1
values[114]	51	1			T502	1		T508	2		T763	1
values[115]	73	1			T502	3		T508	1		T763	1
values[116]	59	1			T502	1		T508	5		T763	1
values[117]	64	1			T502	3		T508	2		T763	2
values[118]	76	1			T502	1		T508	1		T763	3
values[119]	65	1			T502	2		T508	1		T763	3
values[120]	64	1			T502	2		T508	2		T763	5
values[121]	72	1			T502	2		T508	3		T763	1
values[122]	60	1			T502	1		T508	3		T763	8
values[123]	58	1			T502	2		T508	1		T763	1
values[124]	72	1			T502	3		T508	3		T763	1
values[125]	66	1			T502	4		T508	1		T763	1
values[126]	124	1			T502	2		T508	1		T763	2
values[127]	800	1			T502	33		T508	32		T763	28
values[128]	6477	1			T502	265		T508	277		T763	265