Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	461	1			T393	2		T389	1		T390	1
all_values[1]	437	1			T393	3		T390	5		T397	1
all_values[2]	461	1			T83	1		T393	1		T389	1
all_values[3]	413	1			T83	1		T393	1		T389	2
all_values[4]	416	1			T393	1		T389	1		T390	3
all_values[5]	445	1			T123	1		T83	1		T782	2
all_values[6]	428	1			T77	1		T123	1		T390	1
all_values[7]	442	1			T82	2		T83	1		T393	2
all_values[8]	486	1			T83	1		T393	2		T389	1
all_values[9]	433	1			T393	1		T389	2		T390	3
all_values[10]	421	1			T389	2		T390	2		T397	1
all_values[11]	441	1			T77	2		T83	2		T393	1
all_values[12]	436	1			T83	2		T389	1		T782	1
all_values[13]	423	1			T82	1		T389	1		T390	1
all_values[14]	461	1			T393	4		T782	1		T397	1
all_values[15]	493	1			T393	2		T626	1		T647	2
all_values[16]	435	1			T502	1		T390	3		T397	1
all_values[17]	439	1			T83	1		T393	2		T390	2
all_values[18]	415	1			T83	1		T393	1		T782	1
all_values[19]	401	1			T393	2		T782	1		T390	1
all_values[20]	476	1			T77	1		T83	2		T393	2
all_values[21]	397	1			T393	3		T389	1		T397	2
all_values[22]	433	1			T83	1		T390	1		T647	1
all_values[23]	440	1			T393	2		T389	1		T390	2
all_values[24]	465	1			T83	1		T393	1		T389	2
all_values[25]	453	1			T83	1		T503	1		T393	2
all_values[26]	405	1			T82	1		T83	2		T389	1
all_values[27]	475	1			T389	1		T390	3		T397	3
all_values[28]	480	1			T393	2		T389	1		T390	2
all_values[29]	471	1			T393	1		T389	1		T390	3
all_values[30]	490	1			T389	2		T397	2		T647	1
all_values[31]	442	1			T389	5		T782	1		T397	2
all_values[32]	470	1			T77	1		T393	1		T389	2
all_values[33]	437	1			T83	1		T390	1		T397	1
all_values[34]	457	1			T83	1		T393	3		T389	3
all_values[35]	422	1			T83	1		T503	1		T393	2
all_values[36]	457	1			T83	1		T393	1		T389	1
all_values[37]	427	1			T503	1		T393	4		T389	1
all_values[38]	493	1			T393	2		T389	1		T390	1
all_values[39]	507	1			T123	1		T83	1		T393	1
all_values[40]	473	1			T782	1		T390	3		T397	4
all_values[41]	444	1			T82	1		T393	2		T389	1
all_values[42]	468	1			T83	1		T503	1		T393	3
all_values[43]	445	1			T123	1		T83	1		T393	6
all_values[44]	458	1			T123	1		T390	2		T397	1
all_values[45]	447	1			T83	1		T502	1		T503	1
all_values[46]	424	1			T83	1		T389	2		T397	2
all_values[47]	430	1			T389	2		T390	2		T397	4
all_values[48]	463	1			T83	1		T389	2		T390	1
all_values[49]	446	1			T82	1		T393	4		T389	4