Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3331	1			T82	3		T83	1		T393	3
all_values[1]	3399	1			T82	1		T83	8		T393	10
all_values[2]	3417	1			T82	2		T83	3		T393	7
all_values[3]	3369	1			T82	5		T83	9		T393	5
all_values[4]	3441	1			T82	5		T83	5		T393	7
all_values[5]	3441	1			T82	5		T83	7		T393	5
all_values[6]	3306	1			T82	4		T83	7		T393	6
all_values[7]	3502	1			T83	3		T393	6		T389	2
all_values[8]	3367	1			T82	2		T83	6		T393	7
all_values[9]	3358	1			T82	3		T83	9		T393	9
all_values[10]	3323	1			T82	2		T83	4		T393	9
all_values[11]	3418	1			T82	13		T83	2		T393	9
all_values[12]	3346	1			T82	3		T83	3		T393	9
all_values[13]	3404	1			T83	6		T393	7		T389	1
all_values[14]	3341	1			T82	3		T83	8		T393	6
all_values[15]	3361	1			T82	3		T83	10		T393	5
all_values[16]	3331	1			T82	3		T83	5		T393	9
all_values[17]	3317	1			T82	6		T83	7		T393	11
all_values[18]	3243	1			T82	3		T83	9		T393	9
all_values[19]	3403	1			T82	5		T83	8		T393	11
all_values[20]	3381	1			T82	3		T83	4		T393	11
all_values[21]	3439	1			T82	5		T83	3		T393	10
all_values[22]	3324	1			T83	5		T393	7		T389	1
all_values[23]	3401	1			T82	4		T83	3		T393	4
all_values[24]	3378	1			T82	2		T83	9		T393	3
all_values[25]	3447	1			T82	2		T83	4		T393	12
all_values[26]	3392	1			T82	4		T83	7		T393	7
all_values[27]	3372	1			T82	4		T83	7		T393	7
all_values[28]	3322	1			T82	1		T83	10		T393	8
all_values[29]	3347	1			T82	2		T83	5		T393	7
all_values[30]	3362	1			T82	3		T83	6		T393	6
all_values[31]	3467	1			T82	3		T83	11		T393	11
all_values[32]	3234	1			T82	6		T83	11		T393	11
all_values[33]	3405	1			T82	2		T83	5		T393	5
all_values[34]	3392	1			T82	3		T83	11		T393	7
all_values[35]	3374	1			T82	3		T83	6		T393	5
all_values[36]	3292	1			T82	4		T83	6		T393	5
all_values[37]	3349	1			T82	2		T83	3		T393	3
all_values[38]	3452	1			T82	4		T83	4		T393	8
all_values[39]	3424	1			T82	2		T83	5		T393	11
all_values[40]	3381	1			T82	3		T83	7		T393	11
all_values[41]	3369	1			T82	2		T83	5		T393	11
all_values[42]	3346	1			T82	6		T83	9		T393	14
all_values[43]	3430	1			T82	1		T83	3		T393	6
all_values[44]	3396	1			T82	5		T83	3		T393	10
all_values[45]	3317	1			T82	3		T83	3		T393	8
all_values[46]	3359	1			T82	3		T83	9		T393	9
all_values[47]	3378	1			T82	2		T83	2		T393	10
all_values[48]	3376	1			T82	5		T83	10		T393	8
all_values[49]	3304	1			T82	3		T83	4		T393	7
all_values[50]	3379	1			T82	2		T83	5		T393	4
all_values[51]	3275	1			T82	2		T83	5		T393	5
all_values[52]	3379	1			T82	3		T83	3		T393	9
all_values[53]	3283	1			T82	2		T83	11		T393	9
all_values[54]	3444	1			T82	5		T83	10		T393	10
all_values[55]	3359	1			T82	1		T83	9		T393	4
all_values[56]	3432	1			T82	6		T83	6		T393	5
all_values[57]	3393	1			T82	7		T83	6		T393	7
all_values[58]	3316	1			T82	4		T83	2		T393	9
all_values[59]	3452	1			T82	5		T83	9		T393	9
all_values[60]	3359	1			T82	1		T83	6		T393	12
all_values[61]	3335	1			T83	7		T393	9		T389	5
all_values[62]	3284	1			T82	6		T83	6		T393	2
all_values[63]	3337	1			T82	4		T83	5		T393	7