Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	484	1			T150	1		T251	5		T429	4
all_values[1]	510	1			T251	6		T429	2		T588	1
all_values[2]	485	1			T150	1		T430	1		T251	4
all_values[3]	473	1			T251	2		T429	5		T588	1
all_values[4]	478	1			T150	1		T251	1		T429	4
all_values[5]	420	1			T251	2		T429	4		T451	1
all_values[6]	429	1			T250	1		T251	3		T429	6
all_values[7]	430	1			T250	1		T251	1		T429	1
all_values[8]	488	1			T251	6		T429	4		T588	2
all_values[9]	447	1			T250	2		T430	1		T251	3
all_values[10]	468	1			T250	1		T251	6		T429	5
all_values[11]	465	1			T150	1		T251	3		T429	7
all_values[12]	467	1			T251	1		T429	3		T588	1
all_values[13]	485	1			T251	3		T429	7		T451	1
all_values[14]	423	1			T251	3		T429	4		T451	3
all_values[15]	469	1			T251	1		T429	1		T588	1
all_values[16]	469	1			T150	1		T251	7		T429	5
all_values[17]	445	1			T150	1		T250	1		T251	4
all_values[18]	490	1			T251	3		T429	7		T588	1
all_values[19]	486	1			T250	1		T251	3		T429	5
all_values[20]	459	1			T251	6		T429	11		T588	1
all_values[21]	449	1			T250	1		T251	2		T429	6
all_values[22]	458	1			T150	1		T251	1		T429	4
all_values[23]	447	1			T251	3		T429	4		T588	1
all_values[24]	503	1			T251	4		T429	8		T865	1
all_values[25]	438	1			T251	3		T429	5		T539	4
all_values[26]	484	1			T430	1		T251	4		T429	4
all_values[27]	443	1			T251	3		T429	9		T539	3
all_values[28]	464	1			T251	3		T428	1		T451	1
all_values[29]	443	1			T251	1		T429	4		T588	1
all_values[30]	495	1			T251	2		T429	3		T451	1
all_values[31]	473	1			T250	1		T251	2		T429	4
all_values[32]	470	1			T150	2		T430	1		T251	4
all_values[33]	468	1			T251	3		T429	10		T428	1
all_values[34]	470	1			T430	1		T251	2		T429	5
all_values[35]	454	1			T250	1		T430	1		T251	2
all_values[36]	424	1			T250	1		T251	2		T429	8
all_values[37]	438	1			T251	2		T429	6		T539	4
all_values[38]	482	1			T251	5		T429	5		T588	2
all_values[39]	461	1			T251	3		T429	5		T451	1
all_values[40]	428	1			T251	2		T429	6		T588	1
all_values[41]	459	1			T150	1		T251	6		T429	1
all_values[42]	463	1			T430	1		T251	6		T429	2
all_values[43]	472	1			T150	1		T251	1		T429	4
all_values[44]	446	1			T251	4		T429	4		T450	1
all_values[45]	426	1			T251	4		T429	6		T588	1
all_values[46]	441	1			T150	1		T430	2		T251	2
all_values[47]	461	1			T251	1		T429	5		T588	2
all_values[48]	493	1			T250	1		T430	1		T251	4
all_values[49]	473	1			T250	1		T251	5		T429	5