Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.09 95.49 93.92 95.38 94.65 97.53 99.58


Total tests in report: 2911
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
39.70 39.70 43.80 43.80 44.05 44.05 30.94 30.94 57.51 57.51 58.74 58.74 3.14 3.14 /workspace/coverage/default/0.chip_sw_alert_test.1204826853
48.48 8.78 58.72 14.92 63.06 19.01 36.88 5.93 69.96 12.45 58.74 0.00 3.52 0.39 /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.1789608580
54.61 6.13 71.84 13.12 72.19 9.13 38.89 2.02 82.46 12.50 58.74 0.00 3.52 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_0.3452658194
59.62 5.02 75.78 3.94 72.53 0.35 39.85 0.96 82.47 0.01 58.74 0.00 28.36 24.84 /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.997757332
63.80 4.18 76.12 0.33 73.88 1.35 39.94 0.09 82.64 0.17 81.82 23.08 28.41 0.05 /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.2269683903
67.40 3.60 76.12 0.00 74.09 0.20 39.94 0.00 82.70 0.06 81.82 0.00 49.76 21.35 /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3096145274
70.85 3.45 82.19 6.07 78.45 4.36 43.82 3.88 84.70 2.00 86.19 4.37 49.76 0.00 /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.4158191559
73.66 2.81 82.19 0.00 79.02 0.57 43.82 0.00 84.73 0.03 86.19 0.00 66.00 16.24 /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.1481357610
76.41 2.75 82.19 0.00 79.03 0.01 60.13 16.31 84.74 0.01 86.36 0.17 66.01 0.01 /workspace/coverage/default/0.rom_keymgr_functest.4103579147
77.91 1.50 82.19 0.00 79.06 0.03 60.13 0.00 84.74 0.00 86.36 0.00 75.00 8.99 /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2619815914
79.33 1.42 82.54 0.35 79.22 0.16 67.42 7.29 84.92 0.19 86.89 0.52 75.00 0.00 /workspace/coverage/default/1.rom_raw_unlock.632099093
80.73 1.40 82.54 0.01 79.40 0.19 69.20 1.78 84.96 0.03 86.89 0.00 81.37 6.37 /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.3357497251
82.10 1.38 84.31 1.76 80.73 1.32 72.06 2.86 86.75 1.79 87.41 0.52 81.37 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1343873024
83.34 1.24 84.31 0.00 80.73 0.00 79.49 7.43 86.75 0.00 87.41 0.00 81.37 0.00 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3326123729
84.42 1.08 86.10 1.80 82.90 2.17 79.73 0.24 88.65 1.90 87.76 0.35 81.37 0.00 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2361202164
85.42 1.00 86.89 0.79 83.47 0.57 80.11 0.37 89.26 0.61 91.43 3.67 81.37 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3492300966
86.42 1.00 86.89 0.00 83.56 0.08 80.11 0.00 89.26 0.00 91.43 0.00 87.29 5.92 /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1127979403
87.40 0.97 86.89 0.00 83.56 0.00 80.11 0.00 89.26 0.00 91.43 0.00 93.13 5.84 /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.1770427788
88.20 0.81 87.59 0.69 83.71 0.15 80.12 0.01 89.40 0.15 95.28 3.85 93.13 0.00 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.529333765
88.94 0.73 88.64 1.05 84.81 1.11 81.09 0.97 90.67 1.27 95.28 0.00 93.13 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_20.3434438188
89.57 0.64 90.03 1.39 85.71 0.90 81.83 0.74 91.29 0.62 95.45 0.17 93.13 0.00 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2329782901
90.20 0.63 91.35 1.32 86.66 0.95 82.59 0.76 92.04 0.75 95.45 0.00 93.13 0.00 /workspace/coverage/default/2.chip_sw_gpio_smoketest.633472212
90.63 0.43 91.35 0.00 86.66 0.00 85.14 2.55 92.04 0.00 95.45 0.00 93.13 0.00 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.265786606
91.04 0.41 91.35 0.00 86.91 0.25 85.16 0.02 92.06 0.02 95.45 0.00 95.30 2.17 /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.628859659
91.43 0.39 91.58 0.23 87.10 0.19 86.95 1.78 92.19 0.14 95.45 0.00 95.30 0.00 /workspace/coverage/default/2.chip_jtag_csr_rw.1426618264
91.80 0.37 91.66 0.08 87.13 0.03 89.04 2.09 92.21 0.02 95.45 0.00 95.30 0.00 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3417236066
92.14 0.34 91.67 0.01 88.73 1.60 89.04 0.00 92.21 0.00 95.45 0.00 95.72 0.42 /workspace/coverage/cover_reg_top/21.chip_tl_errors.770734676
92.43 0.29 92.60 0.93 88.95 0.22 89.18 0.14 92.31 0.10 95.80 0.35 95.72 0.00 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.1813669809
92.69 0.26 92.60 0.00 88.96 0.02 89.18 0.00 92.31 0.00 95.80 0.00 97.26 1.54 /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.4200611559
92.90 0.21 92.94 0.34 89.41 0.45 89.25 0.07 92.72 0.41 95.80 0.00 97.26 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_10.344163414
93.07 0.18 93.08 0.14 89.49 0.08 90.02 0.77 92.77 0.05 95.80 0.00 97.27 0.01 /workspace/coverage/default/65.chip_sw_all_escalation_resets.1039632494
93.25 0.17 93.39 0.31 89.68 0.19 90.26 0.25 93.05 0.28 95.80 0.00 97.29 0.01 /workspace/coverage/default/2.rom_e2e_shutdown_output.1345952374
93.42 0.17 93.39 0.01 90.16 0.48 90.26 0.00 93.61 0.55 95.80 0.00 97.29 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.965562946
93.58 0.16 93.39 0.00 90.18 0.01 90.27 0.01 93.61 0.00 95.80 0.00 98.21 0.93 /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.2454176741
93.72 0.15 93.39 0.00 90.18 0.00 91.14 0.87 93.61 0.00 95.80 0.00 98.21 0.00 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.581603759
93.86 0.14 93.57 0.18 90.29 0.11 91.24 0.09 93.73 0.12 96.15 0.35 98.21 0.00 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2163049362
94.00 0.13 93.85 0.28 90.41 0.12 91.36 0.12 93.80 0.07 96.33 0.17 98.23 0.01 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1878507992
94.12 0.13 94.06 0.21 90.73 0.32 91.58 0.22 93.80 0.00 96.33 0.00 98.23 0.00 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4059253746
94.24 0.12 94.06 0.00 90.73 0.00 92.23 0.65 93.80 0.00 96.33 0.00 98.27 0.05 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.235145194
94.35 0.11 94.06 0.00 91.41 0.67 92.23 0.00 93.80 0.00 96.33 0.00 98.27 0.00 /workspace/coverage/cover_reg_top/0.chip_tl_errors.1513236107
94.45 0.10 94.09 0.03 91.43 0.02 92.76 0.52 93.81 0.01 96.33 0.00 98.27 0.00 /workspace/coverage/default/38.chip_sw_all_escalation_resets.2425917447
94.54 0.10 94.09 0.00 91.70 0.27 92.76 0.00 94.12 0.31 96.33 0.00 98.27 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2595782020
94.62 0.08 94.27 0.18 91.86 0.16 92.76 0.00 94.22 0.11 96.33 0.00 98.27 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.87339413
94.69 0.07 94.27 0.00 91.86 0.00 93.21 0.45 94.22 0.00 96.33 0.00 98.27 0.00 /workspace/coverage/default/2.chip_sw_edn_auto_mode.3846041710
94.76 0.07 94.27 0.00 91.86 0.00 93.61 0.41 94.22 0.00 96.33 0.00 98.27 0.00 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2127159088
94.83 0.06 94.29 0.02 91.89 0.03 93.75 0.13 94.25 0.02 96.50 0.17 98.27 0.00 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.1659073907
94.89 0.06 94.31 0.01 91.90 0.01 94.08 0.33 94.25 0.00 96.50 0.00 98.30 0.02 /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.2670928930
94.94 0.05 94.31 0.00 92.22 0.32 94.08 0.00 94.25 0.00 96.50 0.00 98.30 0.00 /workspace/coverage/cover_reg_top/24.chip_tl_errors.3948156981
94.99 0.05 94.33 0.02 92.28 0.06 94.11 0.04 94.26 0.02 96.68 0.17 98.30 0.00 /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.66330357
95.04 0.04 94.36 0.03 92.28 0.01 94.15 0.04 94.27 0.01 96.85 0.17 98.30 0.00 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.871028877
95.07 0.04 94.36 0.01 92.30 0.02 94.16 0.01 94.29 0.02 97.03 0.17 98.31 0.01 /workspace/coverage/default/72.chip_sw_all_escalation_resets.2829369095
95.11 0.04 94.37 0.01 92.32 0.01 94.16 0.00 94.31 0.02 97.20 0.17 98.32 0.01 /workspace/coverage/default/27.chip_sw_all_escalation_resets.1298606215
95.15 0.04 94.38 0.01 92.33 0.01 94.16 0.01 94.32 0.01 97.38 0.17 98.33 0.01 /workspace/coverage/default/22.chip_sw_all_escalation_resets.3557546567
95.18 0.03 94.38 0.00 92.47 0.14 94.16 0.00 94.34 0.02 97.38 0.00 98.38 0.05 /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.3482467725
95.22 0.03 94.38 0.00 92.48 0.01 94.19 0.03 94.34 0.00 97.55 0.17 98.38 0.00 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.534282254
95.25 0.03 94.38 0.00 92.48 0.00 94.38 0.19 94.34 0.00 97.55 0.00 98.38 0.00 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2581961129
95.28 0.03 94.38 0.00 92.66 0.18 94.38 0.00 94.34 0.00 97.55 0.00 98.38 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_0.2123147212
95.31 0.03 94.41 0.03 92.74 0.08 94.39 0.01 94.39 0.05 97.55 0.00 98.38 0.00 /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.3148956510
95.34 0.03 94.48 0.07 92.77 0.03 94.40 0.01 94.43 0.05 97.55 0.00 98.38 0.00 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3146402605
95.36 0.03 94.54 0.07 92.82 0.05 94.41 0.01 94.47 0.03 97.55 0.00 98.38 0.00 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1419799343
95.38 0.02 94.61 0.07 92.82 0.00 94.47 0.06 94.47 0.01 97.55 0.00 98.38 0.00 /workspace/coverage/default/0.chip_tap_straps_testunlock0.1655876688
95.41 0.02 94.68 0.07 92.87 0.05 94.47 0.01 94.50 0.02 97.55 0.00 98.38 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1754109387
95.43 0.02 94.68 0.00 92.88 0.01 94.47 0.00 94.50 0.00 97.55 0.00 98.50 0.12 /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.4212810183
95.45 0.02 94.68 0.00 92.88 0.00 94.60 0.13 94.50 0.00 97.55 0.00 98.50 0.00 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.186239702
95.47 0.02 94.68 0.00 92.88 0.00 94.71 0.11 94.50 0.00 97.55 0.00 98.50 0.00 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3197304176
95.49 0.02 94.71 0.03 92.93 0.05 94.73 0.01 94.52 0.02 97.55 0.00 98.50 0.00 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2429962256
95.51 0.02 94.74 0.03 92.97 0.04 94.74 0.01 94.55 0.02 97.55 0.00 98.50 0.00 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1341100383
95.53 0.02 94.74 0.00 93.00 0.03 94.74 0.00 94.56 0.02 97.55 0.00 98.55 0.06 /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.4046180807
95.54 0.02 94.75 0.01 93.02 0.01 94.81 0.07 94.58 0.02 97.55 0.00 98.55 0.00 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2169428171
95.56 0.02 94.75 0.00 93.02 0.00 94.90 0.10 94.58 0.00 97.55 0.00 98.55 0.00 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.499946431
95.57 0.01 94.75 0.00 93.10 0.08 94.90 0.00 94.58 0.00 97.55 0.00 98.55 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_0.2052883821
95.59 0.01 94.75 0.00 93.15 0.05 94.90 0.00 94.58 0.00 97.55 0.00 98.59 0.04 /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.2861685084
95.60 0.01 94.75 0.00 93.22 0.07 94.90 0.00 94.58 0.00 97.55 0.00 98.59 0.00 /workspace/coverage/cover_reg_top/17.chip_tl_errors.343663046
95.61 0.01 94.75 0.00 93.29 0.07 94.90 0.00 94.58 0.00 97.55 0.00 98.59 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_20.4107319299
95.62 0.01 94.76 0.01 93.33 0.04 94.92 0.02 94.58 0.00 97.55 0.00 98.59 0.00 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.546286925
95.63 0.01 94.78 0.02 93.34 0.01 94.93 0.01 94.60 0.02 97.55 0.00 98.59 0.00 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3338172580
95.64 0.01 94.80 0.02 93.34 0.01 94.93 0.01 94.61 0.02 97.55 0.00 98.59 0.00 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.18732122
95.65 0.01 94.83 0.02 93.35 0.01 94.94 0.01 94.63 0.02 97.55 0.00 98.59 0.00 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1717660216
95.66 0.01 94.83 0.00 93.36 0.01 94.94 0.00 94.63 0.00 97.55 0.00 98.63 0.04 /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2991476086
95.66 0.01 94.83 0.00 93.36 0.00 94.94 0.00 94.63 0.00 97.55 0.00 98.67 0.05 /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3603818284
95.67 0.01 94.83 0.00 93.36 0.00 94.98 0.05 94.63 0.00 97.55 0.00 98.67 0.00 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3063944752
95.68 0.01 94.83 0.00 93.37 0.01 95.00 0.02 94.63 0.00 97.55 0.00 98.68 0.01 /workspace/coverage/default/62.chip_sw_all_escalation_resets.137062492
95.69 0.01 94.83 0.00 93.37 0.00 95.05 0.04 94.63 0.00 97.55 0.00 98.68 0.00 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3622840927
95.69 0.01 94.83 0.00 93.37 0.00 95.09 0.04 94.63 0.00 97.55 0.00 98.68 0.00 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.275695356
95.70 0.01 94.84 0.01 93.40 0.02 95.09 0.01 94.63 0.00 97.55 0.00 98.68 0.00 /workspace/coverage/default/1.chip_jtag_csr_rw.3720224847
95.70 0.01 94.84 0.00 93.43 0.04 95.09 0.00 94.63 0.00 97.55 0.00 98.68 0.00 /workspace/coverage/cover_reg_top/14.chip_tl_errors.2158814101
95.71 0.01 94.84 0.00 93.43 0.00 95.09 0.00 94.63 0.00 97.55 0.00 98.72 0.04 /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1312937655
95.72 0.01 94.84 0.00 93.43 0.00 95.12 0.04 94.63 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1091957750
95.72 0.01 94.84 0.00 93.46 0.02 95.14 0.01 94.63 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2661212454
95.73 0.01 94.84 0.00 93.49 0.03 95.14 0.00 94.63 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_20.1840486184
95.73 0.01 94.84 0.00 93.51 0.02 95.15 0.01 94.63 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.4114405733
95.74 0.01 94.84 0.00 93.53 0.03 95.15 0.00 94.63 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/cover_reg_top/22.chip_tl_errors.3085309331
95.74 0.01 94.84 0.00 93.56 0.03 95.15 0.00 94.63 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/cover_reg_top/26.xbar_access_same_device.1540064702
95.75 0.01 94.84 0.00 93.56 0.00 95.18 0.03 94.63 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2127927839
95.75 0.01 94.84 0.01 93.57 0.01 95.20 0.02 94.63 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3300703016
95.76 0.01 94.84 0.01 93.58 0.01 95.21 0.01 94.63 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1303866440
95.76 0.01 94.84 0.00 93.58 0.00 95.23 0.03 94.63 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.1649492833
95.76 0.01 94.87 0.02 93.58 0.00 95.24 0.01 94.63 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/default/0.chip_sw_power_idle_load.383160322
95.77 0.01 94.87 0.00 93.60 0.02 95.24 0.00 94.63 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/cover_reg_top/35.xbar_stress_all.605907268
95.77 0.01 94.87 0.00 93.63 0.02 95.24 0.00 94.63 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_10.3806673033
95.78 0.01 94.87 0.00 93.63 0.00 95.24 0.00 94.63 0.00 97.55 0.00 98.74 0.02 /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.3511963824
95.78 0.01 94.87 0.00 93.63 0.00 95.24 0.00 94.63 0.00 97.55 0.00 98.77 0.02 /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.3382265978
95.78 0.01 94.87 0.00 93.65 0.02 95.24 0.00 94.63 0.00 97.55 0.00 98.77 0.00 /workspace/coverage/default/2.chip_sw_gpio.85539986
95.79 0.01 94.87 0.00 93.65 0.00 95.25 0.01 94.63 0.00 97.55 0.00 98.78 0.01 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3294420919
95.79 0.01 94.87 0.00 93.66 0.01 95.25 0.00 94.63 0.00 97.55 0.00 98.79 0.01 /workspace/coverage/cover_reg_top/3.chip_tl_errors.1665435493
95.79 0.01 94.87 0.01 93.67 0.01 95.25 0.01 94.63 0.00 97.55 0.00 98.79 0.00 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3005418755
95.80 0.01 94.87 0.00 93.69 0.02 95.25 0.00 94.63 0.00 97.55 0.00 98.79 0.00 /workspace/coverage/cover_reg_top/26.xbar_stress_all.956164797
95.80 0.01 94.87 0.00 93.70 0.02 95.25 0.00 94.63 0.00 97.55 0.00 98.79 0.00 /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.1607045739
95.80 0.01 94.87 0.00 93.70 0.00 95.27 0.02 94.63 0.00 97.55 0.00 98.79 0.00 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.4123881670
95.80 0.01 94.87 0.00 93.71 0.01 95.27 0.00 94.63 0.00 97.55 0.00 98.80 0.01 /workspace/coverage/cover_reg_top/15.chip_tl_errors.1269338157
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95.99 0.01 94.91 0.00 93.89 0.01 95.36 0.00 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.3322690260
95.99 0.01 94.91 0.00 93.89 0.01 95.36 0.00 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/cover_reg_top/40.xbar_error_random.15787985
95.99 0.01 94.91 0.00 93.90 0.01 95.36 0.00 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.2383716947
95.99 0.01 94.91 0.00 93.90 0.01 95.36 0.00 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.47249860
95.99 0.01 94.91 0.00 93.90 0.01 95.36 0.00 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/cover_reg_top/80.xbar_error_random.3507973279
95.99 0.01 94.91 0.00 93.91 0.01 95.36 0.00 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.1839702571
95.99 0.01 94.91 0.00 93.91 0.01 95.36 0.00 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/default/0.chip_sw_gpio.1917381928
95.99 0.01 94.91 0.00 93.92 0.01 95.36 0.00 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3255250526
96.00 0.01 94.91 0.00 93.92 0.01 95.36 0.00 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2236695727
96.00 0.01 94.91 0.00 93.92 0.01 95.36 0.00 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_10.2736917862
96.00 0.01 94.91 0.00 93.92 0.00 95.37 0.01 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/default/0.chip_tap_straps_rma.3133739854
96.00 0.01 94.91 0.00 93.92 0.00 95.37 0.01 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/default/0.chip_sw_edn_boot_mode.1843840872
96.00 0.01 94.91 0.00 93.92 0.00 95.37 0.01 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2335808755
96.00 0.01 94.91 0.00 93.92 0.00 95.37 0.01 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2653791381
96.00 0.01 94.91 0.00 93.92 0.00 95.38 0.01 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3632728161
96.00 0.01 94.91 0.00 93.92 0.00 95.38 0.01 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1240741964
96.00 0.01 94.91 0.00 93.92 0.00 95.38 0.01 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1185687662
96.00 0.01 94.91 0.00 93.92 0.00 95.38 0.01 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1007243111
96.00 0.01 94.91 0.00 93.92 0.00 95.38 0.01 94.65 0.00 97.55 0.00 99.58 0.00 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1863325065


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.684802373
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.599322574
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2843279020
/workspace/coverage/cover_reg_top/0.chip_csr_rw.709276572
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3823639445
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.942143868
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.4191341637
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2476227607
/workspace/coverage/cover_reg_top/0.xbar_error_random.4097008251
/workspace/coverage/cover_reg_top/0.xbar_random.3008496685
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2946140715
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.134616263
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.81917098
/workspace/coverage/cover_reg_top/0.xbar_same_source.2642751442
/workspace/coverage/cover_reg_top/0.xbar_smoke.3184737923
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.4008420197
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2412661825
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3280468349
/workspace/coverage/cover_reg_top/0.xbar_stress_all.755979690
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2901788672
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3312301209
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1346609012
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2233926968
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2348349953
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1159085345
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.313969449
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2611394277
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.768213106
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1456423398
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1671104082
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2393284137
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.522697846
/workspace/coverage/cover_reg_top/1.xbar_error_random.1343031347
/workspace/coverage/cover_reg_top/1.xbar_random.3653151383
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.229935284
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.298674148
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.115452841
/workspace/coverage/cover_reg_top/1.xbar_same_source.381384612
/workspace/coverage/cover_reg_top/1.xbar_smoke.2933192012
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.4114004620
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3813645079
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1395694952
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1529400314
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2615395244
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.160029848
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1314750794
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1252825761
/workspace/coverage/cover_reg_top/10.chip_tl_errors.1927285254
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1204758557
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.4048848284
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1294029010
/workspace/coverage/cover_reg_top/10.xbar_error_random.3946850054
/workspace/coverage/cover_reg_top/10.xbar_random.3161752335
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1793118417
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.250673013
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1035919348
/workspace/coverage/cover_reg_top/10.xbar_same_source.2918723492
/workspace/coverage/cover_reg_top/10.xbar_smoke.2122200214
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.341204867
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1861522682
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3523827423
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1163520730
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.433680999
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1157746152
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.207173862
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1394640432
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3233701832
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2418322808
/workspace/coverage/cover_reg_top/11.chip_tl_errors.4050339323
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2139561193
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3330227686
/workspace/coverage/cover_reg_top/11.xbar_error_random.695704003
/workspace/coverage/cover_reg_top/11.xbar_random.1300993358
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1756063539
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.4223808312
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.317674540
/workspace/coverage/cover_reg_top/11.xbar_same_source.3817204129
/workspace/coverage/cover_reg_top/11.xbar_smoke.3473599495
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.953986074
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.605039077
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2196124793
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1888597777
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2832709763
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2326447145
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1755592763
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1961699486
/workspace/coverage/cover_reg_top/12.chip_csr_rw.732388682
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.979457004
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.103545278
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.87343164
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3999251768
/workspace/coverage/cover_reg_top/12.xbar_error_random.1902731557
/workspace/coverage/cover_reg_top/12.xbar_random.815147573
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2727006132
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2782797712
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3855189149
/workspace/coverage/cover_reg_top/12.xbar_same_source.3106449990
/workspace/coverage/cover_reg_top/12.xbar_smoke.2380655353
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1988785644
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3593825760
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3559483358
/workspace/coverage/cover_reg_top/12.xbar_stress_all.529167368
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3201700190
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1055903283
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2270585259
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3311169406
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.4150212791
/workspace/coverage/cover_reg_top/13.chip_tl_errors.3886662869
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3174496100
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1426363090
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2791003222
/workspace/coverage/cover_reg_top/13.xbar_error_random.717073527
/workspace/coverage/cover_reg_top/13.xbar_random.2253738008
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2110870842
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.227784031
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3283863352
/workspace/coverage/cover_reg_top/13.xbar_same_source.2116812184
/workspace/coverage/cover_reg_top/13.xbar_smoke.2103262823
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2668671178
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.906572264
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3822212320
/workspace/coverage/cover_reg_top/13.xbar_stress_all.3826193060
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1042228711
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.536535704
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1758742817
/workspace/coverage/cover_reg_top/14.chip_csr_rw.1972146807
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.591236208
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.668028230
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.211159466
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3412618089
/workspace/coverage/cover_reg_top/14.xbar_error_random.465685147
/workspace/coverage/cover_reg_top/14.xbar_random.3206947387
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3008102941
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1038386759
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3012396153
/workspace/coverage/cover_reg_top/14.xbar_same_source.1314552008
/workspace/coverage/cover_reg_top/14.xbar_smoke.1541720194
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2991133104
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1184337641
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.1691743735
/workspace/coverage/cover_reg_top/14.xbar_stress_all.2576374392
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.1302598212
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.4008893740
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3472685573
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.2994348003
/workspace/coverage/cover_reg_top/15.chip_csr_rw.1117164225
/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.2276430797
/workspace/coverage/cover_reg_top/15.xbar_access_same_device.3233673622
/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.1422060702
/workspace/coverage/cover_reg_top/15.xbar_error_random.3004691553
/workspace/coverage/cover_reg_top/15.xbar_random.39932336
/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.1208409241
/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.4169867825
/workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.1470599795
/workspace/coverage/cover_reg_top/15.xbar_same_source.3711561826
/workspace/coverage/cover_reg_top/15.xbar_smoke.1629386847
/workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.1417044145
/workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3278311254
/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3419453078
/workspace/coverage/cover_reg_top/15.xbar_stress_all.266270933
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.2124526870
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3421870329
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3186558336
/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.1132896277
/workspace/coverage/cover_reg_top/16.chip_csr_rw.3825761911
/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.879662830
/workspace/coverage/cover_reg_top/16.chip_tl_errors.2966493506
/workspace/coverage/cover_reg_top/16.xbar_access_same_device.1980890361
/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3957287991
/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3220647324
/workspace/coverage/cover_reg_top/16.xbar_error_random.1375572596
/workspace/coverage/cover_reg_top/16.xbar_random.3238322489
/workspace/coverage/cover_reg_top/16.xbar_random_large_delays.720503757
/workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.4249850326
/workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.3264399044
/workspace/coverage/cover_reg_top/16.xbar_same_source.602452747
/workspace/coverage/cover_reg_top/16.xbar_smoke.3849591372
/workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.2938657481
/workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.720425367
/workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.3421911514
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.876525972
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.1091502595
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.2018358439
/workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.640464370
/workspace/coverage/cover_reg_top/17.chip_csr_rw.3435237688
/workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.2264103399
/workspace/coverage/cover_reg_top/17.xbar_access_same_device.2533171340
/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1901037636
/workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3447163100
/workspace/coverage/cover_reg_top/17.xbar_error_random.3359882812
/workspace/coverage/cover_reg_top/17.xbar_random.2617269337
/workspace/coverage/cover_reg_top/17.xbar_random_large_delays.1505286554
/workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.1625248
/workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.3187859907
/workspace/coverage/cover_reg_top/17.xbar_same_source.3306502726
/workspace/coverage/cover_reg_top/17.xbar_smoke.2445308247
/workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.1676784982
/workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2153090342
/workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.2475721063
/workspace/coverage/cover_reg_top/17.xbar_stress_all.1121010321
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.3297121011
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.534254269
/workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.3045948405
/workspace/coverage/cover_reg_top/18.chip_csr_rw.3608900387
/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1583841024
/workspace/coverage/cover_reg_top/18.chip_tl_errors.743831780
/workspace/coverage/cover_reg_top/18.xbar_access_same_device.2198402137
/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.4034451630
/workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2289384919
/workspace/coverage/cover_reg_top/18.xbar_error_random.548640656
/workspace/coverage/cover_reg_top/18.xbar_random.1969885690
/workspace/coverage/cover_reg_top/18.xbar_random_large_delays.2033890294
/workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.885675925
/workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.1315325901
/workspace/coverage/cover_reg_top/18.xbar_same_source.2740000296
/workspace/coverage/cover_reg_top/18.xbar_smoke.1789800648
/workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.1298048001
/workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3809452308
/workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1230383950
/workspace/coverage/cover_reg_top/18.xbar_stress_all.2407566604
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/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2535434295
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1677282267
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2984481179
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1790380952
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.229624168
/workspace/coverage/default/46.chip_sw_all_escalation_resets.916434893
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3202191656
/workspace/coverage/default/47.chip_sw_all_escalation_resets.1490166882
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3326173453
/workspace/coverage/default/48.chip_sw_all_escalation_resets.657096230
/workspace/coverage/default/49.chip_sw_all_escalation_resets.3559660200
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2799514481
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3853300479
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2780797804
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1717348594
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3910694978
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.226112724
/workspace/coverage/default/51.chip_sw_all_escalation_resets.3251764519
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1760238471
/workspace/coverage/default/52.chip_sw_all_escalation_resets.3296213964
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1659879291
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3468495443
/workspace/coverage/default/54.chip_sw_all_escalation_resets.740862356
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.764130074
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3627017736
/workspace/coverage/default/56.chip_sw_all_escalation_resets.2927874884
/workspace/coverage/default/57.chip_sw_all_escalation_resets.16762255
/workspace/coverage/default/58.chip_sw_all_escalation_resets.531760966
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3443845616
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.689083258
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2280978865
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1714935210
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1736657342
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3715620133
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2252986421
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1389964273
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1153512244
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2740306854
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2732638405
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2658015613
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3441315287
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3095716515
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3926606306
/workspace/coverage/default/68.chip_sw_all_escalation_resets.28894805
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2362578449
/workspace/coverage/default/69.chip_sw_all_escalation_resets.349467477
/workspace/coverage/default/7.chip_sw_all_escalation_resets.417196007
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.989171996
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2318224212
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1259345022
/workspace/coverage/default/70.chip_sw_all_escalation_resets.762322562
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2200399807
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2113293600
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2740219860
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.4211426228
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1401333267
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3612034155
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2029407608
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2758966959
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.947128312
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2400727488
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4249265896
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3102944819
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2984487829
/workspace/coverage/default/78.chip_sw_all_escalation_resets.595232883
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.500880978
/workspace/coverage/default/79.chip_sw_all_escalation_resets.233926948
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2485711866
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3305492666
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2147556691
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1006202371
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3713563634
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1106114847
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3518978951
/workspace/coverage/default/81.chip_sw_all_escalation_resets.968883585
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.414324327
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3405998221
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2955293970
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.918911326
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2395908281
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2754562037
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.76607212
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1847240614
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2605482744
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.475027293
/workspace/coverage/default/88.chip_sw_all_escalation_resets.577719386
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.952591757
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.483848971
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1145521171
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3775586502
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3299323025
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3958202158
/workspace/coverage/default/90.chip_sw_all_escalation_resets.697960434
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2835128267
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2119179117
/workspace/coverage/default/94.chip_sw_all_escalation_resets.363117336
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2109058199
/workspace/coverage/default/97.chip_sw_all_escalation_resets.4221828968
/workspace/coverage/default/98.chip_sw_all_escalation_resets.222724743
/workspace/coverage/default/99.chip_sw_all_escalation_resets.854981553
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.580650830
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1687046331
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1850617548
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1878469081
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1345741436
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.4206061303
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3395312030
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1955547992




Total test records in report: 2911
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspace/coverage/default/2.chip_sw_gpio_smoketest.633472212 Jul 13 08:07:49 PM PDT 24 Jul 13 08:12:37 PM PDT 24 2604018392 ps
T5 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1070299549 Jul 13 08:01:08 PM PDT 24 Jul 13 08:05:10 PM PDT 24 3233985453 ps
T6 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2702494588 Jul 13 08:07:47 PM PDT 24 Jul 13 08:16:24 PM PDT 24 7704738088 ps
T41 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.967975825 Jul 13 07:55:10 PM PDT 24 Jul 13 08:01:33 PM PDT 24 4692500150 ps
T60 /workspace/coverage/default/0.chip_sw_alert_test.1204826853 Jul 13 07:46:35 PM PDT 24 Jul 13 07:51:34 PM PDT 24 2819106900 ps
T15 /workspace/coverage/default/62.chip_sw_all_escalation_resets.137062492 Jul 13 08:16:03 PM PDT 24 Jul 13 08:26:10 PM PDT 24 4681386432 ps
T16 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3294420919 Jul 13 08:16:31 PM PDT 24 Jul 13 08:22:49 PM PDT 24 3756767420 ps
T17 /workspace/coverage/default/83.chip_sw_all_escalation_resets.393893866 Jul 13 08:16:53 PM PDT 24 Jul 13 08:26:53 PM PDT 24 5569013676 ps
T18 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3390820878 Jul 13 08:02:05 PM PDT 24 Jul 13 08:12:45 PM PDT 24 6681825500 ps
T73 /workspace/coverage/default/0.chip_tap_straps_prod.3653757203 Jul 13 07:46:25 PM PDT 24 Jul 13 08:07:10 PM PDT 24 10398663032 ps
T192 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1878507992 Jul 13 08:09:41 PM PDT 24 Jul 13 08:17:12 PM PDT 24 4218008600 ps
T122 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1343873024 Jul 13 07:45:30 PM PDT 24 Jul 13 07:54:53 PM PDT 24 7161685800 ps
T66 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1345769157 Jul 13 07:47:53 PM PDT 24 Jul 13 08:28:12 PM PDT 24 25458617847 ps
T149 /workspace/coverage/default/0.rom_keymgr_functest.4103579147 Jul 13 07:46:54 PM PDT 24 Jul 13 07:57:59 PM PDT 24 5289671972 ps
T283 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2424510906 Jul 13 07:54:29 PM PDT 24 Jul 13 07:58:02 PM PDT 24 2339345580 ps
T248 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1615617172 Jul 13 08:12:35 PM PDT 24 Jul 13 08:20:47 PM PDT 24 3642474226 ps
T168 /workspace/coverage/default/50.chip_sw_all_escalation_resets.4014399984 Jul 13 08:14:15 PM PDT 24 Jul 13 08:25:56 PM PDT 24 6030824060 ps
T189 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2130917756 Jul 13 07:43:22 PM PDT 24 Jul 13 07:57:07 PM PDT 24 7433124400 ps
T190 /workspace/coverage/default/65.chip_sw_all_escalation_resets.1039632494 Jul 13 08:15:04 PM PDT 24 Jul 13 08:26:10 PM PDT 24 5597164620 ps
T284 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.3843313909 Jul 13 08:05:24 PM PDT 24 Jul 13 08:25:14 PM PDT 24 8139819720 ps
T27 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2169428171 Jul 13 07:44:10 PM PDT 24 Jul 13 09:46:16 PM PDT 24 31767359430 ps
T61 /workspace/coverage/default/1.chip_sw_alert_test.3344386949 Jul 13 07:51:06 PM PDT 24 Jul 13 07:56:10 PM PDT 24 3235137344 ps
T439 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.226112724 Jul 13 08:13:26 PM PDT 24 Jul 13 08:19:31 PM PDT 24 3625644660 ps
T220 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.403318209 Jul 13 07:49:36 PM PDT 24 Jul 13 07:55:09 PM PDT 24 3838355900 ps
T346 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.668933118 Jul 13 07:47:38 PM PDT 24 Jul 13 07:53:32 PM PDT 24 3778419716 ps
T203 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1099126853 Jul 13 08:01:05 PM PDT 24 Jul 13 08:11:31 PM PDT 24 4232620110 ps
T1 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.21867500 Jul 13 07:48:20 PM PDT 24 Jul 13 07:52:51 PM PDT 24 3139072488 ps
T101 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.2800113442 Jul 13 07:50:07 PM PDT 24 Jul 13 08:09:11 PM PDT 24 5962195720 ps
T102 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3723058825 Jul 13 07:57:51 PM PDT 24 Jul 13 08:01:44 PM PDT 24 2917290056 ps
T103 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.1659073907 Jul 13 07:59:07 PM PDT 24 Jul 13 08:13:12 PM PDT 24 5170744512 ps
T104 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.405751254 Jul 13 07:46:30 PM PDT 24 Jul 13 07:52:44 PM PDT 24 3202559790 ps
T105 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3049397637 Jul 13 07:47:09 PM PDT 24 Jul 13 08:11:57 PM PDT 24 8172968900 ps
T106 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.851994883 Jul 13 08:07:10 PM PDT 24 Jul 13 08:23:25 PM PDT 24 8194232544 ps
T107 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4059253746 Jul 13 07:56:06 PM PDT 24 Jul 13 08:04:12 PM PDT 24 5378037940 ps
T108 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2535434295 Jul 13 08:12:55 PM PDT 24 Jul 13 08:19:39 PM PDT 24 3815759400 ps
T109 /workspace/coverage/default/0.chip_sw_aes_enc.1326607519 Jul 13 07:42:19 PM PDT 24 Jul 13 07:44:59 PM PDT 24 2516927400 ps
T245 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2342146730 Jul 13 07:53:55 PM PDT 24 Jul 13 08:02:48 PM PDT 24 4857683464 ps
T268 /workspace/coverage/default/2.chip_sw_hmac_multistream.1282221226 Jul 13 08:03:16 PM PDT 24 Jul 13 08:40:06 PM PDT 24 8188095148 ps
T2 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.87339413 Jul 13 07:43:54 PM PDT 24 Jul 13 07:50:25 PM PDT 24 3615804672 ps
T24 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.1813669809 Jul 13 07:46:15 PM PDT 24 Jul 13 07:57:35 PM PDT 24 6378619288 ps
T83 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.415394121 Jul 13 08:15:21 PM PDT 24 Jul 13 08:21:42 PM PDT 24 3878437376 ps
T91 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3157042007 Jul 13 08:01:25 PM PDT 24 Jul 13 08:14:47 PM PDT 24 4623226660 ps
T92 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.871028877 Jul 13 07:45:34 PM PDT 24 Jul 13 07:56:53 PM PDT 24 5027561480 ps
T93 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1581306194 Jul 13 08:11:05 PM PDT 24 Jul 13 08:18:38 PM PDT 24 3521144144 ps
T94 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2458604555 Jul 13 08:05:57 PM PDT 24 Jul 13 08:08:45 PM PDT 24 2125117290 ps
T95 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.4114405733 Jul 13 07:43:54 PM PDT 24 Jul 13 07:53:55 PM PDT 24 3767727333 ps
T96 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3417236066 Jul 13 07:50:49 PM PDT 24 Jul 13 08:08:28 PM PDT 24 6043236494 ps
T97 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3696937169 Jul 13 08:01:48 PM PDT 24 Jul 13 08:09:06 PM PDT 24 5509513800 ps
T98 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.819061136 Jul 13 07:48:06 PM PDT 24 Jul 13 08:01:54 PM PDT 24 4931905250 ps
T59 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3063944752 Jul 13 07:49:41 PM PDT 24 Jul 13 07:51:53 PM PDT 24 2562417450 ps
T219 /workspace/coverage/default/29.chip_sw_all_escalation_resets.1133572614 Jul 13 08:15:48 PM PDT 24 Jul 13 08:25:53 PM PDT 24 4833790564 ps
T55 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2329782901 Jul 13 08:02:00 PM PDT 24 Jul 13 09:09:20 PM PDT 24 15184996920 ps
T28 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1128125798 Jul 13 08:09:38 PM PDT 24 Jul 13 08:16:16 PM PDT 24 5897174880 ps
T401 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2123784825 Jul 13 07:56:36 PM PDT 24 Jul 13 08:17:13 PM PDT 24 5813209440 ps
T29 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1121946871 Jul 13 07:48:21 PM PDT 24 Jul 13 07:58:18 PM PDT 24 5744314104 ps
T384 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4249265896 Jul 13 08:17:17 PM PDT 24 Jul 13 08:23:40 PM PDT 24 3211028760 ps
T402 /workspace/coverage/default/1.chip_sw_hmac_oneshot.2843581611 Jul 13 07:49:53 PM PDT 24 Jul 13 07:56:55 PM PDT 24 2765373800 ps
T160 /workspace/coverage/default/38.chip_sw_all_escalation_resets.2425917447 Jul 13 08:14:50 PM PDT 24 Jul 13 08:27:50 PM PDT 24 4797005420 ps
T114 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.235138643 Jul 13 07:54:53 PM PDT 24 Jul 13 08:59:58 PM PDT 24 24527370473 ps
T215 /workspace/coverage/default/1.chip_sw_uart_tx_rx.685944295 Jul 13 07:47:48 PM PDT 24 Jul 13 07:57:55 PM PDT 24 4604926906 ps
T123 /workspace/coverage/default/0.chip_sw_edn_kat.2531646861 Jul 13 07:43:23 PM PDT 24 Jul 13 07:56:40 PM PDT 24 3323459366 ps
T211 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2721516146 Jul 13 07:50:03 PM PDT 24 Jul 13 08:07:08 PM PDT 24 4665300624 ps
T789 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3612034155 Jul 13 08:15:42 PM PDT 24 Jul 13 08:21:48 PM PDT 24 3858959756 ps
T307 /workspace/coverage/default/2.chip_plic_all_irqs_0.3452658194 Jul 13 08:04:07 PM PDT 24 Jul 13 08:27:42 PM PDT 24 5638485522 ps
T19 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.186239702 Jul 13 07:49:32 PM PDT 24 Jul 13 07:57:05 PM PDT 24 5136409736 ps
T782 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3713563634 Jul 13 08:16:54 PM PDT 24 Jul 13 08:23:25 PM PDT 24 3212537100 ps
T124 /workspace/coverage/default/2.chip_sw_edn_boot_mode.2886774821 Jul 13 08:01:38 PM PDT 24 Jul 13 08:14:01 PM PDT 24 3400298964 ps
T901 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.1023831386 Jul 13 07:47:38 PM PDT 24 Jul 13 07:52:36 PM PDT 24 3367517106 ps
T314 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2074043002 Jul 13 08:02:44 PM PDT 24 Jul 13 08:06:34 PM PDT 24 2272247276 ps
T783 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2407860021 Jul 13 08:12:09 PM PDT 24 Jul 13 08:19:18 PM PDT 24 4382473200 ps
T246 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2515420700 Jul 13 07:45:18 PM PDT 24 Jul 13 07:53:07 PM PDT 24 4100209676 ps
T20 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3197304176 Jul 13 07:44:57 PM PDT 24 Jul 13 07:47:23 PM PDT 24 3132285181 ps
T221 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1297685495 Jul 13 07:49:52 PM PDT 24 Jul 13 08:18:29 PM PDT 24 8520815360 ps
T56 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.1649492833 Jul 13 07:45:17 PM PDT 24 Jul 13 08:18:32 PM PDT 24 10293174599 ps
T225 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.343758955 Jul 13 07:43:25 PM PDT 24 Jul 13 08:07:01 PM PDT 24 8015676912 ps
T902 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1694571634 Jul 13 07:46:55 PM PDT 24 Jul 13 07:54:01 PM PDT 24 5653819797 ps
T903 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.2159409409 Jul 13 08:02:30 PM PDT 24 Jul 13 08:07:13 PM PDT 24 3607706454 ps
T222 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3326123729 Jul 13 08:04:17 PM PDT 24 Jul 13 08:47:30 PM PDT 24 11658456568 ps
T57 /workspace/coverage/default/1.rom_raw_unlock.632099093 Jul 13 07:57:20 PM PDT 24 Jul 13 08:01:50 PM PDT 24 4430981237 ps
T247 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3071853157 Jul 13 08:03:52 PM PDT 24 Jul 13 08:27:17 PM PDT 24 9919167420 ps
T127 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2140630680 Jul 13 07:54:16 PM PDT 24 Jul 13 08:04:27 PM PDT 24 7293979280 ps
T761 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.412004303 Jul 13 08:18:04 PM PDT 24 Jul 13 08:24:26 PM PDT 24 3503596400 ps
T755 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3034224039 Jul 13 08:13:22 PM PDT 24 Jul 13 08:20:41 PM PDT 24 4273292500 ps
T52 /workspace/coverage/default/2.rom_e2e_shutdown_output.1345952374 Jul 13 08:09:21 PM PDT 24 Jul 13 09:10:01 PM PDT 24 28758553196 ps
T904 /workspace/coverage/default/0.chip_sw_aes_entropy.1654800024 Jul 13 07:45:38 PM PDT 24 Jul 13 07:50:46 PM PDT 24 2647134012 ps
T792 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3752903342 Jul 13 08:15:18 PM PDT 24 Jul 13 08:22:54 PM PDT 24 3331657664 ps
T905 /workspace/coverage/default/1.chip_sw_uart_smoketest.374405771 Jul 13 07:57:14 PM PDT 24 Jul 13 08:01:22 PM PDT 24 2840726322 ps
T154 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3637477382 Jul 13 07:47:18 PM PDT 24 Jul 13 07:57:18 PM PDT 24 4455518712 ps
T388 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2896787769 Jul 13 08:19:23 PM PDT 24 Jul 13 08:27:50 PM PDT 24 4113835576 ps
T359 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.310700884 Jul 13 07:44:00 PM PDT 24 Jul 13 08:44:34 PM PDT 24 33837565076 ps
T87 /workspace/coverage/default/0.chip_sw_gpio_smoketest.3935470310 Jul 13 07:46:17 PM PDT 24 Jul 13 07:49:55 PM PDT 24 2600761030 ps
T315 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1341100383 Jul 13 08:09:22 PM PDT 24 Jul 13 08:19:58 PM PDT 24 4154990514 ps
T65 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1997075732 Jul 13 07:48:15 PM PDT 24 Jul 13 07:50:31 PM PDT 24 2921698591 ps
T125 /workspace/coverage/default/2.chip_sw_edn_auto_mode.3846041710 Jul 13 08:03:23 PM PDT 24 Jul 13 08:23:00 PM PDT 24 4795053172 ps
T179 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3931855252 Jul 13 07:59:58 PM PDT 24 Jul 13 09:00:44 PM PDT 24 14897951304 ps
T118 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2661212454 Jul 13 07:47:02 PM PDT 24 Jul 13 08:40:15 PM PDT 24 13646873958 ps
T906 /workspace/coverage/default/1.chip_sw_example_manufacturer.1696072745 Jul 13 07:52:55 PM PDT 24 Jul 13 07:58:16 PM PDT 24 2528668814 ps
T342 /workspace/coverage/default/99.chip_sw_all_escalation_resets.854981553 Jul 13 08:18:09 PM PDT 24 Jul 13 08:30:05 PM PDT 24 5498865288 ps
T58 /workspace/coverage/default/2.chip_jtag_mem_access.2244817693 Jul 13 07:57:22 PM PDT 24 Jul 13 08:23:13 PM PDT 24 13267246900 ps
T316 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3119068056 Jul 13 07:44:41 PM PDT 24 Jul 13 07:57:17 PM PDT 24 4914064984 ps
T731 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3197700780 Jul 13 08:10:08 PM PDT 24 Jul 13 08:18:22 PM PDT 24 3373907864 ps
T907 /workspace/coverage/default/2.chip_sw_aes_entropy.4247838740 Jul 13 08:01:56 PM PDT 24 Jul 13 08:06:08 PM PDT 24 2625967424 ps
T309 /workspace/coverage/default/1.chip_plic_all_irqs_20.3434438188 Jul 13 07:52:30 PM PDT 24 Jul 13 08:04:39 PM PDT 24 4154318662 ps
T259 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.4211426228 Jul 13 08:16:29 PM PDT 24 Jul 13 08:22:51 PM PDT 24 3907936086 ps
T182 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.529866447 Jul 13 07:49:58 PM PDT 24 Jul 13 07:57:10 PM PDT 24 5211708744 ps
T809 /workspace/coverage/default/11.chip_sw_all_escalation_resets.2797430264 Jul 13 08:09:42 PM PDT 24 Jul 13 08:23:44 PM PDT 24 5314938270 ps
T145 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3324032969 Jul 13 07:47:15 PM PDT 24 Jul 13 08:44:33 PM PDT 24 17419248896 ps
T209 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1406208397 Jul 13 07:45:07 PM PDT 24 Jul 13 07:49:17 PM PDT 24 3245889376 ps
T691 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2679792224 Jul 13 08:10:36 PM PDT 24 Jul 13 08:17:50 PM PDT 24 3728659636 ps
T333 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3091859397 Jul 13 08:02:15 PM PDT 24 Jul 13 08:14:45 PM PDT 24 5702770668 ps
T379 /workspace/coverage/default/2.rom_e2e_asm_init_dev.789990436 Jul 13 08:09:23 PM PDT 24 Jul 13 09:10:07 PM PDT 24 15793377960 ps
T212 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3304306025 Jul 13 08:00:07 PM PDT 24 Jul 13 08:53:17 PM PDT 24 12929938736 ps
T119 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.492894156 Jul 13 08:04:47 PM PDT 24 Jul 13 08:16:59 PM PDT 24 4483818568 ps
T908 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.445962578 Jul 13 07:45:46 PM PDT 24 Jul 13 07:51:04 PM PDT 24 2711568144 ps
T398 /workspace/coverage/default/0.rom_e2e_static_critical.2585489851 Jul 13 07:49:49 PM PDT 24 Jul 13 09:02:22 PM PDT 24 17632414136 ps
T339 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.690444166 Jul 13 07:46:20 PM PDT 24 Jul 13 07:49:59 PM PDT 24 3096412514 ps
T773 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2349763287 Jul 13 08:12:38 PM PDT 24 Jul 13 08:20:27 PM PDT 24 4545403072 ps
T64 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1717348594 Jul 13 08:09:58 PM PDT 24 Jul 13 08:31:20 PM PDT 24 12069893174 ps
T343 /workspace/coverage/default/81.chip_sw_all_escalation_resets.968883585 Jul 13 08:16:56 PM PDT 24 Jul 13 08:27:34 PM PDT 24 6089221480 ps
T115 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2931317068 Jul 13 07:46:31 PM PDT 24 Jul 13 08:04:05 PM PDT 24 6254504102 ps
T350 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3976379395 Jul 13 07:45:25 PM PDT 24 Jul 13 07:50:06 PM PDT 24 2837900167 ps
T156 /workspace/coverage/default/90.chip_sw_all_escalation_resets.697960434 Jul 13 08:18:42 PM PDT 24 Jul 13 08:29:22 PM PDT 24 4654416476 ps
T909 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.894597805 Jul 13 08:06:46 PM PDT 24 Jul 13 08:33:18 PM PDT 24 8189153134 ps
T910 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2743389129 Jul 13 07:46:21 PM PDT 24 Jul 13 07:54:25 PM PDT 24 3208895290 ps
T694 /workspace/coverage/default/76.chip_sw_all_escalation_resets.2400727488 Jul 13 08:17:09 PM PDT 24 Jul 13 08:28:52 PM PDT 24 4663010092 ps
T911 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.896324446 Jul 13 07:46:30 PM PDT 24 Jul 13 07:54:28 PM PDT 24 5946487062 ps
T399 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1001200924 Jul 13 07:52:46 PM PDT 24 Jul 13 08:45:59 PM PDT 24 10836505944 ps
T912 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.61739930 Jul 13 07:49:03 PM PDT 24 Jul 13 07:53:25 PM PDT 24 2852029304 ps
T404 /workspace/coverage/default/30.chip_sw_all_escalation_resets.4286293789 Jul 13 08:12:42 PM PDT 24 Jul 13 08:21:32 PM PDT 24 4501360880 ps
T380 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2539277841 Jul 13 08:11:55 PM PDT 24 Jul 13 09:38:33 PM PDT 24 15430661792 ps
T344 /workspace/coverage/default/93.chip_sw_all_escalation_resets.2119179117 Jul 13 08:16:52 PM PDT 24 Jul 13 08:26:53 PM PDT 24 4864696040 ps
T3 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2179774929 Jul 13 07:45:09 PM PDT 24 Jul 13 07:52:10 PM PDT 24 7162078990 ps
T30 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2163049362 Jul 13 08:01:56 PM PDT 24 Jul 13 08:28:32 PM PDT 24 21507512358 ps
T183 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3299323025 Jul 13 08:10:06 PM PDT 24 Jul 13 08:23:50 PM PDT 24 10272809820 ps
T425 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2114559353 Jul 13 08:07:24 PM PDT 24 Jul 13 08:13:36 PM PDT 24 2324605923 ps
T426 /workspace/coverage/default/2.chip_sw_example_rom.2030470310 Jul 13 07:56:43 PM PDT 24 Jul 13 07:58:58 PM PDT 24 2960874858 ps
T400 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2819034836 Jul 13 08:03:29 PM PDT 24 Jul 13 08:24:21 PM PDT 24 5504392824 ps
T159 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2032123878 Jul 13 07:43:45 PM PDT 24 Jul 13 09:23:29 PM PDT 24 48181938779 ps
T427 /workspace/coverage/default/87.chip_sw_all_escalation_resets.2605482744 Jul 13 08:17:24 PM PDT 24 Jul 13 08:26:29 PM PDT 24 4961791352 ps
T356 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.46752485 Jul 13 08:01:35 PM PDT 24 Jul 13 08:08:16 PM PDT 24 4043299822 ps
T323 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3672670376 Jul 13 08:09:52 PM PDT 24 Jul 13 08:39:14 PM PDT 24 8706760800 ps
T253 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.83163348 Jul 13 08:08:48 PM PDT 24 Jul 13 08:15:14 PM PDT 24 3740041062 ps
T827 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2848624276 Jul 13 08:17:12 PM PDT 24 Jul 13 08:23:23 PM PDT 24 3892846248 ps
T155 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2418746253 Jul 13 08:00:30 PM PDT 24 Jul 13 08:28:11 PM PDT 24 12817774796 ps
T88 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.2014377868 Jul 13 07:58:55 PM PDT 24 Jul 13 11:08:03 PM PDT 24 65431796908 ps
T338 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.361556363 Jul 13 07:47:14 PM PDT 24 Jul 13 07:56:34 PM PDT 24 3938685764 ps
T8 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1419799343 Jul 13 08:05:40 PM PDT 24 Jul 13 08:09:53 PM PDT 24 2839488280 ps
T166 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1091957750 Jul 13 07:47:05 PM PDT 24 Jul 13 09:27:37 PM PDT 24 50032410628 ps
T204 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.482579395 Jul 13 08:01:03 PM PDT 24 Jul 13 08:05:39 PM PDT 24 3414787684 ps
T252 /workspace/coverage/default/2.chip_sw_plic_sw_irq.3193988836 Jul 13 08:04:38 PM PDT 24 Jul 13 08:11:39 PM PDT 24 3114610746 ps
T423 /workspace/coverage/default/1.rom_e2e_asm_init_rma.2296593708 Jul 13 08:06:17 PM PDT 24 Jul 13 09:06:33 PM PDT 24 14993765988 ps
T171 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3540201942 Jul 13 08:03:50 PM PDT 24 Jul 13 08:16:21 PM PDT 24 4254249120 ps
T146 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1566321015 Jul 13 08:03:00 PM PDT 24 Jul 13 09:08:51 PM PDT 24 16564300256 ps
T70 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3324345633 Jul 13 07:52:50 PM PDT 24 Jul 13 07:58:57 PM PDT 24 5751050080 ps
T136 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2582990819 Jul 13 08:11:52 PM PDT 24 Jul 13 08:17:52 PM PDT 24 4276856984 ps
T276 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3563471951 Jul 13 07:45:24 PM PDT 24 Jul 13 07:52:12 PM PDT 24 5679509076 ps
T242 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1899270424 Jul 13 07:45:07 PM PDT 24 Jul 13 07:51:49 PM PDT 24 3776966430 ps
T277 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.359091346 Jul 13 08:02:02 PM PDT 24 Jul 13 08:17:11 PM PDT 24 7182353880 ps
T278 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1140698254 Jul 13 08:13:25 PM PDT 24 Jul 13 09:21:30 PM PDT 24 15380173066 ps
T279 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1172812126 Jul 13 07:51:41 PM PDT 24 Jul 13 07:56:55 PM PDT 24 3434957743 ps
T25 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2414318175 Jul 13 07:48:41 PM PDT 24 Jul 13 08:02:08 PM PDT 24 5205884419 ps
T214 /workspace/coverage/default/2.chip_sw_pattgen_ios.2559872059 Jul 13 08:04:56 PM PDT 24 Jul 13 08:09:21 PM PDT 24 2679857826 ps
T810 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1760238471 Jul 13 08:14:09 PM PDT 24 Jul 13 08:22:44 PM PDT 24 3595088704 ps
T306 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.96478544 Jul 13 07:48:49 PM PDT 24 Jul 13 08:23:30 PM PDT 24 27173511238 ps
T913 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3245898102 Jul 13 08:07:37 PM PDT 24 Jul 13 08:16:53 PM PDT 24 7856262792 ps
T199 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3170674692 Jul 13 07:59:02 PM PDT 24 Jul 14 12:00:16 AM PDT 24 79058258776 ps
T790 /workspace/coverage/default/44.chip_sw_all_escalation_resets.1790380952 Jul 13 08:13:16 PM PDT 24 Jul 13 08:25:25 PM PDT 24 4632787480 ps
T734 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.787086809 Jul 13 08:11:23 PM PDT 24 Jul 13 08:19:47 PM PDT 24 3621187880 ps
T914 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2245080529 Jul 13 08:00:59 PM PDT 24 Jul 13 08:23:30 PM PDT 24 6121353165 ps
T116 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4141287913 Jul 13 08:05:04 PM PDT 24 Jul 13 08:35:36 PM PDT 24 11501896051 ps
T234 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2127159088 Jul 13 08:01:59 PM PDT 24 Jul 13 09:26:58 PM PDT 24 45504369200 ps
T347 /workspace/coverage/default/6.chip_sw_all_escalation_resets.2280978865 Jul 13 08:12:08 PM PDT 24 Jul 13 08:23:12 PM PDT 24 5516443200 ps
T448 /workspace/coverage/default/2.chip_sw_kmac_entropy.3036961571 Jul 13 07:59:34 PM PDT 24 Jul 13 08:02:54 PM PDT 24 2110355922 ps
T224 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2727461480 Jul 13 08:04:19 PM PDT 24 Jul 13 08:46:09 PM PDT 24 13458516000 ps
T915 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3974118587 Jul 13 08:11:15 PM PDT 24 Jul 13 08:37:40 PM PDT 24 8206955404 ps
T362 /workspace/coverage/default/1.chip_sw_hmac_enc.909195705 Jul 13 07:54:45 PM PDT 24 Jul 13 07:58:59 PM PDT 24 3303123670 ps
T916 /workspace/coverage/default/49.chip_sw_all_escalation_resets.3559660200 Jul 13 08:14:53 PM PDT 24 Jul 13 08:27:40 PM PDT 24 5227040864 ps
T385 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.4180384761 Jul 13 07:49:06 PM PDT 24 Jul 13 09:38:45 PM PDT 24 24866411464 ps
T917 /workspace/coverage/default/1.rom_e2e_smoke.2058627783 Jul 13 08:00:22 PM PDT 24 Jul 13 09:05:56 PM PDT 24 15022505400 ps
T269 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2780797804 Jul 13 08:08:32 PM PDT 24 Jul 13 08:22:11 PM PDT 24 5162251384 ps
T341 /workspace/coverage/default/0.chip_sw_pattgen_ios.113514950 Jul 13 07:45:55 PM PDT 24 Jul 13 07:51:19 PM PDT 24 2531753472 ps
T918 /workspace/coverage/default/1.chip_sw_aes_enc.706108978 Jul 13 07:49:06 PM PDT 24 Jul 13 07:53:55 PM PDT 24 3465142072 ps
T223 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2653791381 Jul 13 07:47:49 PM PDT 24 Jul 13 08:57:39 PM PDT 24 13452698328 ps
T365 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3326173453 Jul 13 08:14:02 PM PDT 24 Jul 13 08:22:15 PM PDT 24 3650220344 ps
T371 /workspace/coverage/default/58.chip_sw_all_escalation_resets.531760966 Jul 13 08:14:37 PM PDT 24 Jul 13 08:26:14 PM PDT 24 6135483000 ps
T120 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2818245843 Jul 13 07:53:44 PM PDT 24 Jul 13 08:06:32 PM PDT 24 4916942314 ps
T372 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.269033287 Jul 13 07:43:38 PM PDT 24 Jul 13 07:48:49 PM PDT 24 2863422120 ps
T345 /workspace/coverage/default/85.chip_sw_all_escalation_resets.2754562037 Jul 13 08:19:19 PM PDT 24 Jul 13 08:32:56 PM PDT 24 5495437764 ps
T167 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.581603759 Jul 13 07:59:32 PM PDT 24 Jul 13 09:27:18 PM PDT 24 43773325500 ps
T151 /workspace/coverage/default/1.chip_plic_all_irqs_10.344163414 Jul 13 07:51:40 PM PDT 24 Jul 13 08:01:51 PM PDT 24 4150087386 ps
T53 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3737651267 Jul 13 07:50:44 PM PDT 24 Jul 13 09:31:35 PM PDT 24 23611325525 ps
T373 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3173075696 Jul 13 08:00:50 PM PDT 24 Jul 13 08:10:03 PM PDT 24 4622629448 ps
T374 /workspace/coverage/default/5.chip_sw_all_escalation_resets.3714514425 Jul 13 08:08:44 PM PDT 24 Jul 13 08:21:34 PM PDT 24 5582285788 ps
T121 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.672869646 Jul 13 07:52:36 PM PDT 24 Jul 13 08:03:18 PM PDT 24 4245563192 ps
T240 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.265786606 Jul 13 08:00:09 PM PDT 24 Jul 13 09:36:43 PM PDT 24 49538182975 ps
T807 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.414324327 Jul 13 08:16:25 PM PDT 24 Jul 13 08:22:18 PM PDT 24 4251467416 ps
T227 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3719005807 Jul 13 07:43:56 PM PDT 24 Jul 13 08:06:42 PM PDT 24 7330840728 ps
T919 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1205499743 Jul 13 08:11:17 PM PDT 24 Jul 13 09:12:04 PM PDT 24 15597186376 ps
T270 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.225369456 Jul 13 08:06:26 PM PDT 24 Jul 13 08:16:08 PM PDT 24 5938591700 ps
T920 /workspace/coverage/default/2.chip_sw_aes_enc.1192237892 Jul 13 08:01:58 PM PDT 24 Jul 13 08:07:01 PM PDT 24 3130311618 ps
T921 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3874614845 Jul 13 08:07:14 PM PDT 24 Jul 13 08:12:38 PM PDT 24 2638277640 ps
T692 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3208478525 Jul 13 08:13:59 PM PDT 24 Jul 13 08:20:44 PM PDT 24 4218384848 ps
T257 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2724921164 Jul 13 07:44:34 PM PDT 24 Jul 13 09:55:09 PM PDT 24 35979421436 ps
T922 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2428526743 Jul 13 07:50:30 PM PDT 24 Jul 13 08:56:47 PM PDT 24 15054200936 ps
T923 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3217724718 Jul 13 08:03:53 PM PDT 24 Jul 13 08:24:33 PM PDT 24 14149435884 ps
T71 /workspace/coverage/default/0.chip_tap_straps_testunlock0.1655876688 Jul 13 07:46:05 PM PDT 24 Jul 13 07:50:54 PM PDT 24 3724895383 ps
T63 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3005418755 Jul 13 07:42:54 PM PDT 24 Jul 13 07:50:27 PM PDT 24 3231700270 ps
T781 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2908977403 Jul 13 08:18:26 PM PDT 24 Jul 13 08:26:34 PM PDT 24 4231046362 ps
T54 /workspace/coverage/default/0.rom_e2e_shutdown_output.3107746186 Jul 13 07:48:36 PM PDT 24 Jul 13 08:44:47 PM PDT 24 26522859577 ps
T765 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.918911326 Jul 13 08:17:49 PM PDT 24 Jul 13 08:23:19 PM PDT 24 3904074800 ps
T924 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2668120909 Jul 13 07:58:27 PM PDT 24 Jul 13 08:06:19 PM PDT 24 6160050074 ps
T169 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.423890903 Jul 13 07:59:35 PM PDT 24 Jul 13 08:03:36 PM PDT 24 3533041773 ps
T925 /workspace/coverage/default/2.chip_sw_hmac_oneshot.303669058 Jul 13 08:02:58 PM PDT 24 Jul 13 08:08:48 PM PDT 24 3487778840 ps
T749 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3312478988 Jul 13 08:11:47 PM PDT 24 Jul 13 08:17:39 PM PDT 24 4406211728 ps
T231 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1902657514 Jul 13 07:43:28 PM PDT 24 Jul 13 08:31:27 PM PDT 24 12672028752 ps
T174 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1832379181 Jul 13 07:46:38 PM PDT 24 Jul 13 08:03:28 PM PDT 24 8623010062 ps
T236 /workspace/coverage/default/1.chip_sw_flash_init.4024556038 Jul 13 07:45:39 PM PDT 24 Jul 13 08:20:39 PM PDT 24 23909787650 ps
T298 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2714243682 Jul 13 07:45:48 PM PDT 24 Jul 13 09:07:33 PM PDT 24 25577834079 ps
T140 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.719286317 Jul 13 07:51:26 PM PDT 24 Jul 13 07:56:10 PM PDT 24 2887651578 ps
T299 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3337392293 Jul 13 07:44:39 PM PDT 24 Jul 13 07:57:06 PM PDT 24 4959962504 ps
T300 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3443845616 Jul 13 08:15:04 PM PDT 24 Jul 13 08:22:37 PM PDT 24 3782155368 ps
T301 /workspace/coverage/default/2.rom_keymgr_functest.650906396 Jul 13 08:05:50 PM PDT 24 Jul 13 08:13:38 PM PDT 24 4875311500 ps
T302 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3801152592 Jul 13 08:05:19 PM PDT 24 Jul 13 08:15:20 PM PDT 24 6968244170 ps
T46 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.697149651 Jul 13 07:47:57 PM PDT 24 Jul 13 07:54:57 PM PDT 24 5962069928 ps
T303 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1863325065 Jul 13 07:49:09 PM PDT 24 Jul 13 09:36:04 PM PDT 24 24587922332 ps
T926 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1947869473 Jul 13 07:45:58 PM PDT 24 Jul 13 07:49:06 PM PDT 24 3311273925 ps
T927 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.601793084 Jul 13 08:04:39 PM PDT 24 Jul 13 08:10:10 PM PDT 24 3082368874 ps
T226 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3340284640 Jul 13 07:43:43 PM PDT 24 Jul 13 07:52:55 PM PDT 24 5313573500 ps
T928 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2090547813 Jul 13 08:11:37 PM PDT 24 Jul 13 08:20:03 PM PDT 24 6582366298 ps
T929 /workspace/coverage/default/61.chip_sw_all_escalation_resets.2252986421 Jul 13 08:15:08 PM PDT 24 Jul 13 08:27:55 PM PDT 24 6195101004 ps
T213 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.381869817 Jul 13 08:06:16 PM PDT 24 Jul 13 08:15:11 PM PDT 24 3847450580 ps
T806 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2073494689 Jul 13 08:14:48 PM PDT 24 Jul 13 08:22:17 PM PDT 24 4005842424 ps
T930 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1006202371 Jul 13 08:12:58 PM PDT 24 Jul 13 08:23:28 PM PDT 24 4344575770 ps
T310 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2157803642 Jul 13 07:42:58 PM PDT 24 Jul 13 07:53:46 PM PDT 24 4476213222 ps
T931 /workspace/coverage/default/2.rom_e2e_asm_init_prod.46406137 Jul 13 08:13:18 PM PDT 24 Jul 13 09:16:15 PM PDT 24 15191505618 ps
T932 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3923762681 Jul 13 07:50:57 PM PDT 24 Jul 13 09:07:09 PM PDT 24 15239770880 ps
T933 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.2385295742 Jul 13 07:46:02 PM PDT 24 Jul 13 07:50:53 PM PDT 24 3199959400 ps
T340 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.578928673 Jul 13 07:59:31 PM PDT 24 Jul 13 08:11:00 PM PDT 24 4176975669 ps
T84 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.1515559621 Jul 13 07:48:40 PM PDT 24 Jul 13 07:54:31 PM PDT 24 3390833508 ps
T934 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3836589672 Jul 13 08:05:41 PM PDT 24 Jul 13 08:20:49 PM PDT 24 5005671913 ps
T935 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3054801166 Jul 13 08:00:46 PM PDT 24 Jul 13 09:07:23 PM PDT 24 14472674060 ps
T936 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1449171557 Jul 13 07:50:48 PM PDT 24 Jul 13 08:42:04 PM PDT 24 34402733976 ps
T110 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2484117692 Jul 13 07:49:00 PM PDT 24 Jul 13 07:56:24 PM PDT 24 18390047864 ps
T937 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2968073772 Jul 13 07:52:36 PM PDT 24 Jul 13 08:03:31 PM PDT 24 4277268708 ps
T218 /workspace/coverage/default/2.chip_tap_straps_prod.2970113208 Jul 13 08:05:16 PM PDT 24 Jul 13 08:07:32 PM PDT 24 2354570986 ps
T938 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.773166568 Jul 13 07:55:26 PM PDT 24 Jul 13 08:00:18 PM PDT 24 3641653929 ps
T271 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.4270753373 Jul 13 07:47:53 PM PDT 24 Jul 13 07:55:37 PM PDT 24 3171135750 ps
T939 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.681078965 Jul 13 08:11:07 PM PDT 24 Jul 13 08:30:15 PM PDT 24 10003958059 ps
T940 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.891272185 Jul 13 08:02:50 PM PDT 24 Jul 13 08:08:56 PM PDT 24 3464790106 ps
T941 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.851833670 Jul 13 07:51:25 PM PDT 24 Jul 13 07:57:44 PM PDT 24 4488190264 ps
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