Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3424	1			T126	1		T250	4		T430	4
all_values[1]	3428	1			T251	41		T429	13		T450	2
all_values[2]	3471	1			T250	1		T430	1		T251	29
all_values[3]	3444	1			T250	1		T430	7		T251	25
all_values[4]	3442	1			T126	1		T250	3		T251	28
all_values[5]	3478	1			T250	2		T430	3		T251	26
all_values[6]	3484	1			T250	2		T430	2		T251	30
all_values[7]	3452	1			T250	2		T251	25		T429	9
all_values[8]	3429	1			T250	1		T430	1		T251	34
all_values[9]	3521	1			T250	2		T430	1		T251	34
all_values[10]	3441	1			T250	2		T430	2		T251	30
all_values[11]	3409	1			T250	7		T430	2		T251	30
all_values[12]	3394	1			T126	1		T430	1		T251	26
all_values[13]	3436	1			T126	1		T250	2		T430	1
all_values[14]	3303	1			T250	1		T251	22		T429	14
all_values[15]	3346	1			T126	1		T250	1		T430	2
all_values[16]	3463	1			T250	1		T430	4		T251	27
all_values[17]	3450	1			T430	2		T251	22		T429	21
all_values[18]	3415	1			T126	1		T250	2		T430	1
all_values[19]	3595	1			T126	2		T430	2		T251	25
all_values[20]	3422	1			T250	1		T251	25		T429	9
all_values[21]	3493	1			T250	4		T251	26		T429	12
all_values[22]	3514	1			T250	1		T430	2		T251	29
all_values[23]	3466	1			T250	2		T430	2		T251	23
all_values[24]	3493	1			T250	1		T430	1		T251	19
all_values[25]	3491	1			T250	3		T430	2		T251	18
all_values[26]	3424	1			T126	1		T250	3		T430	1
all_values[27]	3460	1			T250	2		T251	17		T429	25
all_values[28]	3523	1			T250	3		T430	2		T251	19
all_values[29]	3404	1			T430	3		T251	17		T429	15
all_values[30]	3399	1			T126	1		T250	2		T430	2
all_values[31]	3496	1			T250	1		T251	24		T429	16
all_values[32]	3355	1			T250	3		T430	2		T251	21
all_values[33]	3475	1			T250	2		T430	2		T251	27
all_values[34]	3449	1			T126	2		T250	1		T430	3
all_values[35]	3517	1			T250	3		T430	1		T251	38
all_values[36]	3438	1			T250	4		T430	1		T251	28
all_values[37]	3424	1			T430	1		T251	23		T429	20
all_values[38]	3536	1			T430	1		T251	25		T429	15
all_values[39]	3410	1			T430	2		T251	30		T429	24
all_values[40]	3393	1			T430	1		T251	29		T429	17
all_values[41]	3558	1			T126	1		T430	2		T251	28
all_values[42]	3615	1			T126	1		T251	20		T429	17
all_values[43]	3465	1			T250	1		T430	3		T251	31
all_values[44]	3463	1			T126	1		T250	5		T430	2
all_values[45]	3436	1			T126	2		T430	2		T251	22
all_values[46]	3524	1			T250	1		T430	1		T251	26
all_values[47]	3548	1			T126	1		T250	3		T251	28
all_values[48]	3388	1			T250	2		T430	1		T251	26
all_values[49]	3399	1			T126	1		T250	1		T430	3
all_values[50]	3456	1			T250	2		T430	2		T251	22
all_values[51]	3475	1			T126	2		T250	2		T430	3
all_values[52]	3364	1			T250	2		T251	24		T429	9
all_values[53]	3398	1			T126	1		T250	1		T430	1
all_values[54]	3568	1			T250	1		T430	2		T251	24
all_values[55]	3455	1			T126	1		T251	36		T429	13
all_values[56]	3378	1			T126	1		T250	1		T251	20
all_values[57]	3502	1			T430	1		T251	24		T429	17
all_values[58]	3409	1			T126	1		T250	2		T251	30
all_values[59]	3505	1			T250	3		T430	1		T251	17
all_values[60]	3468	1			T251	31		T429	15		T588	11
all_values[61]	3369	1			T126	1		T250	1		T430	2
all_values[62]	3596	1			T126	1		T250	2		T251	33
all_values[63]	3463	1			T250	1		T430	3		T251	25