Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	153650	1			T85	96		T86	48		T89	3
values[2]	3948	1			T85	2		T86	2		T486	7
values[3]	1806	1			T547	1		T551	1		T835	1
values[4]	1319	1			T547	1		T551	1		T835	1
values[5]	1105	1			T547	1		T551	1		T835	1
values[6]	1128	1			T547	1		T551	1		T835	1
values[7]	942	1			T547	1		T551	1		T835	1
values[8]	759	1			T547	1		T551	1		T835	1
values[9]	672	1			T547	1		T551	1		T835	1
values[10]	596	1			T547	1		T551	1		T835	1
values[11]	563	1			T547	1		T551	1		T835	1
values[12]	505	1			T547	1		T551	1		T835	1
values[13]	433	1			T547	2		T551	1		T835	1
values[14]	403	1			T547	1		T551	1		T835	1
values[15]	425	1			T547	1		T551	1		T835	1
values[16]	372	1			T547	1		T551	1		T835	1
values[17]	323	1			T547	1		T551	1		T835	1
values[18]	290	1			T547	1		T551	1		T835	1
values[19]	228	1			T547	1		T551	1		T835	1
values[20]	220	1			T547	1		T551	1		T835	1
values[21]	197	1			T547	1		T551	1		T835	1
values[22]	213	1			T547	1		T551	1		T835	1
values[23]	227	1			T547	1		T551	1		T835	1
values[24]	220	1			T547	1		T551	1		T835	1
values[25]	180	1			T547	1		T551	2		T835	1
values[26]	201	1			T547	1		T551	1		T835	1
values[27]	171	1			T547	1		T551	1		T835	1
values[28]	143	1			T547	1		T551	1		T835	1
values[29]	114	1			T547	1		T551	1		T835	1
values[30]	114	1			T547	1		T551	1		T835	1
values[31]	107	1			T547	1		T551	1		T835	1
values[32]	136	1			T547	1		T551	1		T835	1
values[33]	121	1			T547	1		T551	1		T835	1
values[34]	106	1			T547	1		T551	1		T835	1
values[35]	104	1			T547	1		T551	1		T835	1
values[36]	83	1			T547	1		T551	1		T835	1
values[37]	91	1			T547	1		T551	1		T835	1
values[38]	89	1			T547	1		T551	1		T835	1
values[39]	97	1			T547	1		T551	1		T835	1
values[40]	97	1			T547	1		T551	1		T835	1
values[41]	141	1			T547	1		T551	1		T835	1
values[42]	115	1			T547	1		T551	1		T835	1
values[43]	71	1			T547	1		T551	1		T835	1
values[44]	64	1			T547	1		T551	1		T835	1
values[45]	75	1			T547	1		T551	1		T835	1
values[46]	86	1			T547	1		T551	1		T835	1
values[47]	95	1			T547	1		T551	1		T835	1
values[48]	74	1			T547	1		T551	1		T835	1
values[49]	77	1			T547	1		T551	1		T835	1
values[50]	67	1			T547	1		T551	1		T835	1
values[51]	66	1			T547	1		T551	1		T835	1
values[52]	51	1			T547	1		T551	1		T835	1
values[53]	47	1			T547	1		T551	1		T835	1
values[54]	41	1			T547	1		T551	1		T835	1
values[55]	44	1			T547	1		T551	1		T835	1
values[56]	39	1			T547	1		T551	1		T835	1
values[57]	47	1			T547	1		T551	1		T835	1
values[58]	54	1			T547	1		T551	1		T835	1
values[59]	61	1			T547	1		T551	1		T835	1
values[60]	42	1			T547	1		T551	1		T835	1
values[61]	40	1			T547	1		T551	1		T835	1
values[62]	40	1			T547	2		T551	1		T835	1
values[63]	39	1			T547	1		T551	1		T835	1
values[64]	57	1			T547	1		T551	1		T835	1
values[65]	47	1			T547	1		T551	1		T835	1
values[66]	50	1			T547	1		T551	1		T835	1
values[67]	48	1			T547	1		T551	1		T835	1
values[68]	40	1			T547	1		T551	1		T835	1
values[69]	46	1			T547	1		T551	1		T835	1
values[70]	45	1			T547	1		T551	1		T835	1
values[71]	54	1			T547	1		T551	1		T835	1
values[72]	43	1			T547	1		T551	1		T835	1
values[73]	39	1			T547	1		T551	1		T835	1
values[74]	46	1			T547	1		T551	5		T835	1
values[75]	53	1			T547	1		T551	6		T835	1
values[76]	48	1			T547	1		T551	1		T835	1
values[77]	53	1			T547	1		T551	2		T835	1
values[78]	60	1			T547	1		T551	3		T835	1
values[79]	52	1			T547	1		T551	6		T835	1
values[80]	54	1			T547	1		T551	1		T835	1
values[81]	64	1			T547	1		T551	4		T835	1
values[82]	60	1			T547	1		T551	4		T835	1
values[83]	63	1			T547	1		T551	8		T835	1
values[84]	54	1			T547	1		T551	3		T835	1
values[85]	46	1			T547	1		T551	1		T835	1
values[86]	56	1			T547	1		T551	6		T835	1
values[87]	63	1			T547	1		T551	8		T835	2
values[88]	58	1			T547	1		T551	3		T835	1
values[89]	77	1			T547	1		T551	5		T835	1
values[90]	69	1			T547	1		T551	3		T835	1
values[91]	81	1			T547	1		T551	4		T835	1
values[92]	75	1			T547	1		T551	2		T835	1
values[93]	70	1			T547	1		T551	3		T835	1
values[94]	65	1			T547	1		T551	2		T835	1
values[95]	65	1			T547	1		T551	4		T835	1
values[96]	80	1			T547	1		T551	1		T835	1
values[97]	63	1			T547	1		T551	1		T835	1
values[98]	67	1			T547	1		T551	3		T835	1
values[99]	73	1			T547	1		T551	2		T835	1
values[100]	75	1			T547	2		T551	2		T835	1
values[101]	69	1			T547	3		T551	3		T835	1
values[102]	85	1			T547	2		T551	1		T835	1
values[103]	83	1			T547	2		T551	3		T835	1
values[104]	78	1			T547	1		T551	1		T835	1
values[105]	82	1			T547	1		T551	2		T835	1
values[106]	75	1			T547	5		T551	3		T835	1
values[107]	79	1			T547	2		T551	2		T835	1
values[108]	61	1			T547	1		T551	1		T835	1
values[109]	66	1			T547	1		T551	1		T835	1
values[110]	61	1			T547	1		T551	2		T835	1
values[111]	67	1			T547	1		T551	1		T835	1
values[112]	76	1			T547	1		T551	1		T835	1
values[113]	84	1			T547	1		T551	3		T835	1
values[114]	82	1			T547	2		T551	2		T835	4
values[115]	100	1			T547	4		T551	3		T835	3
values[116]	92	1			T547	3		T551	5		T835	2
values[117]	87	1			T547	2		T551	3		T835	5
values[118]	83	1			T547	2		T551	3		T835	1
values[119]	68	1			T547	1		T551	1		T835	1
values[120]	88	1			T547	2		T551	5		T835	1
values[121]	85	1			T547	1		T551	5		T835	1
values[122]	73	1			T547	1		T551	1		T835	2
values[123]	122	1			T547	2		T551	1		T835	4
values[124]	225	1			T547	4		T551	1		T835	1
values[125]	419	1			T547	1		T551	1		T835	5
values[126]	713	1			T547	20		T551	9		T835	16
values[127]	2533	1			T547	125		T551	90		T835	127
values[128]	4207	1			T547	260		T551	170		T835	248