Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.01	95.41	93.61	95.49		94.41	97.53	99.60

Total tests in report: 2907

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.73	39.73	44.20	44.20	42.81	42.81	34.51	34.51			57.58	57.58	59.09	59.09	0.19	0.19	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1194275139
48.22	8.49	49.32	5.12	53.63	10.82	35.05	0.54			65.70	8.11	84.27	25.17	1.36	1.17	/workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.2558148662
55.45	7.23	55.61	6.28	60.29	6.66	40.61	5.56			67.61	1.91	84.27	0.00	24.34	22.98	/workspace/coverage/cover_reg_top/93.xbar_stress_all.2817473740
60.77	5.32	67.04	11.43	68.15	7.86	42.67	2.06			78.17	10.56	84.27	0.00	24.34	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.43434633
64.63	3.86	72.68	5.64	68.17	0.02	43.76	1.10			78.17	0.00	84.27	0.00	40.75	16.40	/workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1834119023
68.13	3.50	72.68	0.00	68.46	0.29	43.76	0.00			78.33	0.15	84.27	0.00	61.30	20.55	/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1066642283
71.63	3.50	78.77	6.09	72.83	4.37	47.72	3.95			80.35	2.02	88.81	4.55	61.30	0.00	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3221052529
74.17	2.54	78.77	0.00	72.83	0.00	62.92	15.21			80.35	0.00	88.81	0.00	61.34	0.05	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3555013652
76.46	2.29	81.04	2.27	75.53	2.70	69.43	6.51			82.24	1.89	89.16	0.35	61.34	0.00	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.4056693713
78.23	1.78	81.04	0.00	75.53	0.00	69.43	0.00			82.24	0.00	89.16	0.00	72.00	10.66	/workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.2271108260
79.97	1.73	81.04	0.00	75.65	0.12	69.45	0.02			82.24	0.00	89.16	0.00	82.26	10.26	/workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.3608663129
81.67	1.70	83.80	2.75	79.27	3.62	69.72	0.28			85.63	3.39	89.34	0.17	82.26	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2833892275
82.87	1.20	83.80	0.00	79.27	0.00	76.93	7.21			85.63	0.00	89.34	0.00	82.26	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2061202962
83.93	1.06	84.91	1.12	79.95	0.68	79.62	2.69			86.62	0.99	90.21	0.87	82.27	0.01	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3861261542
84.94	1.00	86.13	1.21	81.14	1.19	81.70	2.08			87.71	1.09	90.38	0.17	82.54	0.27	/workspace/coverage/default/2.chip_jtag_csr_rw.2655452295
85.79	0.85	86.86	0.73	81.41	0.27	81.72	0.01			87.98	0.27	94.23	3.85	82.54	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3566440537
86.55	0.76	87.74	0.88	82.02	0.61	82.55	0.83			88.64	0.67	95.80	1.57	82.54	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4111518400
87.30	0.75	88.89	1.15	82.98	0.96	83.81	1.26			89.76	1.12	95.80	0.00	82.54	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2724990830
88.02	0.72	88.89	0.00	83.02	0.04	83.81	0.00			89.76	0.00	95.80	0.00	86.81	4.27	/workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1331367063
88.68	0.66	89.95	1.06	83.76	0.74	84.60	0.79			90.85	1.09	95.98	0.17	86.95	0.14	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1911399206
89.29	0.61	90.75	0.80	85.47	1.72	84.92	0.32			91.57	0.72	95.98	0.00	87.02	0.07	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.74717502
89.86	0.57	91.50	0.75	85.60	0.13	86.60	1.68			91.60	0.03	95.98	0.00	87.86	0.85	/workspace/coverage/cover_reg_top/36.xbar_error_random.2784455555
90.40	0.54	91.88	0.37	85.83	0.23	87.77	1.17			91.75	0.15	95.98	0.00	89.19	1.33	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3439747470
90.90	0.51	91.88	0.00	85.83	0.00	87.77	0.00			91.75	0.00	95.98	0.00	92.22	3.03	/workspace/coverage/cover_reg_top/89.xbar_access_same_device.1451172724
91.36	0.45	92.66	0.79	86.69	0.86	88.13	0.36			92.47	0.72	95.98	0.00	92.22	0.00	/workspace/coverage/default/2.chip_sw_gpio.3014484173
91.74	0.38	93.06	0.40	87.17	0.48	89.05	0.92			92.93	0.46	95.98	0.00	92.22	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.3164581107
92.10	0.37	93.07	0.01	88.94	1.78	89.05	0.00			92.93	0.00	95.98	0.00	92.63	0.41	/workspace/coverage/cover_reg_top/15.chip_tl_errors.1811795831
92.39	0.29	93.07	0.00	89.11	0.17	89.05	0.00			92.97	0.03	95.98	0.00	94.17	1.54	/workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1929778747
92.64	0.25	93.07	0.00	89.16	0.05	89.05	0.00			92.97	0.01	95.98	0.00	95.59	1.42	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.868374718
92.87	0.23	93.07	0.00	89.16	0.00	89.05	0.00			92.97	0.00	95.98	0.00	97.00	1.41	/workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.982957484
93.08	0.21	93.07	0.00	89.16	0.00	90.31	1.26			92.97	0.00	95.98	0.00	97.00	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.194897474
93.26	0.18	93.13	0.06	89.16	0.00	91.33	1.02			92.97	0.00	95.98	0.00	97.00	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.172699660
93.43	0.16	93.20	0.07	89.58	0.42	91.39	0.06			93.40	0.42	95.98	0.00	97.00	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.33503415
93.58	0.15	93.25	0.05	89.64	0.06	91.78	0.39			93.40	0.00	95.98	0.00	97.42	0.41	/workspace/coverage/default/1.chip_sw_alert_test.1683264292
93.71	0.13	93.29	0.04	89.71	0.07	92.41	0.63			93.44	0.05	95.98	0.00	97.42	0.00	/workspace/coverage/default/51.chip_sw_all_escalation_resets.1360355363
93.83	0.12	93.55	0.26	89.87	0.16	92.42	0.01			93.55	0.11	96.15	0.17	97.43	0.01	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3221489933
93.94	0.11	93.70	0.15	89.93	0.06	92.82	0.40			93.59	0.04	96.15	0.00	97.43	0.00	/workspace/coverage/default/0.rom_e2e_shutdown_output.3335521682
94.04	0.11	93.70	0.00	89.95	0.02	92.82	0.00			93.59	0.00	96.15	0.00	98.05	0.62	/workspace/coverage/cover_reg_top/39.xbar_random_large_delays.1101213079
94.15	0.10	93.77	0.07	90.10	0.14	92.84	0.02			93.63	0.04	96.50	0.35	98.05	0.00	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.871021089
94.25	0.10	93.77	0.00	90.71	0.61	92.84	0.00			93.63	0.00	96.50	0.00	98.05	0.00	/workspace/coverage/cover_reg_top/25.chip_tl_errors.2021726901
94.35	0.10	93.93	0.17	90.98	0.26	93.01	0.17			93.63	0.00	96.50	0.00	98.05	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3452877499
94.43	0.08	93.94	0.01	91.19	0.21	93.01	0.00			93.87	0.24	96.50	0.00	98.05	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.35825406
94.50	0.07	93.94	0.00	91.19	0.00	93.44	0.43			93.87	0.00	96.50	0.00	98.05	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.939137310
94.56	0.06	94.01	0.07	91.38	0.19	93.44	0.00			94.00	0.12	96.50	0.00	98.05	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3671360134
94.62	0.05	94.06	0.06	91.44	0.06	93.44	0.01			94.03	0.03	96.68	0.17	98.05	0.00	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2238006685
94.67	0.05	94.06	0.00	91.75	0.31	93.44	0.00			94.03	0.00	96.68	0.00	98.05	0.00	/workspace/coverage/cover_reg_top/23.chip_tl_errors.2874920862
94.72	0.05	94.08	0.02	92.01	0.26	93.45	0.01			94.04	0.01	96.68	0.00	98.05	0.00	/workspace/coverage/cover_reg_top/13.chip_csr_rw.679197630
94.76	0.05	94.13	0.04	92.04	0.03	93.45	0.01			94.05	0.02	96.85	0.17	98.06	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.1749683516
94.81	0.04	94.15	0.02	92.05	0.01	93.68	0.23			94.06	0.01	96.85	0.00	98.06	0.00	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2829968987
94.85	0.04	94.17	0.02	92.08	0.03	93.68	0.00			94.09	0.03	97.03	0.17	98.07	0.01	/workspace/coverage/default/56.chip_sw_all_escalation_resets.2249518514
94.90	0.04	94.17	0.01	92.10	0.03	93.74	0.06			94.09	0.00	97.20	0.17	98.07	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3453810491
94.94	0.04	94.17	0.00	92.10	0.00	94.00	0.26			94.09	0.00	97.20	0.00	98.07	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3102925166
94.98	0.04	94.20	0.03	92.11	0.01	94.00	0.01			94.11	0.02	97.38	0.17	98.08	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.960567894
95.02	0.04	94.20	0.01	92.12	0.01	94.01	0.01			94.12	0.01	97.55	0.17	98.10	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.63203712
95.05	0.03	94.24	0.03	92.14	0.02	94.13	0.13			94.14	0.02	97.55	0.00	98.10	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1715073901
95.08	0.03	94.24	0.00	92.33	0.19	94.13	0.00			94.14	0.00	97.55	0.00	98.10	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.3941327911
95.11	0.03	94.24	0.00	92.33	0.00	94.31	0.18			94.14	0.00	97.55	0.00	98.10	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1872239428
95.14	0.03	94.24	0.00	92.33	0.00	94.48	0.18			94.14	0.00	97.55	0.00	98.10	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2153820160
95.17	0.03	94.31	0.07	92.33	0.00	94.58	0.09			94.15	0.01	97.55	0.00	98.10	0.00	/workspace/coverage/default/2.chip_tap_straps_testunlock0.2101997097
95.20	0.03	94.31	0.00	92.33	0.01	94.58	0.00			94.15	0.00	97.55	0.00	98.26	0.16	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.1535810101
95.22	0.03	94.38	0.07	92.36	0.03	94.58	0.01			94.20	0.05	97.55	0.00	98.26	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.522386303
95.25	0.03	94.38	0.00	92.51	0.15	94.58	0.00			94.20	0.00	97.55	0.00	98.26	0.00	/workspace/coverage/cover_reg_top/21.chip_tl_errors.2119412153
95.27	0.03	94.45	0.07	92.57	0.05	94.58	0.00			94.23	0.03	97.55	0.00	98.26	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.853646589
95.30	0.02	94.45	0.00	92.61	0.05	94.58	0.00			94.25	0.02	97.55	0.00	98.34	0.08	/workspace/coverage/cover_reg_top/24.xbar_access_same_device.1875870219
95.32	0.02	94.47	0.02	92.63	0.02	94.66	0.07			94.26	0.02	97.55	0.00	98.36	0.01	/workspace/coverage/default/3.chip_sw_all_escalation_resets.401492279
95.34	0.02	94.50	0.03	92.64	0.01	94.76	0.10			94.26	0.00	97.55	0.00	98.36	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2348011128
95.36	0.02	94.56	0.07	92.68	0.05	94.76	0.00			94.28	0.02	97.55	0.00	98.36	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2823628024
95.38	0.02	94.57	0.01	92.71	0.03	94.83	0.08			94.29	0.01	97.55	0.00	98.36	0.00	/workspace/coverage/default/0.chip_sw_usbdev_config_host.2060012522
95.40	0.02	94.57	0.00	92.76	0.05	94.83	0.00			94.30	0.02	97.55	0.00	98.40	0.05	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2885969828
95.42	0.02	94.59	0.02	92.79	0.04	94.87	0.04			94.30	0.00	97.55	0.00	98.40	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3652466295
95.43	0.01	94.59	0.00	92.80	0.01	94.87	0.00			94.30	0.00	97.55	0.00	98.48	0.08	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1291560022
95.45	0.01	94.59	0.00	92.80	0.00	94.96	0.09			94.30	0.00	97.55	0.00	98.48	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1348617628
95.46	0.01	94.59	0.00	92.88	0.08	94.96	0.00			94.30	0.00	97.55	0.00	98.48	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.698780404
95.48	0.01	94.61	0.01	92.93	0.04	94.99	0.03			94.30	0.00	97.55	0.00	98.48	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.615501026
95.49	0.01	94.61	0.00	92.94	0.01	94.99	0.00			94.30	0.00	97.55	0.00	98.54	0.06	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.309096239
95.50	0.01	94.61	0.00	92.99	0.05	94.99	0.00			94.30	0.00	97.55	0.00	98.55	0.01	/workspace/coverage/cover_reg_top/18.chip_tl_errors.1657704458
95.51	0.01	94.61	0.00	93.03	0.04	94.99	0.00			94.30	0.00	97.55	0.00	98.58	0.02	/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.1277641845
95.52	0.01	94.61	0.00	93.03	0.00	95.03	0.04			94.30	0.00	97.55	0.00	98.59	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.3592042
95.53	0.01	94.63	0.02	93.03	0.01	95.06	0.03			94.30	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/2.chip_sw_power_sleep_load.3389888959
95.54	0.01	94.67	0.04	93.04	0.01	95.07	0.01			94.30	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2195432389
95.55	0.01	94.67	0.00	93.04	0.01	95.07	0.00			94.30	0.00	97.55	0.00	98.64	0.05	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.225539835
95.55	0.01	94.69	0.02	93.05	0.01	95.08	0.01			94.32	0.02	97.55	0.00	98.64	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1502949836
95.56	0.01	94.71	0.02	93.06	0.01	95.08	0.01			94.34	0.02	97.55	0.00	98.64	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.110428399
95.57	0.01	94.73	0.02	93.06	0.01	95.08	0.01			94.35	0.02	97.55	0.00	98.64	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1731500071
95.58	0.01	94.73	0.00	93.06	0.00	95.13	0.05			94.35	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.431293967
95.59	0.01	94.76	0.02	93.07	0.01	95.13	0.00			94.37	0.02	97.55	0.00	98.64	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1103548072
95.59	0.01	94.76	0.00	93.11	0.04	95.13	0.00			94.37	0.00	97.55	0.00	98.65	0.01	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.4030558955
95.60	0.01	94.77	0.01	93.12	0.02	95.15	0.01			94.38	0.01	97.55	0.00	98.65	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2619321115
95.61	0.01	94.78	0.01	93.12	0.00	95.18	0.03			94.38	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3761247802
95.62	0.01	94.78	0.00	93.17	0.05	95.18	0.00			94.38	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.2062447449
95.63	0.01	94.78	0.00	93.22	0.05	95.18	0.00			94.38	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.3017350543
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95.72	0.01	94.79	0.00	93.44	0.00	95.34	0.00			94.39	0.00	97.55	0.00	98.79	0.02	/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.516549548
95.72	0.01	94.79	0.00	93.44	0.00	95.35	0.01			94.39	0.00	97.55	0.00	98.80	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2343193112
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95.74	0.01	94.80	0.00	93.49	0.00	95.42	0.01			94.39	0.01	97.55	0.00	98.81	0.00	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2108414114
95.75	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	98.83	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1679288799
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95.75	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	98.87	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1367431718
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95.76	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	98.90	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.6780687
95.76	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	98.91	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1915861019
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95.76	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	98.93	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2332258032
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95.77	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	99.00	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.3302614772
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95.78	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	99.04	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.961860073
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95.79	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	99.10	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.2791475433
95.79	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	99.11	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.499426201
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95.80	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	99.13	0.01	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1070186742
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95.81	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	99.19	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.2023674084
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95.86	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/77.chip_sw_all_escalation_resets.1484149302
95.86	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2039635533
95.87	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2514315172
95.87	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	99.57	0.01	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1776152449
95.87	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	99.58	0.01	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.964407970
95.87	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	99.59	0.01	/workspace/coverage/default/95.chip_sw_all_escalation_resets.1847823100
95.87	0.01	94.80	0.00	93.49	0.00	95.42	0.00			94.39	0.00	97.55	0.00	99.60	0.01	/workspace/coverage/default/99.chip_sw_all_escalation_resets.3413103526
95.88	0.01	94.80	0.00	93.49	0.01	95.42	0.00			94.40	0.01	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1265734526
95.88	0.01	94.80	0.00	93.50	0.01	95.42	0.00			94.40	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2125690600
95.88	0.01	94.80	0.00	93.51	0.01	95.42	0.00			94.40	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2368781428
95.88	0.01	94.80	0.00	93.52	0.01	95.42	0.00			94.40	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1831003809
95.88	0.01	94.80	0.01	93.53	0.01	95.42	0.00			94.40	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.3486973803
95.89	0.01	94.80	0.01	93.53	0.00	95.42	0.01			94.40	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/7.chip_sw_all_escalation_resets.3444119209
95.89	0.01	94.81	0.01	93.53	0.00	95.42	0.00			94.40	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.3517615456
95.89	0.01	94.81	0.00	93.53	0.00	95.43	0.01			94.40	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3796721529
95.89	0.01	94.81	0.00	93.53	0.00	95.44	0.01			94.40	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2286171808
95.89	0.01	94.81	0.00	93.53	0.00	95.44	0.00			94.41	0.01	97.55	0.00	99.60	0.00	/workspace/coverage/default/1.chip_tap_straps_dev.492934141
95.89	0.01	94.81	0.00	93.54	0.01	95.44	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/13.chip_tl_errors.1108825137
95.89	0.01	94.81	0.00	93.54	0.01	95.44	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2929289812
95.90	0.01	94.81	0.00	93.55	0.01	95.44	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/16.xbar_stress_all.4227236759
95.90	0.01	94.81	0.00	93.56	0.01	95.44	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.2598844025
95.90	0.01	94.81	0.00	93.57	0.01	95.44	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_gpio.976185597
95.90	0.01	94.81	0.00	93.57	0.01	95.44	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.1992474738
95.90	0.01	94.81	0.00	93.57	0.00	95.45	0.01			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.6936985
95.90	0.01	94.82	0.01	93.57	0.00	95.45	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.387755651
95.90	0.01	94.83	0.01	93.57	0.00	95.45	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3312573993
95.90	0.01	94.83	0.00	93.57	0.00	95.45	0.01			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.569340966
95.90	0.01	94.83	0.00	93.57	0.00	95.46	0.01			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1309294199
95.90	0.01	94.83	0.00	93.57	0.00	95.46	0.01			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc.184906135
95.91	0.01	94.83	0.00	93.57	0.00	95.47	0.01			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.154747566
95.91	0.01	94.83	0.00	93.57	0.00	95.47	0.01			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1131768489
95.91	0.01	94.83	0.00	93.57	0.00	95.48	0.01			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2017336895
95.91	0.01	94.83	0.00	93.58	0.01	95.48	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/11.xbar_error_random.555964214
95.91	0.01	94.83	0.00	93.58	0.01	95.48	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.2103197107
95.91	0.01	94.83	0.00	93.58	0.01	95.48	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.2504809529
95.91	0.01	94.83	0.00	93.59	0.01	95.48	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.1493812962
95.91	0.01	94.83	0.00	93.59	0.01	95.48	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.606408943
95.91	0.01	94.83	0.00	93.59	0.01	95.48	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.2285057768
95.91	0.01	94.83	0.00	93.60	0.01	95.48	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.23862168
95.91	0.01	94.83	0.00	93.60	0.01	95.48	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.815382792
95.91	0.01	94.83	0.00	93.60	0.01	95.48	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.993870906
95.91	0.01	94.83	0.00	93.61	0.01	95.48	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1764133915
95.91	0.01	94.83	0.00	93.61	0.01	95.48	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2272113910
95.91	0.01	94.83	0.00	93.61	0.01	95.48	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/1.chip_sw_gpio.2752542309
95.91	0.01	94.83	0.00	93.61	0.00	95.48	0.01			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1689621579
95.91	0.01	94.83	0.01	93.61	0.00	95.48	0.00			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.433867655
95.92	0.01	94.83	0.00	93.61	0.00	95.48	0.01			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.3315002366
95.92	0.01	94.83	0.00	93.61	0.00	95.49	0.01			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.4062080356
95.92	0.01	94.83	0.00	93.61	0.00	95.49	0.01			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2784584250
95.92	0.01	94.83	0.00	93.61	0.00	95.49	0.01			94.41	0.00	97.55	0.00	99.60	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2183081999

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3994078423
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2983734983
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2364170180
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1402139583
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.372887482
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.579199308
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2783789906
/workspace/coverage/cover_reg_top/0.chip_tl_errors.2666272476
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.681305648
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.4024269432
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3373588376
/workspace/coverage/cover_reg_top/0.xbar_error_random.2736808551
/workspace/coverage/cover_reg_top/0.xbar_random.3502849917
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3847772128
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1538792515
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.888671510
/workspace/coverage/cover_reg_top/0.xbar_same_source.1575696599
/workspace/coverage/cover_reg_top/0.xbar_smoke.1269810881
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2729023214
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3200265909
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2836871058
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2487099199
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.988628033
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.914921320
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2688875387
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1482382566
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3262334143
/workspace/coverage/cover_reg_top/1.chip_csr_rw.836834388
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.4240801085
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1207110774
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.748124216
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.462821958
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.4129731083
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1349343963
/workspace/coverage/cover_reg_top/1.xbar_error_random.1645032706
/workspace/coverage/cover_reg_top/1.xbar_random.3735480390
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3004115367
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1074301375
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.80322553
/workspace/coverage/cover_reg_top/1.xbar_same_source.2476852354
/workspace/coverage/cover_reg_top/1.xbar_smoke.2986862311
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2641399746
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.892342087
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1358816033
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1401372326
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.3703801978
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.951845896
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.961056042
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3617771202
/workspace/coverage/cover_reg_top/10.chip_csr_rw.4148315137
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.656107724
/workspace/coverage/cover_reg_top/10.chip_tl_errors.3039043002
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1229331387
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2248677728
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1609089297
/workspace/coverage/cover_reg_top/10.xbar_error_random.373500698
/workspace/coverage/cover_reg_top/10.xbar_random.3347401836
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3576595278
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3237936767
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.2010143313
/workspace/coverage/cover_reg_top/10.xbar_same_source.3313685578
/workspace/coverage/cover_reg_top/10.xbar_smoke.3454327361
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1934311799
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.664179904
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2925022700
/workspace/coverage/cover_reg_top/10.xbar_stress_all.2481661054
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.4002526216
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2804414168
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1382527390
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.4045469998
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3619914364
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3708451946
/workspace/coverage/cover_reg_top/11.chip_tl_errors.4019537296
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.642653722
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1190853862
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.914330901
/workspace/coverage/cover_reg_top/11.xbar_random.2150719856
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3040444277
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3510393302
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1592462411
/workspace/coverage/cover_reg_top/11.xbar_same_source.925914277
/workspace/coverage/cover_reg_top/11.xbar_smoke.232419529
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.3806230252
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.399044321
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.4213879244
/workspace/coverage/cover_reg_top/11.xbar_stress_all.248310187
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3287235498
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2775453089
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.150205536
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.735939250
/workspace/coverage/cover_reg_top/12.chip_csr_rw.663120707
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3627205115
/workspace/coverage/cover_reg_top/12.chip_tl_errors.1536867463
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.16886559
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.4072892548
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2003072242
/workspace/coverage/cover_reg_top/12.xbar_error_random.3562345558
/workspace/coverage/cover_reg_top/12.xbar_random.3798907927
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1096302661
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3654871569
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2706874611
/workspace/coverage/cover_reg_top/12.xbar_same_source.2351116525
/workspace/coverage/cover_reg_top/12.xbar_smoke.428519913
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.4038688149
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.965572239
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1313002276
/workspace/coverage/cover_reg_top/12.xbar_stress_all.2420347560
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.913781550
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2946761898
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.158025966
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.123306860
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1879869
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.1689712010
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1662265080
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.151513712
/workspace/coverage/cover_reg_top/13.xbar_error_random.1907920648
/workspace/coverage/cover_reg_top/13.xbar_random.3441737522
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2945782179
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.4109632597
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2903601225
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/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.4021983485
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2959650804
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3543783002
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2361486430
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1896313002
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2523072885
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2626433427
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1474085523
/workspace/coverage/default/2.chip_sw_rv_timer_irq.678479900
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2296006967
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2075323844
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.1079346837
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3149281143
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2138337227
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/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3538881527
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/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3480980388
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/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2105346691
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/workspace/coverage/default/3.chip_tap_straps_dev.1132884802
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/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2310079745
/workspace/coverage/default/33.chip_sw_all_escalation_resets.2988984990
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3677987633
/workspace/coverage/default/34.chip_sw_all_escalation_resets.2742475771
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3798805273
/workspace/coverage/default/35.chip_sw_all_escalation_resets.4144835586
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.37735793
/workspace/coverage/default/36.chip_sw_all_escalation_resets.3468747397
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3474616594
/workspace/coverage/default/37.chip_sw_all_escalation_resets.1594844657
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1614131730
/workspace/coverage/default/39.chip_sw_all_escalation_resets.261354949
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1079944910
/workspace/coverage/default/4.chip_sw_all_escalation_resets.4069097105
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.157378567
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2530838630
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1403966753
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2226977018
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4159406358
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.174418201
/workspace/coverage/default/4.chip_sw_uart_tx_rx.1231297086
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/workspace/coverage/default/4.chip_tap_straps_dev.1786363399
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/workspace/coverage/default/4.chip_tap_straps_rma.2365516051
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1654397744
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383305223
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3926677364
/workspace/coverage/default/42.chip_sw_all_escalation_resets.265232610
/workspace/coverage/default/43.chip_sw_all_escalation_resets.3477474020
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1212316002
/workspace/coverage/default/45.chip_sw_all_escalation_resets.3538668523
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2557568317
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2430774220
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.4055080737
/workspace/coverage/default/49.chip_sw_all_escalation_resets.580368100
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3177664125
/workspace/coverage/default/5.chip_sw_all_escalation_resets.579603034
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.448876714
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1948355083
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.4059861151
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1974308574
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.569222867
/workspace/coverage/default/52.chip_sw_all_escalation_resets.460555894
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1291066821
/workspace/coverage/default/54.chip_sw_all_escalation_resets.46886898
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1862843195
/workspace/coverage/default/55.chip_sw_all_escalation_resets.1179832074
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1491091601
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.933392519
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1807917554
/workspace/coverage/default/58.chip_sw_all_escalation_resets.2428356495
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2864198052
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.513943717
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3530900481
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3191352274
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3031817248
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1109698544
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2697228797
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3085190720
/workspace/coverage/default/63.chip_sw_all_escalation_resets.596355291
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.4163211263
/workspace/coverage/default/64.chip_sw_all_escalation_resets.123894123
/workspace/coverage/default/65.chip_sw_all_escalation_resets.3507657769
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3172745969
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3019372440
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2398984664
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2076508990
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.726671868
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.316108117
/workspace/coverage/default/69.chip_sw_all_escalation_resets.3562587058
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3293346026
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.662045409
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2087038375
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3147209759
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3906410883
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2121662288
/workspace/coverage/default/71.chip_sw_all_escalation_resets.1550667267
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3444555698
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3104058584
/workspace/coverage/default/73.chip_sw_all_escalation_resets.605315899
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2824547357
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2100313241
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2829032541
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2184701294
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.665782036
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3374619367
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2047687896
/workspace/coverage/default/8.chip_sw_all_escalation_resets.140826652
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1716550994
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2263567447
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3262443993
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.460438520
/workspace/coverage/default/80.chip_sw_all_escalation_resets.622142631
/workspace/coverage/default/81.chip_sw_all_escalation_resets.53749843
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1083409890
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3730882722
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3382178526
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3426612925
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3500665178
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2585848625
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2533115707
/workspace/coverage/default/86.chip_sw_all_escalation_resets.2028420052
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1310071824
/workspace/coverage/default/87.chip_sw_all_escalation_resets.696545129
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1978729097
/workspace/coverage/default/88.chip_sw_all_escalation_resets.4200858726
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2261849729
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2361038341
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3424955760
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3886912043
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.4223434682
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2684228142
/workspace/coverage/default/90.chip_sw_all_escalation_resets.170952242
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1834825562
/workspace/coverage/default/92.chip_sw_all_escalation_resets.609543636
/workspace/coverage/default/93.chip_sw_all_escalation_resets.567037560
/workspace/coverage/default/94.chip_sw_all_escalation_resets.678174286
/workspace/coverage/default/96.chip_sw_all_escalation_resets.4074112216
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1510982782
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1047477220
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.217865062
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1692315846
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1164335796
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1814822430
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.562520973
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.320414827
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2556779911
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.856632003

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Total test records in report: 2907

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1911399206			Jul 14 08:04:26 PM PDT 24	Jul 14 08:11:51 PM PDT 24	4886310856 ps
T5	/workspace/coverage/default/2.chip_sw_pattgen_ios.407794410			Jul 14 08:07:35 PM PDT 24	Jul 14 08:10:59 PM PDT 24	2768358948 ps
T6	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.4056693713			Jul 14 08:21:03 PM PDT 24	Jul 14 09:01:23 PM PDT 24	11192843286 ps
T43	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1460551334			Jul 14 08:16:53 PM PDT 24	Jul 14 08:24:24 PM PDT 24	3348706690 ps
T17	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3798805273			Jul 14 08:22:40 PM PDT 24	Jul 14 08:29:37 PM PDT 24	4144656438 ps
T95	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2713121417			Jul 14 07:54:44 PM PDT 24	Jul 14 08:00:42 PM PDT 24	2848956990 ps
T42	/workspace/coverage/default/81.chip_sw_all_escalation_resets.53749843			Jul 14 08:27:11 PM PDT 24	Jul 14 08:34:49 PM PDT 24	5558892712 ps
T70	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.316108117			Jul 14 08:23:35 PM PDT 24	Jul 14 08:29:34 PM PDT 24	4333638932 ps
T71	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1194275139			Jul 14 08:13:28 PM PDT 24	Jul 14 09:01:29 PM PDT 24	21959589877 ps
T96	/workspace/coverage/default/1.chip_sw_example_rom.1412370992			Jul 14 07:55:07 PM PDT 24	Jul 14 07:56:56 PM PDT 24	2630526994 ps
T18	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.939137310			Jul 14 08:12:53 PM PDT 24	Jul 14 08:23:21 PM PDT 24	8237358510 ps
T215	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.441479922			Jul 14 07:53:16 PM PDT 24	Jul 14 08:08:10 PM PDT 24	5288497000 ps
T177	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1715073901			Jul 14 08:13:40 PM PDT 24	Jul 14 08:18:56 PM PDT 24	3108533537 ps
T61	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3876987738			Jul 14 07:55:42 PM PDT 24	Jul 14 08:07:26 PM PDT 24	3782611160 ps
T74	/workspace/coverage/default/3.chip_sw_all_escalation_resets.401492279			Jul 14 08:19:02 PM PDT 24	Jul 14 08:30:28 PM PDT 24	4931728440 ps
T19	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3861261542			Jul 14 07:52:51 PM PDT 24	Jul 14 11:44:09 PM PDT 24	78651775924 ps
T306	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2343193112			Jul 14 08:20:33 PM PDT 24	Jul 14 08:26:23 PM PDT 24	3803428866 ps
T307	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3152860876			Jul 14 08:20:54 PM PDT 24	Jul 14 08:28:05 PM PDT 24	3491907232 ps
T193	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1761626329			Jul 14 08:03:27 PM PDT 24	Jul 14 08:13:42 PM PDT 24	4409139794 ps
T255	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2272113910			Jul 14 07:53:45 PM PDT 24	Jul 14 08:06:41 PM PDT 24	5355129158 ps
T56	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2303214482			Jul 14 08:04:53 PM PDT 24	Jul 14 10:05:32 PM PDT 24	23188040174 ps
T176	/workspace/coverage/default/38.chip_sw_all_escalation_resets.3468143662			Jul 14 08:21:16 PM PDT 24	Jul 14 08:30:37 PM PDT 24	5420329952 ps
T62	/workspace/coverage/default/1.chip_tap_straps_prod.160928055			Jul 14 08:01:53 PM PDT 24	Jul 14 08:04:00 PM PDT 24	2624331683 ps
T72	/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.3789322273			Jul 14 08:12:01 PM PDT 24	Jul 14 08:18:54 PM PDT 24	4896200728 ps
T1	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4111518400			Jul 14 08:02:45 PM PDT 24	Jul 14 08:09:15 PM PDT 24	7194112572 ps
T20	/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3026566065			Jul 14 07:55:46 PM PDT 24	Jul 14 08:28:10 PM PDT 24	32575040755 ps
T105	/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1008319996			Jul 14 07:55:10 PM PDT 24	Jul 14 08:18:40 PM PDT 24	10804773502 ps
T57	/workspace/coverage/default/0.rom_e2e_static_critical.3881317486			Jul 14 08:03:04 PM PDT 24	Jul 14 09:09:56 PM PDT 24	17260920552 ps
T106	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2195432389			Jul 14 08:19:18 PM PDT 24	Jul 14 08:39:46 PM PDT 24	7943588300 ps
T107	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2361486430			Jul 14 08:12:03 PM PDT 24	Jul 14 08:26:25 PM PDT 24	5133565560 ps
T108	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2434348395			Jul 14 07:59:10 PM PDT 24	Jul 14 08:50:22 PM PDT 24	11698375390 ps
T109	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3420824716			Jul 14 07:57:35 PM PDT 24	Jul 14 08:19:52 PM PDT 24	10399252136 ps
T63	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.879798992			Jul 14 08:00:11 PM PDT 24	Jul 14 08:01:58 PM PDT 24	2450442479 ps
T110	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3177664125			Jul 14 08:18:06 PM PDT 24	Jul 14 08:27:58 PM PDT 24	4663809688 ps
T711	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.726671868			Jul 14 08:24:33 PM PDT 24	Jul 14 08:31:35 PM PDT 24	3410857660 ps
T211	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.387755651			Jul 14 07:52:01 PM PDT 24	Jul 14 08:07:08 PM PDT 24	4561979964 ps
T117	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3604342708			Jul 14 08:13:47 PM PDT 24	Jul 14 08:26:01 PM PDT 24	3249445144 ps
T121	/workspace/coverage/default/0.chip_sw_otbn_randomness.1965324325			Jul 14 07:52:30 PM PDT 24	Jul 14 08:08:04 PM PDT 24	5860393388 ps
T90	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3221489933			Jul 14 08:26:44 PM PDT 24	Jul 14 08:33:31 PM PDT 24	3938636680 ps
T58	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2829968987			Jul 14 08:19:22 PM PDT 24	Jul 14 08:37:08 PM PDT 24	11953597575 ps
T97	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.140290708			Jul 14 07:59:11 PM PDT 24	Jul 14 08:03:55 PM PDT 24	3024010430 ps
T98	/workspace/coverage/default/1.chip_sw_kmac_entropy.2635347548			Jul 14 07:58:19 PM PDT 24	Jul 14 08:02:39 PM PDT 24	2280990358 ps
T99	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2435120664			Jul 14 07:57:48 PM PDT 24	Jul 14 08:11:06 PM PDT 24	4542283374 ps
T100	/workspace/coverage/default/51.chip_sw_all_escalation_resets.1360355363			Jul 14 08:22:47 PM PDT 24	Jul 14 08:34:40 PM PDT 24	5006866152 ps
T101	/workspace/coverage/default/1.chip_sw_otbn_randomness.266491322			Jul 14 08:00:37 PM PDT 24	Jul 14 08:17:18 PM PDT 24	6144237104 ps
T91	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1952548588			Jul 14 08:12:16 PM PDT 24	Jul 14 11:17:27 PM PDT 24	256323774954 ps
T102	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3633687541			Jul 14 07:53:57 PM PDT 24	Jul 14 11:41:39 PM PDT 24	256090613184 ps
T103	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3366668319			Jul 14 08:06:52 PM PDT 24	Jul 14 08:20:01 PM PDT 24	5176905592 ps
T59	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2108414114			Jul 14 08:13:35 PM PDT 24	Jul 14 08:20:48 PM PDT 24	5036248678 ps
T158	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2398984664			Jul 14 08:24:48 PM PDT 24	Jul 14 08:30:40 PM PDT 24	3325181344 ps
T152	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.4099887894			Jul 14 08:12:30 PM PDT 24	Jul 14 08:55:12 PM PDT 24	12329658270 ps
T118	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4134887441			Jul 14 07:55:59 PM PDT 24	Jul 14 08:06:44 PM PDT 24	3843705880 ps
T260	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1689621579			Jul 14 07:53:42 PM PDT 24	Jul 14 07:56:25 PM PDT 24	1962233976 ps
T212	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3089931504			Jul 14 08:18:53 PM PDT 24	Jul 14 08:42:40 PM PDT 24	8563585710 ps
T53	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3746102224			Jul 14 08:18:25 PM PDT 24	Jul 14 09:11:18 PM PDT 24	14885591689 ps
T2	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.815006269			Jul 14 08:15:15 PM PDT 24	Jul 14 08:47:52 PM PDT 24	24890615696 ps
T73	/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.427170363			Jul 14 08:02:50 PM PDT 24	Jul 14 08:10:41 PM PDT 24	4329157318 ps
T29	/workspace/coverage/default/0.chip_sw_usbdev_stream.2883374450			Jul 14 07:52:44 PM PDT 24	Jul 14 08:49:43 PM PDT 24	19214896274 ps
T153	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3555013652			Jul 14 07:54:48 PM PDT 24	Jul 14 08:51:58 PM PDT 24	12411960276 ps
T27	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2684228142			Jul 14 08:17:51 PM PDT 24	Jul 14 08:39:13 PM PDT 24	8706544296 ps
T216	/workspace/coverage/default/4.chip_sw_uart_tx_rx.1231297086			Jul 14 08:15:47 PM PDT 24	Jul 14 08:27:05 PM PDT 24	4628385896 ps
T356	/workspace/coverage/default/28.chip_sw_all_escalation_resets.2589835639			Jul 14 08:21:22 PM PDT 24	Jul 14 08:30:51 PM PDT 24	4634841460 ps
T210	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1181392188			Jul 14 08:22:24 PM PDT 24	Jul 14 08:29:12 PM PDT 24	3353490420 ps
T60	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3774540056			Jul 14 07:51:52 PM PDT 24	Jul 14 08:00:12 PM PDT 24	5597214702 ps
T64	/workspace/coverage/default/2.chip_jtag_csr_rw.2655452295			Jul 14 08:05:14 PM PDT 24	Jul 14 08:21:08 PM PDT 24	8995005670 ps
T92	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3439747470			Jul 14 07:56:37 PM PDT 24	Jul 14 08:18:06 PM PDT 24	9945365068 ps
T28	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1510157113			Jul 14 08:17:10 PM PDT 24	Jul 14 08:28:09 PM PDT 24	3875003904 ps
T54	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2241476611			Jul 14 08:05:06 PM PDT 24	Jul 14 09:46:32 PM PDT 24	24394398152 ps
T335	/workspace/coverage/default/11.chip_sw_all_escalation_resets.4101121833			Jul 14 08:18:27 PM PDT 24	Jul 14 08:28:26 PM PDT 24	4412366400 ps
T701	/workspace/coverage/default/1.chip_sw_aes_entropy.3353402904			Jul 14 07:58:26 PM PDT 24	Jul 14 08:01:35 PM PDT 24	2572921458 ps
T341	/workspace/coverage/default/97.chip_sw_all_escalation_resets.1510982782			Jul 14 08:25:46 PM PDT 24	Jul 14 08:38:34 PM PDT 24	5372645544 ps
T408	/workspace/coverage/default/1.rom_e2e_static_critical.345455531			Jul 14 08:08:40 PM PDT 24	Jul 14 09:27:39 PM PDT 24	17449268660 ps
T259	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1716550994			Jul 14 08:18:53 PM PDT 24	Jul 14 09:05:49 PM PDT 24	12819128696 ps
T146	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3999354365			Jul 14 08:18:13 PM PDT 24	Jul 14 08:55:51 PM PDT 24	13051731992 ps
T878	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.3346018055			Jul 14 08:14:01 PM PDT 24	Jul 14 08:21:24 PM PDT 24	3099128332 ps
T115	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3453810491			Jul 14 08:12:22 PM PDT 24	Jul 14 08:24:40 PM PDT 24	4192221881 ps
T239	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1912889705			Jul 14 07:59:13 PM PDT 24	Jul 14 08:08:11 PM PDT 24	3222919940 ps
T487	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2795747906			Jul 14 07:54:55 PM PDT 24	Jul 14 08:19:04 PM PDT 24	7438784067 ps
T404	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2739429466			Jul 14 07:55:34 PM PDT 24	Jul 14 08:26:52 PM PDT 24	7292531250 ps
T79	/workspace/coverage/default/0.chip_jtag_mem_access.3820184925			Jul 14 07:46:04 PM PDT 24	Jul 14 08:12:18 PM PDT 24	12977370610 ps
T879	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.862719965			Jul 14 08:01:26 PM PDT 24	Jul 14 09:03:36 PM PDT 24	15235320080 ps
T245	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2557568317			Jul 14 08:21:50 PM PDT 24	Jul 14 08:30:30 PM PDT 24	4595375968 ps
T295	/workspace/coverage/default/2.chip_sw_csrng_kat_test.3700645756			Jul 14 08:11:04 PM PDT 24	Jul 14 08:16:52 PM PDT 24	2822717130 ps
T296	/workspace/coverage/default/0.chip_sw_aes_masking_off.4092498251			Jul 14 07:53:15 PM PDT 24	Jul 14 07:59:12 PM PDT 24	3135875272 ps
T180	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.776593615			Jul 14 08:03:55 PM PDT 24	Jul 14 08:07:29 PM PDT 24	2093296778 ps
T192	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2937341189			Jul 14 08:13:01 PM PDT 24	Jul 14 08:23:00 PM PDT 24	4698391160 ps
T116	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1376923082			Jul 14 08:13:43 PM PDT 24	Jul 14 08:17:47 PM PDT 24	2470816944 ps
T297	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.945570239			Jul 14 08:05:04 PM PDT 24	Jul 14 08:08:40 PM PDT 24	2633111226 ps
T186	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2523072885			Jul 14 08:12:21 PM PDT 24	Jul 14 08:20:01 PM PDT 24	5294180832 ps
T298	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2147913197			Jul 14 08:00:33 PM PDT 24	Jul 14 08:21:48 PM PDT 24	9626840144 ps
T299	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.4119192185			Jul 14 08:10:11 PM PDT 24	Jul 14 08:14:06 PM PDT 24	2598264810 ps
T303	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1759342508			Jul 14 07:59:43 PM PDT 24	Jul 14 08:04:09 PM PDT 24	2955661672 ps
T119	/workspace/coverage/default/0.chip_sw_edn_auto_mode.194897474			Jul 14 07:54:48 PM PDT 24	Jul 14 08:15:09 PM PDT 24	5064203882 ps
T304	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3049196208			Jul 14 08:20:16 PM PDT 24	Jul 14 08:26:19 PM PDT 24	4389969000 ps
T178	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1361188411			Jul 14 08:13:20 PM PDT 24	Jul 14 08:24:21 PM PDT 24	5823246942 ps
T202	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2715980234			Jul 14 07:54:34 PM PDT 24	Jul 14 07:59:03 PM PDT 24	2711165266 ps
T308	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.933425358			Jul 14 08:19:17 PM PDT 24	Jul 14 08:49:02 PM PDT 24	8845169388 ps
T218	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1754147021			Jul 14 07:51:41 PM PDT 24	Jul 14 08:14:35 PM PDT 24	7611866524 ps
T88	/workspace/coverage/default/0.chip_jtag_csr_rw.3067705380			Jul 14 07:46:05 PM PDT 24	Jul 14 08:04:41 PM PDT 24	10291584975 ps
T703	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.961860073			Jul 14 08:19:36 PM PDT 24	Jul 14 08:27:26 PM PDT 24	3349623310 ps
T366	/workspace/coverage/default/56.chip_sw_all_escalation_resets.2249518514			Jul 14 08:24:22 PM PDT 24	Jul 14 08:34:10 PM PDT 24	4972885470 ps
T55	/workspace/coverage/default/0.rom_e2e_shutdown_output.3335521682			Jul 14 07:57:29 PM PDT 24	Jul 14 08:52:22 PM PDT 24	25062146072 ps
T113	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.4262021479			Jul 14 07:55:58 PM PDT 24	Jul 14 08:16:37 PM PDT 24	6869375175 ps
T393	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2057565767			Jul 14 08:14:50 PM PDT 24	Jul 14 08:27:38 PM PDT 24	8840735756 ps
T394	/workspace/coverage/default/83.chip_sw_all_escalation_resets.3426612925			Jul 14 08:27:43 PM PDT 24	Jul 14 08:36:54 PM PDT 24	5565177428 ps
T214	/workspace/coverage/default/0.chip_sw_pattgen_ios.433867655			Jul 14 07:51:48 PM PDT 24	Jul 14 07:56:16 PM PDT 24	3271450878 ps
T395	/workspace/coverage/default/1.chip_sw_aes_enc.2178722287			Jul 14 07:58:48 PM PDT 24	Jul 14 08:04:15 PM PDT 24	3152683112 ps
T396	/workspace/coverage/default/2.rom_keymgr_functest.1694840081			Jul 14 08:16:50 PM PDT 24	Jul 14 08:23:20 PM PDT 24	4429144770 ps
T388	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.622826126			Jul 14 08:24:48 PM PDT 24	Jul 14 08:31:11 PM PDT 24	4012129688 ps
T163	/workspace/coverage/default/2.rom_volatile_raw_unlock.2316269965			Jul 14 08:13:52 PM PDT 24	Jul 14 08:15:55 PM PDT 24	2928267051 ps
T272	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3399406029			Jul 14 08:00:46 PM PDT 24	Jul 14 09:33:08 PM PDT 24	24025101524 ps
T386	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.264394180			Jul 14 08:22:52 PM PDT 24	Jul 14 08:28:17 PM PDT 24	3793857964 ps
T21	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2833892275			Jul 14 07:51:57 PM PDT 24	Jul 14 07:56:07 PM PDT 24	2524503402 ps
T880	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1923897200			Jul 14 07:55:49 PM PDT 24	Jul 14 08:01:27 PM PDT 24	2805694780 ps
T274	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2895559630			Jul 14 07:54:13 PM PDT 24	Jul 14 08:01:35 PM PDT 24	8297876706 ps
T219	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.4092651519			Jul 14 08:23:50 PM PDT 24	Jul 14 08:30:23 PM PDT 24	3591939878 ps
T378	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3490634647			Jul 14 08:01:31 PM PDT 24	Jul 14 09:53:39 PM PDT 24	24854019116 ps
T240	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1246224092			Jul 14 08:09:09 PM PDT 24	Jul 14 08:23:13 PM PDT 24	5046302290 ps
T268	/workspace/coverage/default/25.chip_sw_all_escalation_resets.2936495916			Jul 14 08:20:10 PM PDT 24	Jul 14 08:31:41 PM PDT 24	4840803768 ps
T81	/workspace/coverage/default/0.chip_tap_straps_prod.3990144689			Jul 14 07:54:54 PM PDT 24	Jul 14 08:18:47 PM PDT 24	13335376131 ps
T269	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1599333909			Jul 14 08:00:45 PM PDT 24	Jul 14 09:23:56 PM PDT 24	22104624128 ps
T78	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.809938044			Jul 14 08:15:41 PM PDT 24	Jul 14 08:23:49 PM PDT 24	4913157394 ps
T132	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.110428399			Jul 14 08:02:56 PM PDT 24	Jul 14 08:12:31 PM PDT 24	4660731280 ps
T139	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3796721529			Jul 14 07:53:43 PM PDT 24	Jul 14 08:03:50 PM PDT 24	8827821056 ps
T171	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2263567447			Jul 14 08:17:48 PM PDT 24	Jul 14 08:36:03 PM PDT 24	11331059437 ps
T270	/workspace/coverage/default/13.chip_sw_all_escalation_resets.1835575585			Jul 14 08:19:01 PM PDT 24	Jul 14 08:32:47 PM PDT 24	4775922820 ps
T271	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1404919856			Jul 14 08:14:16 PM PDT 24	Jul 14 08:17:52 PM PDT 24	2936388200 ps
T181	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1633326572			Jul 14 07:54:32 PM PDT 24	Jul 14 08:08:32 PM PDT 24	7364811993 ps
T881	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2773605380			Jul 14 08:11:37 PM PDT 24	Jul 14 08:23:24 PM PDT 24	3961444978 ps
T114	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1872239428			Jul 14 07:53:35 PM PDT 24	Jul 14 08:10:47 PM PDT 24	6964049660 ps
T675	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2794532477			Jul 14 08:10:16 PM PDT 24	Jul 14 08:40:18 PM PDT 24	17633580236 ps
T704	/workspace/coverage/default/0.chip_sw_hmac_multistream.2437989331			Jul 14 07:57:05 PM PDT 24	Jul 14 08:29:47 PM PDT 24	8184483216 ps
T149	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.4062080356			Jul 14 08:00:32 PM PDT 24	Jul 14 09:06:24 PM PDT 24	17338881792 ps
T357	/workspace/coverage/default/54.chip_sw_all_escalation_resets.46886898			Jul 14 08:22:51 PM PDT 24	Jul 14 08:33:46 PM PDT 24	4865246080 ps
T344	/workspace/coverage/default/0.chip_sw_aon_timer_irq.504253583			Jul 14 07:53:17 PM PDT 24	Jul 14 08:00:39 PM PDT 24	3819870262 ps
T882	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3119600141			Jul 14 08:14:17 PM PDT 24	Jul 14 08:24:58 PM PDT 24	4240303272 ps
T883	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.637914732			Jul 14 07:54:59 PM PDT 24	Jul 14 07:59:26 PM PDT 24	3650264724 ps
T884	/workspace/coverage/default/1.rom_e2e_asm_init_rma.965201322			Jul 14 08:08:33 PM PDT 24	Jul 14 09:18:37 PM PDT 24	14197732500 ps
T336	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.403662443			Jul 14 08:05:53 PM PDT 24	Jul 14 08:10:22 PM PDT 24	2177756318 ps
T885	/workspace/coverage/default/2.chip_sw_example_concurrency.243820245			Jul 14 08:10:02 PM PDT 24	Jul 14 08:14:16 PM PDT 24	2629007268 ps
T184	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1202189984			Jul 14 07:56:26 PM PDT 24	Jul 14 08:06:13 PM PDT 24	4726005100 ps
T220	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2433248886			Jul 14 08:00:51 PM PDT 24	Jul 14 08:38:48 PM PDT 24	11304627290 ps
T273	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1765010818			Jul 14 08:00:19 PM PDT 24	Jul 14 08:56:15 PM PDT 24	15521282976 ps
T147	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.4059861151			Jul 14 08:17:06 PM PDT 24	Jul 14 09:02:22 PM PDT 24	12565904460 ps
T886	/workspace/coverage/default/1.chip_sw_hmac_multistream.1529494253			Jul 14 08:00:15 PM PDT 24	Jul 14 08:34:11 PM PDT 24	7808300840 ps
T221	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2080572764			Jul 14 08:01:15 PM PDT 24	Jul 14 08:40:03 PM PDT 24	12208050043 ps
T30	/workspace/coverage/default/0.chip_sw_usbdev_dpi.1524819487			Jul 14 07:53:13 PM PDT 24	Jul 14 08:42:13 PM PDT 24	11696912340 ps
T887	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1330446992			Jul 14 08:02:49 PM PDT 24	Jul 14 08:49:35 PM PDT 24	11611800568 ps
T363	/workspace/coverage/default/18.chip_sw_all_escalation_resets.2862696519			Jul 14 08:20:22 PM PDT 24	Jul 14 08:31:18 PM PDT 24	5006398218 ps
T169	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.172699660			Jul 14 07:55:32 PM PDT 24	Jul 14 09:16:59 PM PDT 24	44322650440 ps
T217	/workspace/coverage/default/3.chip_tap_straps_prod.1689582555			Jul 14 08:14:53 PM PDT 24	Jul 14 08:17:40 PM PDT 24	3165917113 ps
T35	/workspace/coverage/default/1.chip_sw_gpio_smoketest.932518178			Jul 14 08:05:31 PM PDT 24	Jul 14 08:10:46 PM PDT 24	3341247305 ps
T349	/workspace/coverage/default/2.chip_sw_hmac_enc.3450105826			Jul 14 08:11:39 PM PDT 24	Jul 14 08:17:03 PM PDT 24	2560007688 ps
T179	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3292005424			Jul 14 08:02:39 PM PDT 24	Jul 14 08:13:03 PM PDT 24	4097130240 ps
T888	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1577407844			Jul 14 08:11:05 PM PDT 24	Jul 14 08:26:03 PM PDT 24	4300042116 ps
T360	/workspace/coverage/default/87.chip_sw_all_escalation_resets.696545129			Jul 14 08:25:17 PM PDT 24	Jul 14 08:34:05 PM PDT 24	4927999248 ps
T728	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2047687896			Jul 14 08:27:48 PM PDT 24	Jul 14 08:33:14 PM PDT 24	4474162162 ps
T889	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2495702129			Jul 14 08:14:03 PM PDT 24	Jul 14 08:30:47 PM PDT 24	8565809344 ps
T208	/workspace/coverage/default/1.chip_jtag_mem_access.2290497152			Jul 14 07:55:16 PM PDT 24	Jul 14 08:21:37 PM PDT 24	13863276520 ps
T890	/workspace/coverage/default/1.chip_sw_hmac_oneshot.1370681690			Jul 14 08:01:49 PM PDT 24	Jul 14 08:06:17 PM PDT 24	2962125400 ps
T120	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3109778778			Jul 14 08:12:20 PM PDT 24	Jul 14 08:30:58 PM PDT 24	6628057208 ps
T891	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2849676978			Jul 14 08:04:53 PM PDT 24	Jul 14 08:16:43 PM PDT 24	4760708486 ps
T480	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1974786601			Jul 14 08:12:04 PM PDT 24	Jul 14 08:19:49 PM PDT 24	3102799508 ps
T892	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1604834462			Jul 14 07:59:38 PM PDT 24	Jul 14 08:03:42 PM PDT 24	3591996666 ps
T375	/workspace/coverage/default/3.chip_tap_straps_dev.1132884802			Jul 14 08:18:43 PM PDT 24	Jul 14 08:24:52 PM PDT 24	4175875478 ps
T75	/workspace/coverage/default/2.chip_tap_straps_testunlock0.2101997097			Jul 14 08:13:09 PM PDT 24	Jul 14 08:18:07 PM PDT 24	3562297287 ps
T893	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2639305571			Jul 14 07:54:19 PM PDT 24	Jul 14 08:04:45 PM PDT 24	4534355850 ps
T670	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1212316002			Jul 14 08:21:43 PM PDT 24	Jul 14 08:27:00 PM PDT 24	4318111536 ps
T334	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3652466295			Jul 14 07:58:35 PM PDT 24	Jul 14 08:18:39 PM PDT 24	9067088479 ps
T894	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1579186381			Jul 14 08:11:28 PM PDT 24	Jul 14 08:54:30 PM PDT 24	33126251460 ps
T125	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4159406358			Jul 14 08:17:47 PM PDT 24	Jul 14 08:31:25 PM PDT 24	8268980722 ps
T895	/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2079636989			Jul 14 08:18:21 PM PDT 24	Jul 14 08:26:47 PM PDT 24	7201017634 ps
T256	/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3642413124			Jul 14 07:57:15 PM PDT 24	Jul 14 08:54:50 PM PDT 24	32052744070 ps
T896	/workspace/coverage/default/0.chip_sw_kmac_idle.2394559549			Jul 14 07:55:33 PM PDT 24	Jul 14 08:00:46 PM PDT 24	2830775912 ps
T897	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1564628446			Jul 14 07:58:47 PM PDT 24	Jul 14 08:03:26 PM PDT 24	3550767696 ps
T898	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4028987002			Jul 14 08:03:03 PM PDT 24	Jul 14 08:15:04 PM PDT 24	4503753830 ps
T899	/workspace/coverage/default/0.chip_sw_example_rom.2821736949			Jul 14 07:51:16 PM PDT 24	Jul 14 07:53:18 PM PDT 24	1954369480 ps
T166	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2061202962			Jul 14 07:59:51 PM PDT 24	Jul 14 09:24:32 PM PDT 24	48534160184 ps
T209	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.48641291			Jul 14 07:57:12 PM PDT 24	Jul 14 08:00:55 PM PDT 24	2501617760 ps
T361	/workspace/coverage/default/47.chip_sw_all_escalation_resets.2430774220			Jul 14 08:21:41 PM PDT 24	Jul 14 08:30:47 PM PDT 24	5550829716 ps
T213	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2105346691			Jul 14 08:15:27 PM PDT 24	Jul 14 08:38:52 PM PDT 24	8646060040 ps
T900	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1453316239			Jul 14 07:59:05 PM PDT 24	Jul 14 08:10:43 PM PDT 24	4609443328 ps
T901	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3191352274			Jul 14 08:17:40 PM PDT 24	Jul 14 08:59:07 PM PDT 24	12453314410 ps
T902	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2765878060			Jul 14 08:09:48 PM PDT 24	Jul 14 08:18:52 PM PDT 24	8102276164 ps
T903	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.68182427			Jul 14 07:54:09 PM PDT 24	Jul 14 08:09:29 PM PDT 24	9261869080 ps
T904	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2335071362			Jul 14 07:58:52 PM PDT 24	Jul 14 08:41:44 PM PDT 24	11820769627 ps
T905	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2775518944			Jul 14 08:08:46 PM PDT 24	Jul 14 08:15:18 PM PDT 24	5183841000 ps
T379	/workspace/coverage/default/1.rom_e2e_asm_init_prod.900705889			Jul 14 08:10:15 PM PDT 24	Jul 14 09:03:01 PM PDT 24	15386210989 ps
T65	/workspace/coverage/default/1.chip_jtag_csr_rw.4014320454			Jul 14 07:55:25 PM PDT 24	Jul 14 08:12:31 PM PDT 24	9375513880 ps
T906	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2921390642			Jul 14 07:53:58 PM PDT 24	Jul 14 07:59:11 PM PDT 24	3157722489 ps
T478	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.235784715			Jul 14 08:00:48 PM PDT 24	Jul 14 08:19:58 PM PDT 24	5392707080 ps
T907	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1911103815			Jul 14 07:53:59 PM PDT 24	Jul 14 08:01:58 PM PDT 24	5865525482 ps
T908	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2139589440			Jul 14 08:10:39 PM PDT 24	Jul 14 08:16:49 PM PDT 24	4997323884 ps
T24	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1693675222			Jul 14 08:10:51 PM PDT 24	Jul 14 08:24:52 PM PDT 24	6965724828 ps
T909	/workspace/coverage/default/2.rom_e2e_asm_init_rma.3842156743			Jul 14 08:17:57 PM PDT 24	Jul 14 09:18:32 PM PDT 24	14342980040 ps
T31	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3761247802			Jul 14 08:09:24 PM PDT 24	Jul 14 09:01:39 PM PDT 24	20221366397 ps
T257	/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.4184772773			Jul 14 07:56:16 PM PDT 24	Jul 14 08:35:20 PM PDT 24	11803963616 ps
T234	/workspace/coverage/default/1.chip_sw_flash_init.2202701366			Jul 14 07:57:02 PM PDT 24	Jul 14 08:39:56 PM PDT 24	23119837335 ps
T669	/workspace/coverage/default/0.chip_sw_edn_kat.3248338830			Jul 14 07:54:08 PM PDT 24	Jul 14 08:06:42 PM PDT 24	3605727720 ps
T223	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2853139836			Jul 14 07:59:26 PM PDT 24	Jul 14 08:27:21 PM PDT 24	9651683600 ps
T69	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2619321115			Jul 14 07:51:50 PM PDT 24	Jul 14 07:58:49 PM PDT 24	3272600620 ps
T735	/workspace/coverage/default/90.chip_sw_all_escalation_resets.170952242			Jul 14 08:26:19 PM PDT 24	Jul 14 08:36:34 PM PDT 24	4579651670 ps
T910	/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.4135758035			Jul 14 08:10:06 PM PDT 24	Jul 14 08:14:13 PM PDT 24	3601846735 ps
T224	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3087611535			Jul 14 07:58:24 PM PDT 24	Jul 14 08:21:14 PM PDT 24	7358899100 ps
T3	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3671360134			Jul 14 08:00:16 PM PDT 24	Jul 14 08:05:42 PM PDT 24	3860713260 ps
T418	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2407294630			Jul 14 08:10:10 PM PDT 24	Jul 14 09:11:46 PM PDT 24	15293082024 ps
T419	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.11205424			Jul 14 08:01:35 PM PDT 24	Jul 14 08:11:02 PM PDT 24	5323064250 ps
T420	/workspace/coverage/default/4.chip_sw_all_escalation_resets.4069097105			Jul 14 08:16:06 PM PDT 24	Jul 14 08:29:27 PM PDT 24	6257143730 ps
T421	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1466573035			Jul 14 08:07:25 PM PDT 24	Jul 14 08:28:21 PM PDT 24	9302857512 ps
T422	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.800658957			Jul 14 07:51:29 PM PDT 24	Jul 14 08:09:52 PM PDT 24	6311695273 ps
T423	/workspace/coverage/default/1.chip_sw_aes_idle.236098395			Jul 14 08:01:05 PM PDT 24	Jul 14 08:05:49 PM PDT 24	2996455068 ps
T424	/workspace/coverage/default/0.chip_sw_hmac_smoketest.1023927695			Jul 14 07:57:17 PM PDT 24	Jul 14 08:04:09 PM PDT 24	3495963400 ps
T425	/workspace/coverage/default/1.chip_sw_example_manufacturer.671859899			Jul 14 07:56:08 PM PDT 24	Jul 14 08:00:43 PM PDT 24	3234111360 ps
T374	/workspace/coverage/default/24.chip_sw_all_escalation_resets.1811687141			Jul 14 08:20:22 PM PDT 24	Jul 14 08:31:54 PM PDT 24	5745140048 ps
T286	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1964923422			Jul 14 07:54:10 PM PDT 24	Jul 14 08:03:34 PM PDT 24	4735104916 ps
T911	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.937847049			Jul 14 07:51:58 PM PDT 24	Jul 14 08:19:01 PM PDT 24	8533414488 ps
T709	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3629776828			Jul 14 07:55:49 PM PDT 24	Jul 14 08:06:23 PM PDT 24	6296559744 ps
T745	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.87775977			Jul 14 08:20:36 PM PDT 24	Jul 14 08:25:05 PM PDT 24	3566478688 ps
T912	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1042728219			Jul 14 08:12:40 PM PDT 24	Jul 14 08:15:59 PM PDT 24	3195171168 ps
T913	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1034378675			Jul 14 08:06:31 PM PDT 24	Jul 14 09:18:28 PM PDT 24	14998806584 ps
T914	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2783289907			Jul 14 08:11:37 PM PDT 24	Jul 14 08:14:46 PM PDT 24	2895397744 ps
T167	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2860965175			Jul 14 08:09:07 PM PDT 24	Jul 14 09:35:13 PM PDT 24	47798954148 ps
T385	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1846899084			Jul 14 07:53:12 PM PDT 24	Jul 14 07:58:15 PM PDT 24	2984794260 ps
T142	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.925363681			Jul 14 07:53:03 PM PDT 24	Jul 14 11:06:51 PM PDT 24	58393665626 ps
T915	/workspace/coverage/default/2.chip_sw_uart_smoketest.519064263			Jul 14 08:16:29 PM PDT 24	Jul 14 08:21:04 PM PDT 24	3298324620 ps
T409	/workspace/coverage/default/1.chip_sw_kmac_app_rom.2963144416			Jul 14 08:01:51 PM PDT 24	Jul 14 08:04:51 PM PDT 24	3102221464 ps
T916	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.742401742			Jul 14 08:07:35 PM PDT 24	Jul 14 08:12:09 PM PDT 24	2932896720 ps
T287	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3765476000			Jul 14 07:54:50 PM PDT 24	Jul 14 08:03:52 PM PDT 24	4303485406 ps
T479	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1036322576			Jul 14 08:11:07 PM PDT 24	Jul 14 08:17:37 PM PDT 24	3152979416 ps
T664	/workspace/coverage/default/1.chip_sw_aes_masking_off.907181092			Jul 14 08:01:11 PM PDT 24	Jul 14 08:07:44 PM PDT 24	2938101612 ps
T150	/workspace/coverage/default/1.chip_sw_otbn_smoketest.1377722372			Jul 14 08:06:12 PM PDT 24	Jul 14 08:34:02 PM PDT 24	8540061786 ps
T93	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.2523331548			Jul 14 08:00:36 PM PDT 24	Jul 14 08:06:09 PM PDT 24	3654279971 ps
T253	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.754395354			Jul 14 07:56:31 PM PDT 24	Jul 14 08:01:45 PM PDT 24	2681136610 ps
T148	/workspace/coverage/default/0.chip_sw_power_sleep_load.2800322281			Jul 14 07:54:47 PM PDT 24	Jul 14 08:05:54 PM PDT 24	11398676872 ps
T481	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2346825342			Jul 14 08:03:33 PM PDT 24	Jul 14 08:21:24 PM PDT 24	6642632056 ps
T917	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2166298889			Jul 14 08:04:19 PM PDT 24	Jul 14 08:12:16 PM PDT 24	3619657200 ps
T918	/workspace/coverage/default/2.rom_e2e_asm_init_dev.1442961927			Jul 14 08:19:11 PM PDT 24	Jul 14 09:10:53 PM PDT 24	15394529676 ps
T345	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1946814382			Jul 14 08:01:05 PM PDT 24	Jul 14 08:08:49 PM PDT 24	3457864296 ps
T919	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1474085523			Jul 14 08:18:11 PM PDT 24	Jul 14 08:21:43 PM PDT 24	3213656896 ps
T172	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2474352375			Jul 14 08:12:31 PM PDT 24	Jul 14 08:25:04 PM PDT 24	11778943890 ps
T246	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3761154052			Jul 14 08:22:41 PM PDT 24	Jul 14 08:32:59 PM PDT 24	3644087260 ps
T170	/workspace/coverage/default/0.rom_raw_unlock.31809172			Jul 14 07:58:11 PM PDT 24	Jul 14 08:03:15 PM PDT 24	6818590599 ps
T920	/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.134135552			Jul 14 07:52:46 PM PDT 24	Jul 14 07:58:00 PM PDT 24	3044009328 ps
T80	/workspace/coverage/default/0.chip_tap_straps_rma.1621351604			Jul 14 07:55:24 PM PDT 24	Jul 14 07:57:29 PM PDT 24	2216330208 ps
T921	/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3029412503			Jul 14 07:58:18 PM PDT 24	Jul 14 08:03:58 PM PDT 24	3193977046 ps
T922	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1409910716			Jul 14 07:56:14 PM PDT 24	Jul 14 08:00:09 PM PDT 24	3400505955 ps
T677	/workspace/coverage/default/1.chip_tap_straps_dev.492934141			Jul 14 08:02:48 PM PDT 24	Jul 14 08:16:58 PM PDT 24	8387767407 ps
T923	/workspace/coverage/default/2.chip_sw_edn_kat.1820957789			Jul 14 08:13:00 PM PDT 24	Jul 14 08:24:06 PM PDT 24	3572602424 ps
T126	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.522386303			Jul 14 08:19:51 PM PDT 24	Jul 14 08:33:28 PM PDT 24	7437940920 ps
T746	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2345836755			Jul 14 08:23:11 PM PDT 24	Jul 14 08:32:50 PM PDT 24	4066622774 ps