Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	140742	1			T85	110		T86	61		T89	11
values[2]	8924	1			T85	2		T86	3		T486	10
values[3]	3352	1			T547	1		T426	1		T545	1
values[4]	2077	1			T547	1		T426	3		T545	1
values[5]	1433	1			T547	1		T426	3		T545	1
values[6]	998	1			T547	1		T426	1		T545	1
values[7]	707	1			T547	1		T426	2		T545	1
values[8]	630	1			T547	2		T426	6		T545	1
values[9]	545	1			T547	1		T426	8		T545	1
values[10]	460	1			T547	1		T426	16		T545	1
values[11]	447	1			T547	1		T426	2		T545	1
values[12]	461	1			T547	1		T426	2		T545	1
values[13]	372	1			T547	1		T426	1		T545	1
values[14]	444	1			T547	1		T426	1		T545	2
values[15]	414	1			T547	1		T426	3		T545	1
values[16]	407	1			T547	1		T426	3		T545	1
values[17]	332	1			T547	1		T426	2		T545	1
values[18]	367	1			T547	1		T426	1		T545	1
values[19]	338	1			T547	1		T426	2		T545	1
values[20]	318	1			T547	1		T426	1		T545	1
values[21]	290	1			T547	1		T426	13		T545	1
values[22]	331	1			T547	1		T426	17		T545	1
values[23]	352	1			T547	1		T426	5		T545	1
values[24]	334	1			T547	1		T426	1		T545	1
values[25]	348	1			T547	1		T426	1		T545	1
values[26]	324	1			T547	1		T426	2		T545	1
values[27]	342	1			T547	1		T426	2		T545	1
values[28]	319	1			T547	1		T426	7		T545	1
values[29]	358	1			T547	1		T426	3		T545	1
values[30]	332	1			T547	1		T426	2		T545	1
values[31]	303	1			T547	1		T426	1		T545	1
values[32]	282	1			T547	1		T426	2		T545	1
values[33]	301	1			T547	1		T426	2		T545	1
values[34]	390	1			T547	1		T426	1		T545	1
values[35]	271	1			T547	1		T426	1		T545	1
values[36]	284	1			T547	1		T426	2		T545	1
values[37]	265	1			T547	1		T426	1		T545	1
values[38]	256	1			T547	1		T426	3		T545	1
values[39]	310	1			T547	1		T426	1		T545	1
values[40]	272	1			T547	1		T426	1		T545	1
values[41]	299	1			T547	1		T426	4		T545	1
values[42]	279	1			T547	1		T426	1		T545	1
values[43]	257	1			T547	1		T426	3		T545	1
values[44]	263	1			T547	1		T426	3		T545	1
values[45]	287	1			T547	1		T426	3		T545	1
values[46]	244	1			T547	1		T426	4		T545	1
values[47]	310	1			T547	1		T426	4		T545	1
values[48]	261	1			T547	1		T426	7		T545	1
values[49]	314	1			T547	1		T426	14		T545	1
values[50]	250	1			T547	2		T426	7		T545	1
values[51]	292	1			T547	2		T426	5		T545	1
values[52]	249	1			T547	1		T426	5		T545	1
values[53]	228	1			T547	1		T426	6		T545	1
values[54]	243	1			T547	1		T426	1		T545	1
values[55]	225	1			T547	1		T426	5		T545	1
values[56]	227	1			T547	1		T426	2		T545	1
values[57]	223	1			T547	1		T426	2		T545	1
values[58]	173	1			T547	1		T426	1		T545	1
values[59]	209	1			T547	1		T426	2		T545	1
values[60]	224	1			T547	1		T426	4		T545	1
values[61]	170	1			T547	1		T426	2		T545	1
values[62]	173	1			T547	1		T426	2		T545	1
values[63]	156	1			T547	1		T426	2		T545	1
values[64]	129	1			T547	1		T426	5		T545	1
values[65]	139	1			T547	1		T426	14		T545	1
values[66]	141	1			T547	1		T426	6		T545	1
values[67]	172	1			T547	1		T426	16		T545	1
values[68]	148	1			T547	1		T426	21		T545	1
values[69]	137	1			T547	1		T426	14		T545	1
values[70]	158	1			T547	1		T426	8		T545	1
values[71]	155	1			T547	1		T426	15		T545	1
values[72]	149	1			T547	1		T426	18		T545	1
values[73]	113	1			T547	1		T426	9		T545	1
values[74]	131	1			T547	1		T426	14		T545	1
values[75]	97	1			T547	1		T426	7		T545	1
values[76]	138	1			T547	1		T426	21		T545	1
values[77]	137	1			T547	1		T426	15		T545	2
values[78]	111	1			T547	1		T426	15		T545	1
values[79]	68	1			T547	1		T426	7		T545	1
values[80]	67	1			T547	1		T426	2		T545	1
values[81]	67	1			T547	1		T426	1		T545	1
values[82]	61	1			T547	1		T545	1		T488	1
values[83]	53	1			T547	1		T545	1		T488	1
values[84]	69	1			T547	1		T545	1		T488	1
values[85]	81	1			T547	1		T545	1		T488	1
values[86]	82	1			T547	1		T545	1		T488	1
values[87]	72	1			T547	1		T545	1		T488	1
values[88]	48	1			T547	1		T545	1		T488	1
values[89]	54	1			T547	1		T545	1		T488	1
values[90]	50	1			T547	1		T545	1		T488	1
values[91]	65	1			T547	1		T545	1		T488	1
values[92]	68	1			T547	1		T545	1		T488	1
values[93]	57	1			T547	1		T545	1		T488	1
values[94]	61	1			T547	1		T545	1		T488	1
values[95]	57	1			T547	1		T545	2		T488	1
values[96]	72	1			T547	1		T545	1		T488	1
values[97]	55	1			T547	1		T545	4		T488	1
values[98]	67	1			T547	1		T545	6		T488	1
values[99]	71	1			T547	1		T545	2		T488	1
values[100]	69	1			T547	1		T545	2		T488	1
values[101]	61	1			T547	1		T545	1		T488	1
values[102]	74	1			T547	1		T545	5		T488	1
values[103]	68	1			T547	1		T545	2		T488	1
values[104]	66	1			T547	1		T545	1		T488	1
values[105]	62	1			T547	1		T545	3		T488	1
values[106]	53	1			T547	1		T545	2		T488	1
values[107]	80	1			T547	1		T545	2		T488	1
values[108]	73	1			T547	1		T545	3		T488	1
values[109]	57	1			T547	1		T545	2		T488	1
values[110]	63	1			T547	1		T545	2		T488	1
values[111]	70	1			T547	1		T545	1		T488	2
values[112]	59	1			T547	1		T545	2		T488	2
values[113]	62	1			T547	1		T545	1		T488	1
values[114]	50	1			T547	1		T545	1		T488	1
values[115]	62	1			T547	3		T545	1		T488	2
values[116]	73	1			T547	8		T545	1		T488	1
values[117]	60	1			T547	1		T545	2		T488	1
values[118]	57	1			T547	3		T545	1		T488	1
values[119]	44	1			T547	2		T545	3		T488	1
values[120]	41	1			T547	2		T545	1		T488	1
values[121]	52	1			T547	2		T545	1		T488	3
values[122]	70	1			T547	2		T545	1		T488	3
values[123]	57	1			T547	4		T545	1		T488	2
values[124]	46	1			T547	1		T545	1		T488	1
values[125]	67	1			T547	1		T545	1		T488	3
values[126]	91	1			T547	4		T545	2		T488	2
values[127]	642	1			T547	38		T545	31		T488	23
values[128]	5490	1			T547	367		T545	321		T488	278