Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	136505	1			T85	101		T86	57		T87	1
values[2]	9193	1			T85	2		T86	3		T87	1
values[3]	3668	1			T87	1		T828	107		T547	2
values[4]	2353	1			T87	1		T828	72		T547	3
values[5]	1560	1			T87	1		T828	39		T547	2
values[6]	988	1			T87	1		T828	23		T547	2
values[7]	797	1			T87	1		T828	6		T547	2
values[8]	612	1			T87	1		T828	3		T547	2
values[9]	508	1			T87	1		T547	2		T551	1
values[10]	527	1			T87	1		T547	2		T551	1
values[11]	399	1			T87	1		T547	2		T551	1
values[12]	373	1			T87	1		T547	2		T551	1
values[13]	410	1			T87	1		T547	3		T551	1
values[14]	373	1			T87	1		T547	2		T551	1
values[15]	318	1			T87	1		T547	2		T551	1
values[16]	334	1			T87	1		T547	3		T551	1
values[17]	306	1			T87	1		T547	2		T551	1
values[18]	354	1			T87	1		T547	2		T551	1
values[19]	317	1			T87	1		T547	2		T551	1
values[20]	277	1			T87	1		T547	2		T551	1
values[21]	293	1			T87	1		T547	2		T551	1
values[22]	270	1			T87	1		T547	2		T551	1
values[23]	285	1			T87	1		T547	2		T551	1
values[24]	313	1			T87	1		T547	2		T551	1
values[25]	289	1			T87	1		T547	2		T551	1
values[26]	262	1			T87	1		T547	2		T551	1
values[27]	301	1			T87	1		T547	2		T551	1
values[28]	299	1			T87	1		T547	2		T551	1
values[29]	299	1			T87	1		T547	2		T551	1
values[30]	293	1			T87	1		T547	2		T551	1
values[31]	293	1			T87	1		T547	2		T551	2
values[32]	277	1			T87	1		T547	2		T551	1
values[33]	272	1			T87	1		T547	2		T551	1
values[34]	361	1			T87	1		T547	2		T551	1
values[35]	301	1			T87	1		T547	2		T551	1
values[36]	270	1			T87	1		T547	2		T551	1
values[37]	272	1			T87	1		T547	2		T551	1
values[38]	315	1			T87	1		T547	2		T551	1
values[39]	307	1			T87	1		T547	2		T551	1
values[40]	339	1			T87	1		T547	3		T551	1
values[41]	270	1			T87	1		T547	2		T551	1
values[42]	236	1			T87	1		T547	2		T551	1
values[43]	286	1			T87	1		T547	2		T551	1
values[44]	268	1			T87	1		T547	2		T551	1
values[45]	277	1			T87	1		T547	2		T551	1
values[46]	270	1			T87	1		T547	2		T551	1
values[47]	269	1			T87	1		T547	2		T551	1
values[48]	234	1			T87	1		T547	2		T551	1
values[49]	212	1			T87	1		T547	2		T551	1
values[50]	271	1			T87	1		T547	2		T551	1
values[51]	256	1			T87	1		T547	3		T551	1
values[52]	246	1			T87	1		T547	3		T551	1
values[53]	251	1			T87	1		T547	2		T551	1
values[54]	219	1			T87	1		T547	2		T551	2
values[55]	248	1			T87	1		T547	2		T551	1
values[56]	213	1			T87	1		T547	2		T551	1
values[57]	230	1			T87	1		T547	2		T551	1
values[58]	225	1			T87	1		T547	2		T551	1
values[59]	241	1			T87	1		T547	2		T551	1
values[60]	247	1			T87	1		T547	2		T551	1
values[61]	267	1			T87	1		T547	2		T551	1
values[62]	228	1			T87	1		T547	2		T551	1
values[63]	247	1			T87	1		T547	2		T551	1
values[64]	211	1			T87	1		T547	2		T551	1
values[65]	185	1			T87	1		T547	2		T551	1
values[66]	153	1			T87	1		T547	2		T551	1
values[67]	173	1			T87	1		T547	2		T551	1
values[68]	146	1			T87	1		T547	2		T551	1
values[69]	132	1			T87	1		T547	2		T551	1
values[70]	102	1			T87	1		T547	3		T551	1
values[71]	109	1			T87	1		T547	2		T551	1
values[72]	95	1			T87	1		T547	2		T551	1
values[73]	81	1			T87	1		T547	2		T551	1
values[74]	57	1			T87	1		T547	2		T551	1
values[75]	60	1			T87	1		T547	2		T551	1
values[76]	62	1			T87	1		T547	2		T551	1
values[77]	73	1			T87	1		T547	2		T551	1
values[78]	51	1			T87	1		T547	2		T551	1
values[79]	52	1			T87	1		T547	2		T551	1
values[80]	57	1			T87	1		T547	2		T551	1
values[81]	54	1			T87	1		T547	2		T551	1
values[82]	69	1			T87	1		T547	2		T551	1
values[83]	69	1			T87	1		T547	2		T551	1
values[84]	64	1			T87	1		T547	2		T551	1
values[85]	68	1			T87	1		T547	2		T551	1
values[86]	68	1			T87	1		T547	2		T551	1
values[87]	66	1			T87	1		T547	2		T551	1
values[88]	53	1			T87	1		T547	2		T551	1
values[89]	44	1			T87	1		T547	2		T551	1
values[90]	68	1			T87	1		T547	2		T551	1
values[91]	62	1			T87	1		T547	3		T551	1
values[92]	59	1			T87	1		T547	6		T551	1
values[93]	71	1			T87	1		T547	2		T551	1
values[94]	53	1			T87	1		T547	3		T551	1
values[95]	76	1			T87	1		T547	10		T551	1
values[96]	64	1			T87	1		T547	7		T551	1
values[97]	71	1			T87	1		T547	12		T551	7
values[98]	70	1			T87	1		T547	12		T551	6
values[99]	80	1			T87	2		T547	6		T551	1
values[100]	71	1			T87	1		T547	7		T551	1
values[101]	65	1			T87	2		T547	3		T551	2
values[102]	88	1			T87	1		T547	10		T551	6
values[103]	79	1			T87	4		T547	7		T551	3
values[104]	92	1			T87	3		T547	10		T551	7
values[105]	73	1			T87	5		T547	2		T551	3
values[106]	78	1			T87	7		T547	2		T551	1
values[107]	79	1			T87	3		T547	3		T551	6
values[108]	73	1			T87	6		T547	4		T551	1
values[109]	71	1			T87	2		T547	2		T551	6
values[110]	81	1			T87	1		T547	4		T551	1
values[111]	78	1			T87	5		T547	6		T551	2
values[112]	88	1			T87	10		T547	3		T551	5
values[113]	92	1			T87	6		T547	6		T551	2
values[114]	72	1			T87	1		T547	3		T551	1
values[115]	85	1			T87	1		T547	11		T551	1
values[116]	94	1			T87	5		T547	7		T551	2
values[117]	92	1			T87	3		T547	5		T551	1
values[118]	95	1			T87	2		T547	3		T551	2
values[119]	103	1			T87	1		T547	4		T551	2
values[120]	85	1			T87	1		T547	5		T551	2
values[121]	83	1			T87	5		T547	3		T551	1
values[122]	78	1			T87	1		T547	5		T551	4
values[123]	92	1			T87	1		T547	9		T551	2
values[124]	100	1			T87	1		T547	6		T551	4
values[125]	115	1			T87	1		T547	6		T551	1
values[126]	191	1			T87	6		T547	10		T551	2
values[127]	998	1			T87	16		T547	54		T551	34
values[128]	8510	1			T87	261		T547	559		T551	261